JPH0789572B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention a. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a deep depletion type insulated gate field effect transistor (hereinafter referred to as a deep depletion Tr).

B. Conventional technology MOSFET (Metal Oxide Semiconductor Field Effect)
In the case of a P-channel type, a transistor usually uses an N-type substrate as a substrate and forms P ⁺ -type source and drain regions on the N-type substrate. However, SOS (Silicon
When the substrate itself can be made very thin as in the on Sapphire structure, for example, as shown in FIG.
The P-type single crystal silicon layer 2 grown above can be used as a substrate. The SOS structure MOSFET shown in Fig. 10 has P
^{A −} type substrate 2 has a P ⁺ type source region 3 and a drain region 4, and a gate electrode 7 is provided on a channel region 5 between these regions via a gate oxide film 6. This is called the so-called deep depletion Tr, SR
Detailed analysis by Hofstein [IEEE TRANSACTIONS OF ELECTRON
DEVICES), VOL.ED-13, NO.12, DECEMBER 1966].

In this P-type deep depletion transistor, the source voltage is generally V _DD . However, since the substrate potential is determined by the current flowing through the substrate, it has a gradient in the channel direction, but is V _DD at the maximum. Further, assuming that the drain voltage is 0V, the substrate potential near the drain region is 0V. If the gate voltage is assumed to be 0V, no depletion layer is generated in the substrate due to the gate voltage, and this transistor operates as a resistor. However, when the gate voltage is gradually increased, a depletion layer is first generated in the vicinity of the drain region in the substrate, which narrows the current path in the channel region and reduces the source / drain current. In this case, for example, even if the gate voltage is increased to 5V, the substrate potential is 5V (= V _DD ) in the vicinity of the source region, so that the depletion layer does not extend there.

The present inventor has arrived at the following conclusion as a result of devising whether or not the current may be completely cut off in the state where the portion not depleted remains near the source region as described above. That is, assuming that the channel region is completely blocked before the depletion layer reaches the source region and the current is cut off (pinch off), the potential at the position where the end of the depletion layer faces the source region is 5V. It should be. However, if this potential is 5 V, the gate voltage is also 5 V, or at the same position, there is no effect of the electric field from the gate and depletion does not occur. Therefore, the edge of the depletion layer at the portion facing the source region recedes toward the drain region. This retreat continues until the substrate current begins to flow and the substrate potential begins to drop. That is, when the gate potential is equal to or less than the source potential, the saturation current always flows.

Therefore, in the P-type deep depletion transistor, it is necessary to raise the gate voltage above the source voltage in order to completely cut off the current. For this purpose, a booster circuit for boosting the gate voltage is provided, or three power supplies (for example, 0V, + V _DD , + V) are used for the source, gate and drain.
You must take measures such as making it _DD ). This is no different from the case of using a normal depletion type MOSFET, so effective measures are desired.

C. Object of the invention The object of the present invention is to provide the current of the deep depletion transistor without providing a special step-up (or step-down) circuit and by only supplying two power sources from the outside (for example, 0 V and V _DD ). It is an object of the present invention to provide a semiconductor device capable of completely shutting off.

D. Structure of the Invention That is, the present invention is formed between an insulating substrate, a source region and a drain region of the first conductivity type formed on the substrate and separated from each other, and between the source region and the drain region. A first conductivity type channel region having a lower impurity concentration than the source region and the drain region; a floating gate formed on the channel region via an insulating layer; and an insulating layer on the floating gate via an insulating layer. A source region, the channel region, the drain region, the floating gate, and the control gate, the depletion-type insulated gate field effect transistor is formed, and the floating gate has the source region. And the voltage applied to the control gate is almost the same At this time, the present invention relates to a semiconductor device in which carriers are injected so that the current flowing in the channel region is completely cut off.

The present invention also provides, as a second invention, a first-conductivity-type semiconductor substrate, and a second-conductivity-type first source region and a first-drain region formed on one main surface of the semiconductor substrate so as to be separated from each other. A control gate formed on the first channel region between the first source region and the first drain region via an insulating layer, and a floating gate formed on the control gate via the insulating layer. Formed between the second source region and the second drain region of the first conductivity type and the second source region and the second drain region which are formed on the floating gate and are separated from each other with an insulating layer interposed therebetween. The second source region and the second channel region of the first conductivity type having an impurity concentration lower than that of the second drain region, and the first source region and the first channel region A second conductivity type insulated gate field effect transistor is constituted by the rain region and the control gate, and the first conductivity is constituted by the second source region, the second channel region, the second drain region, the floating gate and the control gate. Type depletion-type insulated gate field effect transistor is configured, and a current flowing in the second channel region is applied to the floating gate when the voltages applied to the second source region and the control gate are substantially the same. The present invention relates to a semiconductor device in which carriers are injected so as to be completely cut off.

E. Embodiments Embodiments of the present invention will be described in detail below with reference to FIGS. 1 to 9.

1 to 3 show a first embodiment in which the present invention is applied to a P-channel type deep depletion Tr having an SOS structure.

First, the structure of the semiconductor device according to this embodiment will be described. An P ^- type single crystal silicon layer 12 with an impurity concentration of 10 ¹⁴ to 10 ¹⁶ / cm ³ grown on one main surface of an insulating substrate, for example, a sapphire substrate 11. Further, a P ⁺ type source region 13 and a drain region 14 having an impurity concentration of 10 ²¹ to 10 ²² pieces / cm ³ are formed. Then, adjacent to the source region 13, the impurity concentration is 10 ²¹ to 10 ²²
An N ⁺ type carrier injection region (hereinafter referred to as an injector) 20 of / cm ³ is formed. Also, the channel region 15
And the source region 13, and further the source region 13-injector
A gate oxide film 16 and a floating gate 18 are provided so as to cover the PN junction 21 between 20 and a control gate 17 is provided on the floating gate 18 via an oxide film 19. Electrodes 22 and 23 are deposited on the drain region 14 and the injector 20, respectively, and a predetermined potential is applied thereto. An electrode (not shown) is also deposited on the source region 13 to apply a predetermined potential. Further, in the figure, 24 is an insulating film (oxide film) on the gate surface, and 25 is a field oxide film.

The P-channel type deep depletion transistor thus configured has a so-called EPROM (erasable programmabl) having a floating gate 18 and a control gate 17.
e read only memory), but with the same structure but with a completely different operation.

When a P-channel type PROM having a floating gate is manufactured similarly to a normal (generally N-channel type) EPROM, writing is performed by injecting holes having a negative potential into the floating gate. The injection of holes utilizes avalanche breakdown near the drain region. On the other hand, in the P-channel type deep depletion transistor based on the present invention illustrated in FIG. 1, holes are injected into the floating gate like EPROM, but the holes are not injected from the drain region but the P ⁺ type source. Region 13 and N ⁺ injector 20
A reverse voltage is applied to the junction (21) and the junction (21) to cause a junction breakdown, and hot carriers generated thereby are injected into the floating gate (18). In this case, the holes to be injected have a positive potential, but the method of injecting such holes has already been confirmed by DIFMOS (Dual Injection Floating Gate MO
S) and its operation has already been confirmed and explained (JP-A-53-108247, JP-A-53-108247).
54-66088, etc.).

In this way, holes having a positive potential are injected into the floating gate 18, so that the gate voltage shifts in the positive direction. For example, when 5V is applied to the control gate 17, the gate voltage seen from the substrate surface rises to 7V. As a result, the gate voltage is increased without providing the gate voltage booster circuit as described above,
It becomes possible to completely deplete the substrate, and it is possible to realize a deep depletion transistor capable of completely interrupting the current so that the substrate current becomes zero. Moreover, the external power supply only requires 0 V and V _DD , and no additional power supply is required.

Next, a method of manufacturing the semiconductor device of this embodiment will be described with reference to FIG.

According to the usual method, first, as shown in FIG. 3A, a P ⁻ type single crystal silicon layer 12 is epitaxially grown on one main surface of the sapphire substrate 11, and then, as shown in FIG. 3B, LOCOS (Local Oxidatio
The field oxide film 25 is selectively grown by the n of silicon) method to form an element region.

Next, as shown in FIG. 3C, a P ⁺ type source region 13 and a drain region 14 are formed in the silicon layer 12 by a known ion implantation technique, and further an N ⁺ type injector 20 is formed. At this time, for example, boron ions 26 are implanted for the source and drain regions, and phosphorus ions 27 are implanted for the injector.

Then, as shown in FIG. 3D, a gate oxide film 16 is formed on the surface of the silicon layer 12 by a conventional method, and an impurity-doped polysilicon layer 18, a SiO ₂ film 19, and an impurity-doped polysilicon layer 17 are further formed on the entire surface. Sequentially formed by the CVD (Chmical Vapor Deposition) method.

Further, as shown in FIG. 3E, the polysilicon layer 17, the SiO ₂ film 19, the polysilicon layer 18 and the gate oxide film 16 are etched into a predetermined pattern, and then the SiO ₂ film 24 is deposited by the CVD method.
Then, contact holes in each region are formed by photo-etching, and the electrodes (and wirings) are formed as shown in FIG. 1 by vapor deposition and patterning of an electrode material such as aluminum.
To form.

4 to 9 show a second embodiment in which the present invention is applied to a three-dimensional IC.

As shown in FIGS. 4 and 5, the semiconductor device according to this embodiment basically uses N ⁺ type semiconductor regions 33 and 34 formed on one main surface side of the P ⁻ type silicon substrate 31 as sources. Region and drain region and on the gate oxide film 36 a gate electrode
A normal N-channel MOSFET having 37 and the above-mentioned first
The P ⁺ type source region 4 is formed in the P ⁻ type silicon layer 42 as in the embodiment of FIG.
3. A P-channel type deep depletion transistor Tr having a drain region 44 and an N ⁺ type injector 50 and having a floating gate 48 and a control gate 37 is laminated under the silicon layer 42. Both of these transistors have a common gate 37 and drain regions 34-44.
The wires 52 are electrically connected to each other by the wiring 52.
An inverter circuit as shown in the figure can be constructed.
In the figure, 47 and 57 are source electrodes, and 53 is an injector electrode. Further, 49 and 54 are oxide films corresponding to 19 and 24 in FIG. 1, 56 is a similar oxide film, and 55 is a surface oxide film of silicon.

The impurity concentration of each of the above regions 43, 44, 50 is as described above.
It may be the same as 13, 14, 20.

According to the three-dimensional IC configured as described above, the above-mentioned first
Similarly to the embodiment described above, positive potential holes are injected by avalanche breakdown by the reverse voltage applied to the PN junction 51 between the source region 43 and the injector 50 with respect to the floating gate 48 of the P channel type deep depletion Tr. However, the channel region 45 can be completely turned off. The injection of holes into the floating gate is the same as in the examples of FIGS. 1 to 3 described above,
If it is done by the manufacturer at the manufacturing stage of this transistor, it is unnecessary after that. Therefore, when using it, it is possible for the manufacturer to make V _{INJ the} same as V _DD in advance (therefore, when using, V _INJ is unnecessary),
Unlike EPROM, it is not necessary for the user to consider erasing or writing the stored charge in the gate. Therefore, the data retention time can be designed to be sufficiently long. That is, in an EPROM or the like, the longer the data retention time, the longer the writing time, and thus the retention time cannot be set longer than necessary. However, in the device according to the present embodiment, the retention time is sufficiently long for the above reason. There is no problem even if you leave it.

Further, since the three-dimensional IC structure according to the present embodiment has semiconductor elements stacked on the substrate, the degree of integration is improved and the chip size can be reduced as compared with the two-dimensional IC. However, it is generally said that a major obstacle to realizing a three-dimensional IC is a method of manufacturing a second layer substrate. In FIG. 4, one method is to recrystallize the once grown polysilicon layer by laser annealing when forming the silicon layer 42 as the second substrate as single crystal silicon. As a typical method, there is a method of forming a substrate that is so-called pseudo-single-crystallized, rather than forming complete single-crystal silicon. In this case, the polysilicon layer is annealed in a hydrogen atmosphere so that the islands of the polysilicon are filled with hydrogen atoms. Although this is a method of making the manufacturing cost very low, it tends to cause a large leak current at the PN junction as compared with pure single crystal silicon.

However, in the structure of FIG. 4 according to this example, when the substrate 42 is formed by applying the above method, this is used for the deep depletion Tr of the second layer, so that the leak current is very small. That is, in the deep depletion transistor of this example, there is only one PN junction between the source region 43 and the injector 50 (51 in FIG. 4), but this injector potential (V _INJ ) is the source during operation. Since the potential (V _DD ) may be used, no leak current is generated in the PN junction 51. Further, in the current cutoff mode of this transistor, since the channel region 45 is depleted over the entire region, even if the crystal structure of the silicon layer 42 is partially collapsed, its influence is greater than that at the PN junction surface. Less is. Therefore, with the structure of this example, the leakage current is significantly reduced, and a high-performance three-dimensional IC can be realized.

Also, in a three-dimensional IC, since the substrate is in a floating state, it is known that a drain current distortion called a kink phenomenon occurs. However, according to the deep depletion transistor of this example, the substrate 42 becomes the source potential, the drain potential, or an intermediate potential between them, and does not enter into a floating state, so that an unstable phenomenon such as a kink phenomenon does not occur.

Next, a method of manufacturing the three-dimensional IC according to this example will be described with reference to FIG.

First, as shown in FIG. 7A, a gate oxide film 36 is grown on one main surface of a P ⁻ type silicon substrate 31 by a thermal oxidation method, and a CV film is formed on the gate oxide film 36.
Impurity-doped polysilicon layer 37 and SiO ₂ film 4 by D method
9. Impurity-doped polysilicon layer 48 is sequentially formed.

Then, as shown in FIG. 7B, each layer 48, 49, 37, 36 is etched into a predetermined pattern to form a gate region, and the N ⁺ type source region is diffused by impurity diffusion by the cell alignment technique using the gate as a mask. 33 and the drain region 34 are formed.

Next, as shown in FIG. 7C, an oxide film 54 is formed by the CVD method, and a P ⁻ -type polysilicon layer 42 is further grown thereon.
The polysilicon layer 42 is preferably annealed in a hydrogen atmosphere after completing all the high temperature heating steps as described above.

Then, as shown in FIG. 7D, ion implantation of each impurity is performed in the same manner as described above, and the P ⁺ type source region 43 and the drain region are formed.
44, N ⁺ type injector 50 is formed, and then silicon layer 42 is patterned by photoetching. And
As shown in FIG. 4, contact holes are opened in the oxide film 56 formed on the entire surface, and a wiring material is deposited and then patterned to form each wiring.

FIG. 8 and FIG. 9 show another embodiment of the three-dimensional IC, but the portions common to the example of FIG. 4 are given common reference numerals and the description thereof may be omitted.

The semiconductor device according to this example also constitutes an inverter circuit, but is different from the example in FIG. 4 in that it is adjacent to the source region 43.
That is, the N ⁺ type injector is not provided, and the third gate 60 for carrier injection made of impurity-doped polysilicon is provided. An injector voltage (V _INJ ) is applied to this gate 60 via electrode 63, which causes gate 60 to
From the above, positive potential holes are injected into the floating gate 48 through the oxide film 49.

Although the present invention has been illustrated above, the above-described embodiments can be further modified based on the technical idea of the present invention.

For example, in the example of FIGS. 1 and 4 described above, the PN junction 2
The parts 1 and 51 are located inward of the end of the floating gate (specifically, in the example of FIG. 1,
It is necessary for carrier injection that the PN junction 21 is covered by the gate 18. However, the position of the PN junction may be at any position of the gate. Further, it is also possible to inject carriers from the source region by providing V _INJ using the source region itself of the deep depletion _Tr as an injector without providing the carrier injecting means as in the above-mentioned example. Further, in the above example, the P-channel type deep depletion _Tr is described, but the conductivity type of each region can be converted to form the N-channel type deep depletion _Tr . In this N-channel type,
Compared with the P-channel type, it is only necessary to partially change the polarity and the like. The present invention can be applied not only to the three-dimensional IC as described above, but also to other circuits in general.

F. As described above, in the semiconductor device of the present invention, in the depletion type insulated gate field effect transistor, when the voltages applied to the source region and the control gate are substantially the same, the current flowing in the channel region is completely Since the structure is such that carriers are injected into the floating gate so as to be cut off, the current can be completely cut off between the source region and the drain region without raising or lowering the control gate voltage above the power supply voltage. The step-up circuit or step-down circuit can be eliminated.

In addition, such a depletion type insulated gate field effect transistor is provided on the reverse conductivity type insulated gate field effect transistor to form a three-dimensional IC.
High integration and stable operation can be achieved.

[Brief description of drawings]

1 to 9 show an embodiment of the present invention. FIG. 1 is a sectional view of a P-channel type deep depletion _Tr of SOS structure according to the first embodiment, and FIG. _{r is} a plan view, FIG. 3A, FIG. 3B, FIG. 3C, FIG. 3D, and FIG. 3E are sectional views showing the manufacturing method of the same _{Tr in} the order of steps, and FIG. Sectional view of the IC, Fig. 5 is a plan view of the IC, Fig. 6 is an equivalent circuit diagram of the IC, and Figs. 7A, 7B, 7C, and 7D show the manufacturing method of the IC in the order of steps. Sectional views shown in FIG. 8, FIG. 8 is a sectional view of a three-dimensional IC according to the third embodiment, and FIG. 9 is an equivalent circuit diagram of the same IC. FIG. 10 is a sectional view of a P-channel type deep depletion T _r to which the prior art is applied. In the drawing, reference numerals 11 ... Sapphire substrate (insulating substrate) 12, 42 ... P ^- type silicon layer 13, 33, 43 ... Source region 14, 34, 44 ... Drain region 15, 45. Channel regions 17, 37 ... Control gates 18, 48 ... Floating gates 20, 50, 60 ... Injectors.

Claims (2)

[Claims] 1. An insulating substrate, source and drain regions of a first conductivity type formed on the substrate and spaced apart from each other, and the source region formed between the source region and the drain region. A channel region of the first conductivity type having a lower impurity concentration than the drain region, a floating gate formed on the channel region via an insulating layer, and a control formed on the floating gate via an insulating layer. A source region, the channel region, the drain region, the floating gate, and the control gate to form a depletion type insulated gate field effect transistor, and the floating gate includes the source region and the control gate. When the voltage applied to each is almost the same , Wherein a carrier is injected so that the current flowing through the channel region is completely blocked. 2. A first-conductivity-type semiconductor substrate, second-conductivity-type first source regions and first-drain regions formed on one main surface of the semiconductor substrate so as to be separated from each other, and the first source region. And a control gate formed on the first channel region between the first drain region and the first drain region via an insulating layer,
A floating gate formed on the control gate via an insulating layer; a second source region and a second drain region of the first conductivity type formed on the floating gate and spaced apart from each other by an insulating layer; A second channel region of the first conductivity type having a lower impurity concentration than the second source region and the second drain region, the second channel region being formed between the second source region and the second drain region; A first source region, the first channel region, the first
A second conductivity type insulated gate field effect transistor is constituted by the drain region and the control gate, the second source region, the second channel region, and the second region.
The drain region, the floating gate, and the control gate form a depletion-type insulated gate field effect transistor of the first conductivity type, and the floating gate receives a voltage applied to the second source region and the control gate, respectively. A semiconductor device in which carriers are injected so that a current flowing through the second channel region is completely cut off when the same.