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JPH0789575B2 - Printed wiring board for mounting semiconductor chips - Google Patents
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JPH0789575B2 - Printed wiring board for mounting semiconductor chips - Google Patents

Printed wiring board for mounting semiconductor chips

Info

Publication number
JPH0789575B2
JPH0789575B2 JP61285659A JP28565986A JPH0789575B2 JP H0789575 B2 JPH0789575 B2 JP H0789575B2 JP 61285659 A JP61285659 A JP 61285659A JP 28565986 A JP28565986 A JP 28565986A JP H0789575 B2 JPH0789575 B2 JP H0789575B2
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
coating film
semiconductor chip
flow stop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61285659A
Other languages
Japanese (ja)
Other versions
JPS63137460A (en
Inventor
正秀 近藤
裕紀 竹中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP61285659A priority Critical patent/JPH0789575B2/en
Publication of JPS63137460A publication Critical patent/JPS63137460A/en
Publication of JPH0789575B2 publication Critical patent/JPH0789575B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、半導体チップを搭載し、その回りを樹脂材料
で封止する構造の半導体装置に用いるプリント配線板に
関し、特に半導体チップ封止のための樹脂流れ止め枠を
有したプリント配線板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board used in a semiconductor device having a structure in which a semiconductor chip is mounted and the periphery thereof is sealed with a resin material. The present invention relates to a printed wiring board having a resin flow stop frame for.

(従来の技術) プリント配線板に半導体チップを搭載する際、半導体チ
ップを回路パターンと導電接続後、半導体チップを液状
の熱硬化性樹脂で覆い、その後加熱硬化して樹脂封止す
ることが一般的に行なわれている。そのため、この用途
に用いられるプリント配線板には、封止樹脂が不必要な
箇所に広がることの防止と、封止樹脂の高さを十分確保
することによる封止の信頼性の向上を目的として、しば
しば半導体チップを搭載すべき部分の周囲に樹脂流れ止
め枠を設けている。
(Prior Art) When mounting a semiconductor chip on a printed wiring board, it is common to cover the semiconductor chip with a liquid thermosetting resin after conductively connecting the circuit chip to a circuit pattern, and then heat-cure the resin to seal it. Is being carried out. Therefore, the printed wiring board used for this purpose aims to prevent the sealing resin from spreading to unnecessary places and to improve the reliability of the sealing by ensuring a sufficient height of the sealing resin. Often, a resin flow stop frame is provided around the portion where the semiconductor chip is to be mounted.

この枠の形成方法としては、単純には特開昭59−105342
号公報のようにあらかじめ所定の枠形状に成形した枠状
成形体を接着剤を用いて所定の位置に貼り付ければよ
い。しかし、この方法では枠状成形体の形成、貼付の位
置決め、接着など、工程が非常に煩雑であり製品価格的
にも好ましくない。そこで、簡便に流れ止め枠を形成す
る方法として、実公昭49−43873号公報のように、スク
リーン印刷法等を用いて絶縁性樹脂を枠状に塗布、硬化
する方法がある。そして、この方法をさらに改善した方
法が、実開昭55−25381号公報のように、樹脂流れ止め
枠を独立の工程として形成するのではなく、通常用いる
ソルダーレジストを樹脂流れ止め枠として用いる方法で
ある。
As a method for forming this frame, a simple method is disclosed in Japanese Patent Laid-Open No. 59-105342.
As in Japanese Patent Laid-Open Publication No. JP-A No. 2003-187, a frame-shaped molded body previously molded in a predetermined frame shape may be attached to a predetermined position using an adhesive. However, with this method, the steps such as forming the frame-shaped molded body, positioning of pasting, and adhesion are extremely complicated, and the product price is not preferable. Therefore, as a method for easily forming the flow stop frame, there is a method of applying and curing an insulating resin in a frame shape by using a screen printing method or the like, as disclosed in JP-B-49-43873. And, as a method further improving this method, as in Japanese Utility Model Laid-Open No. 55-25381, a method of using a normally used solder resist as a resin flow stop frame rather than forming the resin flow stop frame as an independent step. Is.

ところが、スクリーン印刷法を用いた場合、通常の方法
では1回の印刷で形成できる印刷体の厚みには限界があ
り、場合によっては何回もの印刷、乾燥を繰り返さなけ
れば必要な枠高さが得られない場合がある。その場合、
厚膜配線基板にあっては、特開昭59−117253号公報のよ
うに各厚膜素子の形成工程時に同時に、各厚膜素子と同
一材料の厚膜パターンを積層して膜厚を厚くする方法も
ある。
However, when the screen printing method is used, there is a limit to the thickness of the printed material that can be formed by one printing by the usual method, and in some cases, the required frame height is required unless printing and drying are repeated many times. You may not get it. In that case,
In the case of a thick film wiring board, the thick film pattern made of the same material as each thick film element is laminated at the same time as the thick film element forming process as in JP-A-59-117253 to increase the film thickness. There is also a method.

しかし、特開昭59−117253号公報等において提案されて
いる発明は、あくまでも各厚膜素子と同一材料を使いダ
ム形成の工程を増加させないことが前提となっており、
しかも厚膜材料の電気的特性は問題にしておらず、単に
必要な膜厚を確保することだけが目的となっている。ま
た、このダムの形成目的は、半導体チップ封止樹脂の厚
膜抵抗体部への侵入を防止することであり、半導体チッ
プの樹脂封止を確実にすることを目的としたものではな
い。
However, the invention proposed in Japanese Patent Laid-Open No. 59-117253 is based on the premise that the same material as each thick film element is used and the number of dam formation steps is not increased.
Moreover, the electrical characteristics of the thick film material are not a problem, and the purpose is merely to secure the necessary film thickness. Further, the purpose of forming the dam is to prevent the semiconductor chip sealing resin from entering the thick film resistor portion, and is not intended to ensure the resin sealing of the semiconductor chip.

それよりも重要なことは、以上の各従来技術において
は、樹脂封止の他の部分への流れを確実に防止すること
にしか意を用いていないものであり、樹脂流れ止め枠に
電気的な機能を付加することによってこの種の封止樹脂
流れ止め枠の機能を高めることについては、何等考慮し
ていないことである。
More importantly, in each of the above-mentioned prior arts, only the intention is to reliably prevent the resin sealing from flowing to other parts. No consideration is given to enhancing the function of this kind of sealing resin flow stop frame by adding such a function.

(発明が解決しようとする問題点) 本発明は、以上のような実状に鑑みてなされたものであ
り、その解決しようとする問題点は、従来の封止樹脂流
れ止め枠が、樹脂の流出を単に物理的に防止しているだ
けで、電気回路的には何ら寄与していないこである。
(Problems to be Solved by the Invention) The present invention has been made in view of the above circumstances, and the problem to be solved is that the conventional sealing resin flow stop frame causes resin outflow. Is merely physically prevented, and does not contribute to the electric circuit at all.

そして、本発明の目的とするところは、この種の半導体
チップ搭載用プリント配線板における封止樹脂流れ止め
枠に導電性を付与して、これを回路の一部として利用す
ることであり、このことによってより一層配線の高密度
化、或いは基板の小型化をした半導体チップ搭載用プリ
ント配線板を提供することにある。
Then, an object of the present invention is to impart conductivity to a sealing resin flow stop frame in a semiconductor chip mounting printed wiring board of this type and use this as a part of a circuit. In this way, it is possible to provide a printed wiring board for mounting a semiconductor chip, which has a higher wiring density or a smaller substrate.

(問題点を解決するための手段) 以上の問題点を解決するために、本発明が採った手段
は、実施例に対応する第1図〜第3図を参考にして説明
すると、 「半導体チップ(2)をプリント配線板上に搭載し、該
半導体チップ(2)を連続して囲んで設けた樹脂流れ止
め枠(10)内に封止樹脂(6)を滴下流動させて封止す
る半導体装置において、 樹脂流れ止め枠(10)が抵抗体となる導電性塗膜(1)
で形成され、かつ、絶縁基板(7)上の回路パターン
(3)間を導電性体塗膜(1)で導通接続したことを特
徴とする半導体チップ搭載用プリント配線板」である。
(Means for Solving Problems) In order to solve the above problems, means adopted by the present invention will be described with reference to FIGS. 1 to 3 corresponding to the embodiment. A semiconductor in which (2) is mounted on a printed wiring board, and a sealing resin (6) is dripped and flowed into a resin flow stop frame (10) provided so as to continuously surround the semiconductor chip (2) for sealing. In the equipment, the conductive coating film (1) in which the resin flow stop frame (10) becomes a resistor
And the circuit patterns (3) on the insulating substrate (7) are electrically connected by the conductive material coating film (1) ".

この構成を図面に従って詳細に説明すると、第1図〜第
3図に示すように、回路パターン(3)上に直接導電性
塗膜(1)を連続した枠状に形成して樹脂流れ止め枠
(10)とし、この樹脂流れ止め枠(10)によって、その
本来の樹脂流れ止めを行なうとともに、各回路パターン
(3)間に導電性を付与したものである。
This configuration will be described in detail with reference to the drawings. As shown in FIGS. 1 to 3, a resin coating film is formed by forming a conductive coating film (1) directly on the circuit pattern (3) in a continuous frame shape. (10), the resin flow stop frame (10) is used to perform the original resin flow stop, and conductivity is imparted between the circuit patterns (3).

なお、この半導体チップ搭載用プリント配線板は、第4
図〜第6図に示したように、回路パターン(3)上に絶
縁性塗膜(8)と導電性塗膜(1)を積層することによ
り連続した樹脂流れ止め枠(10)を形成するとともに、
絶縁性塗膜(8)に形成した開口(イ)及び(ロ)を通
して導電性塗膜(1)を回路パターン(3)上に接続し
て部分的な導電性を付与することもできるものである。
また、第7図は、特に厚膜配線基板に本発明を適用する
場合で、各厚膜素子を形成するのと同時に樹脂流れ止め
枠(10)を形成するものであり、この場合の樹脂流れ止
め枠(10)においては、絶縁基板(7)上側の少なくと
も一層が導電性塗膜(1)で形成されている多層塗膜で
あるものである。
The printed wiring board for mounting the semiconductor chip is the fourth
As shown in FIGS. 6 to 6, a continuous resin flow stop frame (10) is formed by laminating an insulating coating film (8) and a conductive coating film (1) on a circuit pattern (3). With
The conductive coating film (1) can be connected to the circuit pattern (3) through the openings (a) and (b) formed in the insulating coating film (8) to impart partial conductivity. is there.
Further, FIG. 7 shows a case where the present invention is applied to a thick film wiring board, in which the resin flow stop frame (10) is formed at the same time when each thick film element is formed. In the stop frame (10), at least one layer on the upper side of the insulating substrate (7) is a multilayer coating film formed of the conductive coating film (1).

(発明の作用) 本発明が以上のような手段を採ることによって以下のよ
うな作用がある。
(Operation of the Invention) The present invention adopts the above-mentioned means and has the following operation.

本発明に係る半導体チップ搭載用プリント配線板におい
ては、第1図〜第3図に示すように、回路パターン上に
直接連続した枠状に形成した導電性塗膜の材料として、
印刷抵抗体用ペーストを用いれば、各回路パターン間に
抵抗器を実装した場合と同等になり、抵抗体付プリント
配線板となる。このときの導電性体塗膜(1)からなる
樹脂流れ止め枠(10)の形成方法は、スクリーン印刷法
を用いても良いし、さらに大きな膜厚を得る必要がある
場合には定量塗出装置を用いた描画法を用いても良い。
また、特に回路上各回路パターン間に抵抗体を設ける必
要がない場合でも、半導体の作動を妨げない程十分大き
な抵抗値をもつ低抗体を回路パターン間に設けた場合に
は、この低抗体が静電気等による半導体の破壊や誤動作
を防止する保護回路となる。
In the printed wiring board for mounting a semiconductor chip according to the present invention, as shown in FIGS. 1 to 3, as a material for a conductive coating film directly formed on a circuit pattern in a continuous frame shape,
If the paste for printed resistors is used, it becomes equivalent to the case where resistors are mounted between the circuit patterns, and the printed wiring board with resistors is obtained. At this time, the resin flow stop frame (10) formed of the conductive coating film (1) may be formed by a screen printing method, or if a larger film thickness is required, a fixed amount is applied. A drawing method using an apparatus may be used.
Even when it is not necessary to provide a resistor between the circuit patterns on the circuit, if a low antibody having a resistance value large enough not to interfere with the operation of the semiconductor is provided between the circuit patterns, the low antibody will be reduced. It serves as a protection circuit that prevents semiconductor damage and malfunction due to static electricity.

また、この半導体性チップ搭載用プリント配線板におい
ては、第4図〜第6図に示すように、回路パターン上に
絶縁性塗膜と導電性塗膜を積層して連続した枠状に形成
すれば、樹脂流れ止め枠(10)が厚膜多層回路における
ジャンパー線となる。もちろん、この部分は、導電性塗
膜の導電性により低抗体にもなることは言うまでもな
い。
Further, in this semiconductor chip mounted printed wiring board, as shown in FIGS. 4 to 6, the insulating coating film and the conductive coating film are laminated on the circuit pattern to form a continuous frame. For example, the resin flow stop frame (10) becomes a jumper wire in the thick film multilayer circuit. Needless to say, this portion also becomes a low antibody due to the conductivity of the conductive coating film.

さらに、第7図に示すように、厚膜配線基板に本発明を
適用すれば、上述した抵抗体、或いはジャンパー線とし
ての機能は、厚膜素子の形成過程で樹脂流れ止め枠(1
0)に付与され、該樹脂流れ止め枠(10)を形成するの
に別の工程を付与する必要がない。さらに厚膜基板にお
いては、塗膜が多層になるのが一般的であり、通常のス
クリーン印刷法を用いても樹脂流れ止め枠(10)として
十分な膜厚となる。
Further, as shown in FIG. 7, when the present invention is applied to a thick film wiring board, the function as the resistor or the jumper wire described above is achieved by the resin flow stop frame (1
No additional step is required to form the resin flow stop frame (10) provided in step (0). Further, in the case of a thick film substrate, the coating film is generally multi-layered, and even if a normal screen printing method is used, the resin flow stop frame (10) has a sufficient film thickness.

以上のように本発明によれば、樹脂流れ止め枠(10)が
単に樹脂の流れ止めの機能だけでなく、抵抗体、ジャン
パー線としても機能する。
As described above, according to the present invention, the resin flow stop frame (10) functions not only as a resin flow stop, but also as a resistor and a jumper wire.

次に、本発明を実施例について説明する。Next, the present invention will be described with reference to examples.

(実施例) 実施例1 第1図〜第3図に示す実施例では、エッチング法により
35μm銅箔にて回路パターン(3)を形成した後、その
表面にニッケル5μm、金0.5μmの電気めっきを施
し、さらにその上に導電塗膜(1)として、スクリーン
印刷法によりシート抵抗値1MΩ/□の樹脂系カーボンペ
ーストを連続した枠状に印刷塗布し、加熱硬化した。こ
の樹脂系カーボンペーストは半導体の保護抵抗としての
機能を目的としたものであり、その導電性の最適値は半
導体チップの特性によって決まるものである。
(Example) Example 1 In the example shown in FIGS. 1 to 3, the etching method was used.
After forming a circuit pattern (3) with 35 μm copper foil, electroplating nickel 5 μm and gold 0.5 μm on the surface, and as a conductive coating film (1) on it, sheet resistance value 1 MΩ by screen printing method. The resin-based carbon paste of / □ was applied by printing in a continuous frame shape and heat-cured. This resin-based carbon paste is intended to function as a protective resistance of the semiconductor, and the optimum value of its conductivity is determined by the characteristics of the semiconductor chip.

実施例2 第4図〜第6図に示す実施例では、実施例1と同様にし
て回路パターン(3)の形成を行った後、ジャンパー線
(2)での導通接続を必要とする回路パターン(3)上
の2点(イ)、(ロ)の部分と、半導体チップを搭載す
べき部分の両者を除いた部分に、通常用いられているエ
ポキシ系ソルダーレジストを用いて、絶縁性塗膜(8)
を形成した。さらに、その枠より若干大きめの枠形状に
導電性塗膜(1)として、樹脂系銀ペーストを印刷塗布
後、加熱硬化した。このとき、該樹脂系銀ペーストはジ
ャンパー線としての機能を目的としたものである。
Example 2 In the example shown in FIGS. 4 to 6, after the circuit pattern (3) is formed in the same manner as in Example 1, the circuit pattern requiring the conductive connection with the jumper wire (2). (3) An insulating coating film is formed by using an epoxy solder resist that is usually used, except for the above two points (a) and (b) and the part where the semiconductor chip is to be mounted. (8)
Was formed. Further, as a conductive coating film (1) having a frame shape slightly larger than the frame, a resin silver paste was applied by printing, and then cured by heating. At this time, the resin-based silver paste is intended to function as a jumper wire.

実施例3 第7図に示す実施例では、実施例1及び2と同様にして
回路パターン(3)の形成を行った後、実施例2と同様
に絶縁性塗膜(8)を形成し、次に印刷抵抗体用の銀電
極を形成するのと同時に銀塗膜(9)を形成する。さら
に、印刷抵抗体形成時にカーボン塗膜(9a)を、印刷抵
抗体の保護膜形成時に再度絶縁性塗膜(8a)を形成す
る。これらの塗膜形成にはすべてスクリーン印刷法を用
いた。また、銀塗膜(9)は実施例2、と同様にジャン
パー回路として機能している。そして樹脂流れ止め枠と
しては、十分な厚みを確保でき特に枠形成のために付与
する工程は不要であった。
Example 3 In the example shown in FIG. 7, after forming the circuit pattern (3) in the same manner as in Examples 1 and 2, the insulating coating film (8) is formed in the same manner as in Example 2. Next, the silver coating film (9) is formed at the same time when the silver electrode for the printed resistor is formed. Further, the carbon coating film (9a) is formed when the printed resistor is formed, and the insulating coating film (8a) is formed again when the protective film of the printed resistor is formed. A screen printing method was used for forming these coating films. Further, the silver coating film (9) functions as a jumper circuit as in the second embodiment. Further, as the resin flow stop frame, a sufficient thickness can be secured, and a step of adding it for forming the frame is unnecessary.

(発明の効果) 以上説明したように、各発明に係る半導体チップ搭載用
プリント配線板によれば、樹脂流れ止め枠が回路パター
ンの一部として使用でき、そして、導電塗膜の材料と形
状に適当なものを選ぶことにより、半導体チップの静電
気破壊防止処理、印刷抵抗体、ジャンパー線等の様々な
機能を付加することができ、プリント配線板の表面の効
率的な利用が可能となる。このことは、プリント配線板
の高密度化と小型化に大きく寄与するものであり、電子
機器の軽薄短小化の要求をよく満たすプリント配線板の
提供が可能となる。
(Effects of the Invention) As described above, according to the semiconductor chip mounting printed wiring board according to each invention, the resin flow stop frame can be used as a part of the circuit pattern, and the material and shape of the conductive coating film can be improved. By selecting an appropriate one, various functions such as the electrostatic breakdown prevention treatment of the semiconductor chip, the printed resistor, the jumper wire and the like can be added, and the surface of the printed wiring board can be efficiently used. This greatly contributes to high density and downsizing of the printed wiring board, and it is possible to provide a printed wiring board that satisfies the requirements of light, thin, short and small electronic devices.

また、本発明を厚膜配線基板に用いれば、スクリーン印
刷法で各素子を基板上に形成していく過程で、同一材料
を用いて同時に樹脂流れ止め枠の形成が可能となり、樹
脂流れ止め枠形成を別の工程として加える必要がなく、
その分安価に回路機能を有する樹脂流れ止め枠付きの半
導体チップ搭載用プリント配線板の提供が可能となる。
Further, when the present invention is applied to a thick film wiring board, it becomes possible to simultaneously form a resin flow stop frame using the same material in the process of forming each element on the board by the screen printing method. There is no need to add the formation as a separate step,
Therefore, it becomes possible to provide a semiconductor chip mounting printed wiring board with a resin flow stop frame having a circuit function at a low cost.

【図面の簡単な説明】[Brief description of drawings]

第1図〜第3図には本発明に係る半導体チップ搭載用プ
リント配線板が示してあり、第1図は当該半導体チップ
搭載用プリント配線板の平面図、第2図及び第3図のそ
れぞれは第1図のX−X及びY−Y線に沿って見た断面
図である。 また、第4図〜第6図は他の実施例に係る半導体チップ
搭載用プリント配線板が示してあり、第4図は当該半導
体チップ搭載用プリント配線板の平面図、第5図及び第
6図のそれぞれは第4図のX−X及びY−Y線に沿って
見た断面図である。 さらに、第7図はさらに他の実施例に係る半導体チップ
搭載用プリント配線板の断面図である。 符号の説明 10……樹脂流れ止め枠、1……導電性塗膜、2……半導
体チップ、3……回路パターン、4……ボンディングワ
イヤ、5……ダイパッド、6……封止樹脂、7……絶縁
基板、8……絶縁性塗膜、9……銀塗膜、9a……カーボ
ン塗膜、8a……絶縁性塗膜、(イ)、(ロ)……回路パ
ターン上へ導通接続すべき部分。
FIGS. 1 to 3 show a semiconductor chip mounting printed wiring board according to the present invention. FIG. 1 is a plan view of the semiconductor chip mounting printed wiring board, FIG. 2 and FIG. 3, respectively. FIG. 3 is a sectional view taken along line XX and YY of FIG. 1. Further, FIGS. 4 to 6 show a semiconductor chip mounting printed wiring board according to another embodiment, and FIG. 4 is a plan view of the semiconductor chip mounting printed wiring board, FIGS. Each of the figures is a cross-sectional view taken along line XX and YY of FIG. Furthermore, FIG. 7 is a cross-sectional view of a semiconductor chip mounting printed wiring board according to still another embodiment. Explanation of reference numerals 10 ... Resin flow stop frame, 1 ... Conductive coating film, 2 ... Semiconductor chip, 3 ... Circuit pattern, 4 ... Bonding wire, 5 ... Die pad, 6 ... Sealing resin, 7 …… Insulating substrate, 8 …… Insulating coating, 9 …… Silver coating, 9a …… Carbon coating, 8a …… Insulating coating, (a), (b) …… Conductive connection on the circuit pattern The part to be done.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】半導体チップをプリント配線板上に搭載
し、該半導体チップを連続して囲んで設けた樹脂流れ止
め枠内に封止樹脂を滴下流動させて封止する半導体装置
において、 前記樹脂流れ止め枠が低抗体となる導電性塗膜で形成さ
れ、かつ、絶縁基板上の回路パターン間を前記導電性体
塗膜で導通接続したことを特徴とする半導体チップ搭載
用プリント配線板。
1. A semiconductor device in which a semiconductor chip is mounted on a printed wiring board, and a sealing resin is dripped and flowed into a resin flow stop frame provided so as to continuously surround the semiconductor chip for sealing. A printed wiring board for mounting a semiconductor chip, characterized in that the anti-flow frame is formed of a conductive coating film which becomes a low antibody, and the circuit patterns on the insulating substrate are electrically connected by the conductive coating film.
【請求項2】前記樹脂流れ止め枠は、前記絶縁基板上側
の少なくとも一層を導電性塗膜で形成した多層塗膜であ
ることを特徴とする特許請求の範囲第1項記載の半導体
チップ搭載用プリント配線板。
2. The semiconductor chip mounting device according to claim 1, wherein the resin flow stop frame is a multilayer coating film in which at least one layer on the upper side of the insulating substrate is formed of a conductive coating film. Printed wiring board.
JP61285659A 1986-11-28 1986-11-28 Printed wiring board for mounting semiconductor chips Expired - Lifetime JPH0789575B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61285659A JPH0789575B2 (en) 1986-11-28 1986-11-28 Printed wiring board for mounting semiconductor chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61285659A JPH0789575B2 (en) 1986-11-28 1986-11-28 Printed wiring board for mounting semiconductor chips

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP4154476A Division JPH065697B2 (en) 1992-05-21 1992-05-21 Printed wiring board for mounting semiconductor chips

Publications (2)

Publication Number Publication Date
JPS63137460A JPS63137460A (en) 1988-06-09
JPH0789575B2 true JPH0789575B2 (en) 1995-09-27

Family

ID=17694397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61285659A Expired - Lifetime JPH0789575B2 (en) 1986-11-28 1986-11-28 Printed wiring board for mounting semiconductor chips

Country Status (1)

Country Link
JP (1) JPH0789575B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10024336A1 (en) * 2000-05-17 2001-11-22 Heidenhain Gmbh Dr Johannes Component arrangement on bearer substrate has two barrier layers of identical material joined in contact region with ratio of barrier height and width between 0.5 and one
WO2019111396A1 (en) * 2017-12-07 2019-06-13 オリンパス株式会社 Method of manufacturing treatment tool and treatment tool

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5037366A (en) * 1973-08-06 1975-04-08
JPS53102375U (en) * 1977-01-21 1978-08-18

Also Published As

Publication number Publication date
JPS63137460A (en) 1988-06-09

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