JPH0789586B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to a field effect semiconductor device having a structure particularly suitable for reducing parasitic resistance.

[Conventional technology]

Conventionally, in a device using a two-dimensional electron gas formed at a heterojunction interface as an active layer of a transistor, reduction of resistance between a source and a gate has been required as a method for improving performance. Therefore, a method of forming the source electrode by self-alignment with the gate electrode is performed. In the GaAs / AlGaAs heterojunction FET, a method of reducing the source-gate resistance by increasing the thickness of the n ⁺ -GaAs cap layer and making the cap layer have a low resistance has been considered. This method aims to reduce the resistance in the region between the source and the gate by using both the two-dimensional electron gas and the bulk electrons in the n ⁺ -GaAs cap layer as carriers for electric conduction. this is,
It is discussed in Proceedings of the Japan Society of Applied Physics 3P-T-11 (April 1986).

[Problems to be solved by the invention]

Wherein n ⁺ -GaAs cap of reduction between the source and the gate resistance due to layer thickening process, in order to reduce the resistance of the n ⁺ -GaAs cap layer itself, had 160nm thickness. Therefore, the ohmic electrode 7 is formed on the n ⁺ -GaAs layer 6 having a thickness of 160 nm (FIG. 2).

Moreover, from the study of ohmic contact with the two-dimensional electron gas, n ⁺
-It has become clear that when the GaAs cap layer has a thickness of 150 nm, the ohmic alloy layer no longer reaches the two-dimensional electron gas layer (Proceedings of the Japan Society of Applied Physics 2p-S-
14 (April 1986)).

Was but connexion, although thickening of the n ⁺ -GaAs cap layer is possible reduce the resistance of the n ⁺ -GaAs cap layer itself, on the contrary, 2
From the standpoint of omnidirectional electron gas, Ga
The ohmic property between the As cap layer and the two-dimensional electron gas is disadvantageous because it does not contribute to the ohmic alloy layer.

Further, in order to increase the breakdown voltage, a structure in which an undoped layer or an n ⁻ layer is provided as a semiconductor layer immediately below the gate is known. In the case of this structure, when an epitaxial crystal is used, the undoped layer or n ⁻ layer is naturally provided below the source electrode and the drain electrode. Therefore, n ⁺
-If the GaAs cap layer is extremely thick, it becomes impossible for the ohmic alloy layer to penetrate the cap layer, and neither the undoped layer nor the n ^- layer penetrates the ohmic alloy layer. Therefore, the existence of the undoped layer or the n ^- layer is 2
There is a problem that the ohmic property to the three-dimensional electron gas is deteriorated, and as a result, it is not useful for reducing the resistance between the source and the gate.

An object of the present invention is to reduce the resistance between the source and the gate by making the ohmic alloy layer reach a gas as a two-dimensional electron while reducing the resistance by increasing the thickness of the cap layer.

[Means for solving problems]

The purpose is to increase the thickness of the n ⁺ cap layer and to
When forming a drain electrode, a hole is formed in the n ^{+ (} cap layer so as not to penetrate the cap layer, in other words, a depth whose depth does not exceed the thickness of the cap layer, and at least a sidewall of the hole). It is achieved by forming an ohmic electrode so as to contact with.

[Action]

FIG. 1 is a sectional view of a FET (field effect transistor) according to the present invention using an AlGaAs / GaAs heterojunction. n ⁺
As in the prior art, the -GaAs cap layer 6 is thickened to reduce the resistance. When the source electrode 7 and the drain electrode 8 are formed, it is necessary to form a hole in the n ⁺ -GaAs cap layer 6 and then form the electrodes 7 and 8 in the hole provided in the cap layer 6 in the two-dimensional electron gas layer. This is to reduce the distance between the electrode and the two-dimensional electron gas layer so that the electric field can be reached by the ohmic alloy layer. The reason why the ohmic electrodes 7 and 8 and the holes provided in the cap layer 6 are formed so as to be in contact with each other without a gap is to prevent the resistance against the current flowing through the lateral n ⁺ cap layer from increasing. .

〔Example〕

 Examples of the present invention will be described below.

EXAMPLE The present invention will be described with reference to FIG. First, on a semi-insulating GaAs substrate 1, an undoped GaAs layer (1 μm) 2 and an undoped Al _X Ga _1-X As layer (with a substrate temperature of 650 ° C.) by a well-known MBE (Molecular Beam Epitaxy) device ( x = 0.3, usually x = 0.2 to about 0.4, thickness 40Å, usually 20Å-60
Å) 3, n ⁺ -AlGaAs layer (concentration: 1.8 × 10 ¹⁸ cm ^-3 , thickness: 350
Å) 4, undoped AlGaAs layer (thickness: 100 Å) 5, n ⁺ −Ga
As layer (concentration: 3 × 10 ¹⁸ cm ^-3 , thickness: 1600 Å) 6, sequentially,
It grows by the epitaxial method.

The undoped AlGaAs layer 5 is a layer in contact with the gate electrode 9, and is provided to suppress the gate leak current and increase the breakdown voltage.

Next, after separating the elements by mesa etching, CVD
A SiO ₂ film (thickness 5000 Å) 10 is formed by the method, and holes for the source electrode 7 and the drain electrode 8 are formed by using a normal photolithography process. First, the method is SiO ₂ After making a hole in 10 using a dry etch, the exposed portion of the n ⁺ -GaAs cap layer 6 is subsequently wet-etched to form a hole having a depth of about 500 Å. At this time, when the film thickness of the n ⁺ -GaAs cap layer 6 is 1600Å, the effect of lowering the resistance appears by etching at a depth of about 300Å or more. Further, SiO ₂ 10 is wet-etched and side-etched so that it is easy to lift off.
Next, Au / Ni / AuGe is vapor-deposited and heat treatment (400 ° C. for 2 minutes) is performed to form the source electrode 7 and the drain electrode 8. Further, a gate pattern is formed by using an EB (electron beam) drawing method. At that time, the n ⁺ -GaAs layer 6 is etched by CCl ₂ F ₂ / He selective dry etching with good controllability, and etching is performed up to the front of the undoped AlGaAs layer 5, and the gate metal is n ^+-.
-GaAs to prevent contact with the cap layer, n ⁺ -GaAs
The cap layer 6 was side-etched to provide a gap 11 of about 0.05 to 0.1 μm. This is a process required to increase the breakdown voltage. A gate electrode 9 having a gate length of 0.3 μm and a gate width of 150 μm is formed by depositing Al and lifting off.
Was formed.

The semiconductor device according to the present embodiment has a withstand voltage: 11 V, gm: 280 ms / m
High performance with m, Rs: 0.8Ω ・ mm, Rc: 0.2Ω ・ mm, and high frequency characteristics at 12GHz: NF (noise figure): 0.
It was 9 dB and Gain: 12 dB.

As the undoped AlGaAs layer 5 immediately below the gate, an n ^-- AlGaAs layer having a thickness of 2 × 10 ¹⁷ cm ^-3 or less may be used as long as the breakdown voltage is not reduced. In this case, the withstand voltage becomes slightly worse, but the source-gate resistance becomes smaller. When the layer directly under the gate is undoped or n ⁻ layer, the ohmic alloy layer does not penetrate into the region between the source electrode and the gate electrode. Therefore, the thickness of the undoped layer 5 is preferably 150 Å or less. However, since it becomes impossible to obtain a high breakdown voltage even if it is too thin, a film thickness of 50 Å or more is required, and the film thickness of the undoped layer 5 is appropriately 50 to 150 Å.

〔The invention's effect〕

According to the present invention, the resistance between the source and gate is reduced by reducing the resistance for two current paths in which the n ⁺ -GaAs layer film forming cap layer and the two-dimensional electrons directly under the electrode are ohmic to 2. Moreover, by providing an undoped or n ^-- AlGaAs layer directly under the gate, and by providing the gate metal and the n ⁺ -GaAs cap layer so as not to contact each other, it is possible to increase the breakdown voltage. This has the effect of achieving high performance of the transistor.

[Brief description of drawings]

FIG. 1 is a sectional view of a transistor according to an embodiment of the present invention, and FIG.
The figure is a cross-sectional view of a conventional transistor. 5 ...... gates just below the undoped (or n ^-) AlGaAs layer, 6
...... n ⁺ -GaAs cap layer, 7,8 ...... source and drain electrodes, 9 ...... gate electrode, 10 ...... SiO ₂ , 11 ...... gap between gate electrode and n ⁺ -GaAs cap layer.

Claims (7)

[Claims] 1. An undoped or low impurity concentration semiconductor film, a cap layer having a high impurity concentration formed on the undoped or low impurity concentration semiconductor film, and a predetermined interval on the cap layer. On the surface of the undoped or low impurity concentration semiconductor film exposed by the source electrode and the drain electrode formed apart from each other and the opening formed in the cap layer between the source electrode and the drain electrode. The gate electrode is formed, and the thickness of the cap layer is larger than the thickness of the cap layer that allows the alloy layer formed under the source electrode and the drain electrode to reach the two-dimensional electron gas layer. And the lower part of the drain electrode are formed in the holes formed in the cap layer so as to be spaced apart from each other. Is less than the film thickness of the cap layer, and the distance between the bottom of the hole and the upper surface of the undoped or low impurity concentration semiconductor film is such that the metal alloy can reach the two-dimensional electron gas layer. A semiconductor device characterized in that the thickness is equal to or less than the layer thickness. 2. The semiconductor device according to claim 1, wherein the cap layer has a thickness of 150 nm or more. 3. The semiconductor device according to claim 1, wherein the distance between the bottom of the hole and the upper surface of the undoped or low impurity concentration semiconductor film is 1300 Å or less. . 4. The semiconductor device according to claim 1, wherein the undoped or low impurity concentration semiconductor film has a thickness of 50Å to 150Å. 5. The impurity concentration of the undoped or low impurity concentration semiconductor film is 2 × 10 ¹⁷ cm ⁻³ or less, according to any one of claims 1 to 4. The semiconductor device described. 6. The semiconductor device according to claim 1, wherein side surfaces of the gate electrode and the opening are separated from each other. 7. The semiconductor device according to any one of claims 1 to 6, wherein the cap layer is made of n-type GaAs.