JPH0789605B2 - MOS amplifier circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an amplifier circuit configured by a MOSFET (insulated gate type field effect transistor), and is used for an amplifier circuit for amplifying an analog signal of a relatively high frequency. It relates to effective technology.

[Background technology]

As an amplifier circuit composed of MOSFETs, there is known a circuit including a differential amplifier circuit and an output MOSFET in which the amplified output is supplied to the gate and an output signal is obtained from the drain (for example, IEE, Journal of , Solid State Circuits (IEEE Journal of Solid-
State Circuits) Vol SC17 No.6 (December 1982) Page 969-
See page 982).

The output MOSFET is provided with a phase compensation circuit including a capacitor and a MOSFET that operates as a resistance element between the gate and the drain that are the input and the output.

However, as is well known, MOSFETs have relatively large process variations in their characteristics. That is, in the power worst state in which the maximum current flows due to process variations, for example, a current twice as much as the design value flows, and in the speed worst state in which the most current does not flow, for example, only half the design value current flows. As a result of the variation in the operating current, the gain itself in the amplifier circuit fluctuates greatly, and as a result, it is difficult to set the constants of capacitors and resistors for phase compensation. You will be compensated. As a result, the speed of the amplifier circuit is increased, in other words,
There arises a problem that the high frequency characteristics are sacrificed.

[Object of the Invention]

An object of the present invention is to provide a MOS amplifier circuit with improved high frequency characteristics.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. Ie MO
The output signal of the differential amplifier circuit composed of SFET is supplied to the gate and the output signal is formed from its drain.
Multiple phase compensation capacitors are formed between the drain and gate of the MOSFET, and they are selectively coupled via a switch circuit according to the process variations to achieve optimum phase compensation. To do.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the present invention. Each circuit element in the figure is formed on a semiconductor substrate such as a single crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal N-type silicon. P-channel MOSFET
Is a gate electrode made of polysilicon formed through a thin gate insulating film on the surface of the semiconductor substrate between the source region and the drain region and between the source region and the drain region. Composed of. The N-channel MOSFET is formed in the P-type well region formed on the surface of the semiconductor substrate. As a result, the semiconductor substrate has a plurality of P-channel MOs formed thereon.
Configure a common substrate gate for SFETs. The P-type well region constitutes the base gate of the N-channel MOSFET formed thereon.

The gates of the N-channel type differential amplification MOSFETs Q3 and Q4 are input terminals (-) and (+), respectively. An N-channel MOSFET Q7 that allows a bias current to flow is provided between the common source of these differential amplification MOSFETs Q3 and Q4 and the ground potential point of the circuit. Between the drains of the differential amplification MOSFETs Q3 and Q4 and the current voltage Vcc, P-channel load MOSFETs Q5 and Q6 in a current mirror form are provided.

The drain output of the amplification MOSFET Q4 is supplied to the gate of a P-channel type output MOSFET Q8. This output MOSFET Q8
N-channel MOSFET Q9 as a constant current load that flows the bias current between the drain of the
Is provided.

The MOSFETs Q7 and Q9 are operated by the bias current formed by the following bias circuit. That is, P-channel MOSFET Q1 and N-channel in series form
The MOSFET Q2 has its gate connected to the connection point of both MOSFETs Q1 and Q2 so that a bias current flows. The N-channel MOSFET Q2 is the MOSFET Q7 and Q9.
With the current mirror configuration, MOSF to MOSFET Q2
A bias current according to the size (conductance) ratio of ETQ7 and Q9 is made to flow through the MOSFETs Q7 and Q9.

A phase compensation circuit PC is provided between the gate and drain (nodes N1 and N2) that are the input and output of the output MOSFET Q8.

FIG. 2 shows a concrete example circuit of the phase compensation circuit PC.

In this embodiment, the MOS amplifier circuit is used as an analog / digital conversion circuit formed in a coder / decoder (CODEC) in a digital telephone exchange. In consideration of process variations in the amplifier circuit shown in FIG. 1, a plurality of phase compensating capacitors C1 to Cn and a plurality of sets of switches S1 and S1 'to selectively couple the capacitors C1 to Cn to the nodes N1 and N2, respectively. Sn and Sn ′ are provided. The switches S1 and S1 'are not particularly limited, but as shown in FIG. 3, an N-channel MOSFET Q10 and a P-channel MOSFET Q10 are provided.
11 and N channel MOSFET Q12 and P channel MOSFET Q13
A complementary transmission gate MOSFET consisting of is used. The inverter circuit IV forms a control signal for the P-channel MOSFETs Q11 and Q13. Other switches S2, S2 'or S
Each of n and Sn ′ is also composed of a MOSFET having the same configuration as described above.
When these MOSFETs are turned on, their on resistance (conductance) causes capacitors C1 to Cn to
Together with this, a phase compensation circuit is configured.

The following circuits are provided to automatically control the switches according to process variations.

The odd-numbered CMOS inverter circuits are connected in a ring-shaped cascade to form the oscillation circuit OSC. The oscillation frequency of the oscillation circuit OSC is set to a frequency according to process variations. That is, the oscillation frequency is increased in the power worst state, and the oscillation frequency is decreased in the speed worst state. The oscillation output of the oscillator circuit OSC is input to the counter circuit COUNT. Counter circuit COUNT
Is reset by the synchronization signal SYS, counts the oscillation output until the timing signal T generated after a fixed time is input with the synchronization signal SYS as a reference, and sends the counted output. Thereby, the variation of the oscillation frequency according to the process variation is determined by the counter circuit COUNT. The count output is held by the latch circuit FF, and a control signal for turning on / off the switch is formed. As a result, the optimum phase compensating circuit according to each process variation is selected. By selecting the phase compensation circuit according to the count output held in the latch circuit, it is possible to prevent the occurrence of noise such as field through generated by switching the switch during the operation period of the amplifier circuit.

As the synchronization signal SYS, a reference signal supplied when the CODEC is activated is used. Further, as the timing signal T, a count output of a clock signal formed by a PLL (phase locked loop) circuit based on the reference frequency signal is used.

The control signal for the switch may be formed by decoding the count output held in the latch circuit FF by a decoding circuit formed of a combination of predetermined logic gate circuits.

〔effect〕

(1) Optimum phase compensation can be performed by preparing a plurality of types of phase compensation circuits and selectively coupling them according to the process variation of the amplifier circuit to which they are coupled. . As a result, there is an effect that the speed can be increased, that is, the high-frequency characteristic can be improved, without performing excessive phase compensation in consideration of the process variation as in the conventional case.

(2) The oscillation frequency of the ring oscillator formed in the same semiconductor integrated circuit is determined, and the phase compensation circuit is selected to automatically and accurately perform phase compensation that follows changes in temperature and power supply fluctuations. The effect of being able to do is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, in a differential amplifier circuit, an additional circuit such as a capacitor is provided between the gate of the load MOSFET in the current mirror form and the ground potential point of the circuit in order to increase the power supply ripple rejection ratio. May be Further, the reference time signal for identifying the oscillation frequency uses not only a control timing signal given from the outside but also a constant current is formed to charge or discharge the capacitor to identify its voltage. Anything may be used.

[Field of application]

The present invention constitutes, for example, a digital telephone exchange device.
It can be widely used for MOS amplifier circuits such as CODEC.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing one embodiment of the phase compensation circuit, and FIG. 3 is a circuit diagram showing one embodiment of the switch. is there. PC: Phase compensation circuit, COUNT: Counter circuit, OSC:
Ring oscillator, FF ... Latch circuit

Claims (1)

[Claims] 1. A differential amplifier circuit composed of MOSFETs,
The output signal of this differential amplifier circuit is supplied to the gate and is provided between the output MOSFET that forms the output signal from the drain and the gate and drain of this output MOSFET, and each is connected through multiple switch MOSFETs. And a ring oscillator including a plurality of capacitors that perform a phase compensation operation together with the on-resistance value of the corresponding switch MOSFET, and an odd number of inverter circuits formed by the MOSFET and formed in the same semiconductor integrated circuit as the MOS amplifier circuit. A MOS amplifier circuit comprising: a counter circuit that counts the oscillation output of the ring oscillator within a fixed period of time; and a control signal for the switch MOSFET is formed based on the count output of the counter circuit.