JPH0792711B2 - Floating type parallel regulator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating parallel regulator, and more particularly to noise prevention at its output.

[0002]

2. Description of the Related Art FIG. 2 shows a circuit diagram of a conventional floating type regulator used in audio equipment and the like.
It is composed of transistors 2, 4 and a constant voltage diode 6.

Transistor used as a constant current source
2 and 4 are configured as shown in FIG. Transi
The stars 2 and 4 have better current feedback due to the resistance r.
It has good constant current characteristics. V is the base voltage, V_BE
Is the base-emitter voltage, I e is the emitter current, I_cTo
Collector current, I_bIs the base current,
To establish.

[0004] _{V = V BE + I e r} ∴I e = (V-V BE) / r I 0 = I c = I e -I b = (V-V BE) / r-I b DC current gain ( If h _FE ) is large enough so that I _b can be ignored compared to I _e , then I ₀ = (V−V _BE ) / r. When the voltage obtained by adding a resistance r between the collector and emitter and V _S, V _S -I ₀ characteristic can be expressed as FIG. If the voltage is equal to or higher than the predetermined voltage, the constant current characteristic is exhibited.

Next, the voltage drop of the transistor 2 is changed to V _S1 ,
The voltage drop of the transistor 4 is V _S2 and the input voltage is E ₁
When the output voltage is set to V _{0 and} the voltage distribution of the circuit at this time is calculated, V _S1 = V ₁ −V ₃ , V _S2 = V ₄ −V ₂ ∴V _S1 + V _S2 = V ₁ −V ₂ − (V ₃ −V ₄ ) = E ₁ −V ₀ That is, this circuit satisfies that the sum of the voltage drop of the transistor 2 and the voltage drop of the transistor 4 is the difference between the input voltage and the output voltage. It is operating at current I ₀ .

Normally, the constant current characteristics of the transistors 2 and 4 differ as shown in FIG. 5 due to variations and fluctuations in V, V _BE and r, respectively. In this figure, V _S1 of the transistor 2 is in the saturation region and V _S2 of the transistor 4 is in the constant current region, but the circuit as a whole exhibits constant current characteristics. Therefore, the parallel regulator is operating normally.

[0007]

However, the conventional circuit as described above has the following problems.

In the circuit of FIG. 2, as shown in FIG.
_S2 shows a sufficiently large constant current characteristic, but V _S1 is small in the saturation region. Therefore, when the impedance of the path on the V _S1 side as viewed from the output side becomes low and noise (common mode noise) exists in the input voltage, there is a problem that the path appears on the output side through the path on the V _S1 side.

That is, in the circuit of FIG. 2, even if the parallel regulator operates normally, there is a problem that noise appears on the output side because the impedance of one saturated transistor decreases.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and provide a floating parallel regulator which raises impedance and does not output noise.

[0011]

According to a first aspect of the present invention, there is provided a floating type parallel regulator having a first input terminal, a second input terminal, a first output terminal for extracting a stabilized output, and a stabilized output. A second output end for connecting the first input end and the first output end for setting a first constant current
A first constant current circuit having a resistor and a first transistor,
A second input connected between the second input and the second output ,
The second having the constant current setting resistor and the second transistor
Constant current circuit, two output sides for the first constant current setting
It is connected to both ends of the resistor and is connected to the two input sides.
Input voltage input to the first and second input terminals, respectively
The voltage obtained by adding half the bias voltage to the midpoint voltage,
Midpoint voltage of the output voltage output to the first and second output terminals
Voltage, which is half the bias voltage, is applied.
The first differential amplifier circuit, the two output sides, the second constant
Connected to both ends of the current setting resistor and
On the input side, and input to the first and second input terminals, respectively.
Half the bias voltage from the midpoint voltage of the input voltage
The subtracted voltage, the output that is output to the first and second output terminals
Half the bias voltage is subtracted from the midpoint voltage
A second differential amplifier circuit to which a voltage is applied,
Low potential side of the first differential amplifier circuit and the second differential amplifier circuit
Of the input voltage applied to the first and second input terminals and the output voltage output to the first and second output terminals while connecting the high potential side of Is detected, and current is fed back to the first or second transistor so that the difference is eliminated.

[0012]

A floating type parallel regulator according to a first aspect of the present invention comprises a first differential amplifier circuit and a second differential amplifier circuit.
And an input voltage applied to the first and second input terminals,
The difference between the midpoint potentials of the output voltages output to the first and second output terminals is detected, and the current is fed back to the first or second transistor so as to eliminate this difference.

[0013]

1 is a circuit diagram of a floating type parallel regulator according to an embodiment of the present invention. Input voltages V ₁ and V ₂ appear at the first input terminal 20 and the second input terminal 22. First output terminal 24, second
The output voltages V ₃ and V ₄ appear at the output terminal 26 of the.

A transistor 28, which is a first transistor, and a first resistor r are provided between the input end 20 and the output end 24.
A first constant current circuit is provided. Further, a second constant current circuit having a transistor 30, which is a second transistor, and a second resistor r is provided between the input end 22 and the output end 26.
ing. In addition, the feedback current transistors 32 and 34
Therefore, the first differential amplifier circuit is formed and the feedback current transformer is formed.
The second differential amplifier circuit is formed by the transistors 36 and 38.
Is made. As is clear from FIG. 1, the first differential amplification
The input side of the circuit (ie the bases of the transistors 32, 34)
Of the bias power source V _B and the resistor R _{2 respectively.}
Connection point (V ₅ ), the positive side of the bias power source V _B and the resistor R ₁
Is connected to the connection point (V ₇ ). That is, the first difference
One of the input sides of the dynamic amplification circuit (the base of the transistor 32
Is the bias voltage V at the midpoint potential of the output terminals 24 and 26.
It is connected to a voltage point V ₅ to which half _B is added . Also,
The other of the input side of the differential amplifier circuit 1 (of the transistor 34
The base) is a bias voltage at the midpoint potential of the input terminals 20 and 22.
It is connected to a voltage point V ₇ which is half the pressure V _B. As well
The input side of the second differential amplifier circuit (that is, the transistor
The bases of 36 and 38 are respectively the bias power source V _B.
The negative electrode side and the connection point resistance R ₂ of the (V _6), the bias power source V _B
Is connected to the connection point (V ₈ ) between the negative electrode side and the resistor R ₁ .
That is, one of the input side of the first differential amplifier circuit (transition
The base of the star 36) is the midpoint potential of the output terminals 24, 26.
Connected to the voltage point V ₆ which is half the bias voltage V _B
ing. In addition, the other of the input side of the first differential amplifier circuit
The base of the transistor 38 is a midpoint between the input ends 20 and 22.
Connected to voltage point V ₈ which is the potential minus half the bias voltage V _B
Has been continued. Furthermore, the low potential side of the first differential amplifier circuit
And the high potential side of the second differential amplifier circuit is
Connected. Note that each of the transistors 28-34
Assuming that the direct current amplification factor (h _FE ) is sufficiently large,
Let I _e = I _c + I _b ≈I _c .

When circuit calculation is performed based on the circuit of FIG. 1, I ₃ + I ₄ = I ₇ = I ₅ + I ₆ , I ₁ -I ₃ = I ₀ = I ₂ -I ₅ ,
(V ₁ + V ₂ ) / 2 = (V ₇ + V ₈ ) / 2, (V ₃ + V ₄ ) /
2 = (V ₅ + V ₆ ) / 2, V ₅ = V ₆ + V _B , V ₇ = V ₈ + V _{B The} above equations hold. If V _A = V _BE (transistor 28) + I ₁ r = V _BE (transistor 30) + I ₂ r holds and V _BE (transistor 28) = V _BE (transistor 30), then I ₁ r = I ₂ r ∴ I ₁ = I _2, that is, the current flowing through the resistor r is constant.

If this circuit system is perfectly balanced, the collector-emitter voltage V _CE of the transistors 28 and 30 will be equal. Therefore, the voltage drops during this period are equal and V ₁ −V ₃ = V ₄ −V ₂ .

Therefore, (V ₁ + V ₂ ) / 2 = (V ₃ + V ₄ ).
/ 2. At this time, from the above formula, (V ₇ + V ₈ ) /
2 = (V ₅ + V ₆ ) / 2, V ₅ = (V ₃ + V ₄ ) / 2 + V _B /
_{2, V 6 = (V 3} + V 4) / 2-V B / 2, V 7 = (V 1 + V
_{2) / 2 + V B /} 2, V 8 = (V 1 + V 2) / formula, such as 2-V _B / 2 is derived. Therefore, the base voltages of the transistors 32 and 34 are equal, and the base voltages of the transistors 36 and 38 are equal. At this time, I ₃ = I ₄ = I ₅ = I ₆ = I ₇
/ 2. The circuit of FIG. 1 operates in this way.

Now, because the characteristics of the transistors 28 and 30 are different due to variations in V _A , V _BE , r, etc., assuming that the transistor 28 enters the saturation region, the collector-emitter voltage of the transistor 28 becomes equal to that of the transistor 28. When it becomes smaller than the collector-emitter voltage of 30, V ₁ −V ₃ <V ₄ −V _2, and therefore (V ₁ + V ₂ ) /
2 <(V ₃ + V ₄ ) / 2, V ₅ > V ₇ , V ₆ > V ₈ and the base potential V ₅ of the transistor 32 is the transistor 3
It becomes higher than the base potential V _{7 of} 4. Similarly, the base potential V ₆ of the transistor 36 becomes higher than the base potential V ₈ of the transistor 38.

Since the difference between the base potentials and the emitters of the transistors 32 and 34 are connected in an npn structure, the collector current of the transistor 32 increases and the collector current of the transistor 34 decreases. On the other hand, since the transistors 36 and 38 have the pnp structure, the collector current of the transistor 36 decreases and the collector current of the transistor 38 increases. That is, I ₃ >
The state is I ₄ , I ₅ <I ₆ .

As a result, I ₁ is bypassed by the increased amount of I ₃ , so that the emitter current of the transistor 28 is lowered and the bias is moved from the saturated state to the constant current state. That is, it operates so as to increase the collector-emitter voltage of the transistor 28 by decreasing the emitter current. On the contrary, since the emitter current of the transistor 30 is bypassed by the decrease of I ₅ , the emitter current of the transistor 30 is increased and the collector-emitter voltage of the transistor 30 is decreased.

Thus, the circuit of FIG. 1 has (V ₁ + V ₂ )
It operates so as to keep / 2 = (V ₃ + V ₄ ) / 2. That is, the difference between the midpoint potential of the input voltages V ₁ and V _{2 and} the midpoint potential of the output voltages V ₃ and V ₄ is detected, and current is fed back to the transistor 28 or 30 so as to eliminate the difference, and the saturation region is reached. The bias of the transistor 28 or 30 in FIG.
Both of them set 0 to maintain constant current characteristics.

Therefore, the impedance seen from the output side becomes high in both the transistors 28 and 30,
Common mode noise existing in the input voltage is not output.

[0023]

According to the floating type parallel regulator of the first aspect , the first differential amplifier circuit and the second differential amplifier circuit are provided.
Therefore, the difference between the input voltage applied to the first and second input terminals and the midpoint potential of the output voltage output to the first and second output terminals is detected, and the first voltage is adjusted so that this difference disappears. Alternatively, the current is fed back to the second transistor. Therefore, it is possible to increase the impedance and prevent noise from being output.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a floating parallel regulator according to an embodiment of the present invention.

FIG. 2 shows a circuit diagram of a conventional floating type parallel regulator.

FIG. 3 is a diagram showing a configuration of a constant current source.

FIG. 4 is a diagram showing constant current characteristics of a transistor.

FIG. 5 is a diagram showing constant current characteristics of a transistor.

[Explanation of symbols]

 20 ... 1st input terminal 22 ... 2nd input terminal 24 ... 1st output terminal 26 ... 2nd output terminal 28 ... 1st transistor 30 ... 2nd 32-38 ... Transistors

Claims (1)

[Claims] 1. A first input end, (b) a second input end, (c) a first output end for extracting a stabilized output, and (d) a first output for extracting a stabilized output. second output terminal is connected between the (e) a first input terminal and a first output end, the
A first constant current setting resistor and a first transistor;
1 of the constant current circuit, is connected between the (f) a second input terminal and a second output end, the
A second constant current setting resistor and a second transistor
2 constant current circuit, (g) 2 output sides are both the above-mentioned 1st constant current setting resistance
While being connected to the end, on the two input sides,
Midpoint voltage of the input voltage input to the first and second input terminals
Voltage plus half the bias voltage, above
The midpoint voltage of the output voltage output to the 1st and 2nd output terminals
The first applied with a voltage that is half the Iias voltage
Differential amplifier circuit, (h) the two output sides are both the second constant current setting resistor
While being connected to the end, on the two input sides,
Midpoint voltage of the input voltage input to the first and second input terminals
Voltage minus half the bias voltage, above
From the midpoint voltage of the output voltage output to the 1st and 2nd output terminals
The first applied voltage equal to half the bias voltage
2 differential amplifier circuit, and (i) the low potential side of the first differential amplifier circuit and the second difference
If the high potential side of the dynamic amplifier circuit is connected via a resistor,
At the same time, the difference between the input voltage applied to the first and second input terminals and the midpoint potential of the output voltage output to the first and second output terminals is detected, and the difference is eliminated. A floating type parallel regulator characterized in that a current is fed back to the first or second transistor.