JPH0792772B2 - Watchdog timer device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a CPU (central processing unit).
The present invention relates to a watchdog timer device for monitoring an abnormal operation, and particularly to a watchdog timer device suitable for monitoring the operation of a CPU used in an environment with a lot of external noise such as a microcomputer for controlling an internal combustion engine.

[0002]

2. Description of the Related Art A watchdog timer device has been conventionally used to monitor an abnormal operation of a microcomputer or the like. An example of a conventional watchdog timer device is shown in FIG. A port 10 of the CPU outputs a watchdog timer signal whose polarity is inverted at a constant cycle. This signal is differentiated by the capacitor C1 and the differentiated output is amplified by the transistor Tr. At the same time that the integrating circuit composed of the resistor R1 and the capacitor C2 integrates the output of the transistor Tr, the integrating capacitor C2 is discharged through the resistors R1 and R2. Therefore, the operation of the CPU is normal,
While the pulse-shaped watchdog timer signal is being output from the port 10 at the constant cycle, the terminal voltage of the integrating capacitor C2 does not fall below the preset value. No abnormal output is generated. However, when the operation of the CPU becomes abnormal and the polarity reversal of the watchdog timer signal does not occur for a predetermined time or longer, the terminal voltage of the integration capacitor C2 becomes lower than the set predetermined value, and the voltage comparison circuit 2 produces an output. Display anomalies.

As another method, the polarity of the watchdog timer signal is monitored at regular intervals by a program timer interrupt (of a cycle shorter than the polarity inversion cycle of the watchdog timer signal), and continuously monitored for a predetermined number of times or more. It is also known to determine an abnormality when the results are the same.

[0004]

In the above-mentioned conventional watchdog timer device, the polarity of the watchdog timer signal is inverted a plurality of times or the timer interrupt is required for the abnormality determination, so that the timing of the abnormality determination tends to be delayed. There is a problem that is. Further, it is possible to detect an abnormality (for example, program runaway) such that the cycle becomes shorter than a predetermined value only by detecting an abnormality of the CPU in which the polarity inversion cycle of the watchdog timer signal becomes longer than the predetermined value. Is not intended at all. However, in reality, there is a possibility of occurrence of an abnormality such as the latter, and it is necessary to detect it.

Further, in the analog type watchdog timer device as shown in FIG. 2, since the differentiating circuit is easily affected by external noise, it is used especially in an environment where noise is likely to occur, such as in an automobile. In this case, there is a problem that the CPU abnormality may be overlooked or the abnormality detection may be delayed.

An object of the present invention is to provide a CPU in which the polarity inversion cycle of the watchdog timer signal becomes longer than a predetermined value.
Not only can detect the abnormalities of the above, but also the abnormality that the cycle becomes shorter than the planned value (for example, program runaway).
It is an object of the present invention to provide a watchdog timer device which can detect even the above, and can achieve the detection earlier.

[0007]

An oscillator circuit independent of the operation of the CPU and a counter for counting the output pulses of the oscillator circuit are provided, and the polarity of the watchdog timer signal supplied from the CPU port is inverted. A synchronous trigger generator for generating an inversion detection signal in response to the signal, means for setting an upper limit value and a lower limit value of an oscillation circuit output pulse to be counted during one cycle of polarity inversion of the watchdog timer signal, In response to the inversion detection signal, the count value of the counter is fetched and compared with the upper limit value and the lower limit value, respectively, and when the count value deviates from the upper and lower limit values, an abnormal signal is generated, while the count value An upper / lower limit comparison unit is provided for generating a normal signal when it is between the upper and lower limit values.

Further, a start signal generator for oscillating a single pulse having a predetermined time width as a pseudo normal signal in response to only the polarity reversal of the first watchdog timer signal after power-on or CPU reset operation, oscillation. An oscillation frequency controller for varying the oscillation frequency of the circuit can be provided.

[0009]

Operation: The polarity inversion of the watchdog timer signal is set by setting the upper limit value and the lower limit value of the oscillation circuit output pulse to be counted in one cycle of the polarity inversion of the watchdog timer signal supplied from the CPU port. In response to the above, the count value of the counter is fetched, the count value is compared with the upper limit value and the lower limit value, respectively, and when the count value deviates from the upper and lower limit values, an abnormal signal is generated. Generates a normal signal when between values. As a result, not only an abnormality of the CPU in which the polarity inversion cycle of the watchdog timer signal becomes longer than the planned value can be detected, but also an abnormality in which the cycle becomes shorter than the planned value (for example, program runaway) is detected. Will also be able to detect. Further, since the differentiating circuit is not used, malfunction due to noise is eliminated.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The block diagram of FIG. 1 and the time chart of FIG.
An embodiment of the present invention will be described with reference to FIG.

When the power is turned on, the oscillation circuit 12
The oscillation pulse A having a constant frequency is generated regardless of the operation of U (not shown). The frequency of the oscillation pulse A can be changed by the oscillation frequency control unit 14 according to a desired monitoring time setting and monitoring accuracy. On the other hand, as in the case of FIG. 2, the CPU port 10 supplies the watchdog timer signal which rises as shown by B in FIG. 3 at the time of power-on or reset. The synchronization trigger generator 16 is supplied with the oscillation pulse A and the watchdog timer signal B, and the inversion detection signal synchronized with the oscillation pulse A immediately after the polarity of the signal B is inverted, that is, the trigger pulse C (a to g in FIG. 3). ) Occurs.

The counter 18 counts the oscillation pulse A.
An example of the count value is shown above the waveform A in FIG. The upper and lower limit comparison unit 20 is triggered by the trigger pulse C, takes in the count value of the counter 18 at that time, and compares the count value with the upper and lower limit values set in advance by the upper and lower limit value setting unit 22. The upper and lower limit values are the upper limit value and the lower limit value of the oscillation pulse to be counted during one cycle of the polarity reversal of the watchdog timer signal. On the other hand, the trigger pulse C is delayed by the delay means 24 (1 of the oscillation pulse A).
The time is less than the period) and is also supplied to the counter 18 to reset it.

In this example, the upper limit is 100 and the lower limit is 7.
It is assumed that it is set to 0. The counter 18
Between the upper and lower limit values of the count value of (in this example,
If it is between 70 and 100), a normal signal of 1 level is output as a determination signal, and if it is out of the range, an abnormal signal of 0 level is output as a determination signal. This determination signal is shown by the waveform D in FIG. That is, in response to each of the inversion detection signals a to g shown in C of FIG. 3, the normal / abnormal signals as shown by D in FIG.

The system operation determination section 26 responds to the normal / abnormal signal from the upper / lower limit comparison section 20 and indicates that the system can operate normally (system operation) permission signal ("1") or reset. The signal (“0”) is output. When the reset signal is output, the CPU is reset and restarted. In the example of FIG. 3, an abnormal signal is output according to the trigger pulses a, d, and g, while a normal signal is output according to the trigger pulses b, c, e, and f. When the abnormal signals d and g are generated, the CPU is reset and restarted in response.

As is clear from the attention to the left end of FIG. 3, the count value from the power-on or reset operation to the first inversion point of the watchdog timer signal B is not stable,
Not only is it different, but the output range D of the comparison unit 20 often becomes an abnormal signal because it does not fall within the numerical range set by the upper and lower limit value setting unit 22, so this is a system startup at power-on or reset operation. It may be a hindrance to raising.

As a countermeasure against this, the present invention responds only to the polarity reversal of the first watchdog timer signal after the power is turned on or the reset operation is performed, and the unit of a predetermined time width (slightly longer than the polarity reversal period) is used. A start signal generator 28 for generating one pulse as a start signal is provided. The start signal is a pseudo-normal signal, is supplied to the system operation determination unit 26, and the output signal D from the upper and lower limit comparison unit 20.
Regardless of, the level 1 permission signal is generated. This guarantees the start and restart of system operation.

The start signal generator 28 as described above is
For example, a one-shot multivibrator triggered by the polarity reversal of the watchdog timer signal and a lamp potential generating means that rises from the time of power-on or reset operation are provided, and when the lamp potential rises to a predetermined value, the one-shot multivibrator is provided. This can be achieved by disabling the shot multivibrator. Alternatively, one-shot multi-vibration triggered by power-on or reset action
The same function can be realized by using only the data.

In the embodiment of FIG. 1, the synchronization trigger generator 16
Is provided to synchronize the acquisition of the count value from the counter 18 and the comparison of the count value and the upper and lower limit values by the upper and lower limit value setting unit 22 with the oscillation pulse A immediately after the polarity of the watchdog timer signal B is inverted. However, if the time regulation of the polarity inversion cycle (that is, the criterion for the abnormality determination) is gentle, the synchronization trigger generator 16 simply detects the polarity inversion of the watchdog timer signal B. And output the signal C. That is, the count value may be fetched from the counter 18 at the rising and falling timings of the signal B, and the upper and lower limit value setting unit 22 may compare the count value with the upper and lower limit values.

[0019]

According to the present invention, it is assumed that the polarity inversion cycle of the watchdog timer signal becomes longer than a predetermined value.
Not only can the abnormality of the PU be detected, but also the abnormality in which the cycle becomes shorter than the predetermined value (for example, program runaway) can be detected, so that more complete abnormality monitoring becomes possible. Further, every time the polarity of the watchdog timer signal is inverted, in other words, an early abnormality determination can be made every half cycle of the pulse, so that the propagation of a fault due to a CPU abnormality can be minimized. Furthermore, the present invention
According to the system, the system is
Pseudo normal signal is output under the condition that the operation of the system becomes unstable
Therefore, the polarity reversal cycle is shorter than the planned lower limit value.
Even if it is added to the judgment criteria whether or not
It prevents the power on and off, and during transitional periods such as immediately after the power is turned on.
Even then, complete abnormality monitoring can be realized.

Further, as in the embodiment shown in FIG. 1, the count value is fetched by the upper and lower limit comparison unit 20, the comparison and reset of the counter 18 and the start are synchronized with the oscillation pulse immediately after the polarity reversal of the watchdog timer signal. By doing so, the influence of disturbance noise is reduced and the oscillation pulses are counted more accurately, so that the polarity inversion cycle of the watchdog timer signal can be monitored. Further, by controlling the oscillation frequency of the oscillation circuit, it is easy to adjust the definition of the polarity inversion period monitor.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional watchdog timer device.

FIG. 3 is a time chart for explaining the operation of the embodiment of FIG.

[Explanation of symbols]

 10 CPU Port 12 Oscillation Circuit 14 Oscillation Frequency Control Section 16 Synchronous Trigger Generation Section 18 Counter 20 Upper / Lower Limit Comparison Section 26 System Operation Judgment Section 28 Start Signal Generation Section

Claims (5)

[Claims] 1. An oscillation circuit independent of the operation of a CPU, a counter for counting oscillation pulses output from the oscillation circuit, and inversion detection in response to polarity inversion of a watchdog timer signal supplied from a CPU port. A synchronous trigger generator for generating a signal; means for setting an upper limit value and a lower limit value of an oscillation pulse to be counted during one cycle of polarity reversal of the watchdog timer signal; When the count value of the counter is fetched and compared with the upper limit value and the lower limit value respectively, and an abnormal signal is generated when the count value deviates from the upper and lower limit values, while the count value is between the upper and lower limit values Is the upper and lower limit comparator that generates a normal signal, and the first watchdog after power-on or CPU reset operation.
In response to only the polarity reversal of the
Start signal that generates a single pulse as a pseudo normal signal
Watchdog timer device being characterized in that; and a generation unit. 2. The watchdog timer device according to claim 1, wherein the synchronous trigger generation unit generates the inversion detection signal at a timing that substantially coincides with the polarity inversion of the watchdog timer signal. 3. The watchdog timer according to claim 1, wherein the synchronous trigger generator generates the inversion detection signal at a timing that coincides with the oscillation pulse output immediately after the polarity inversion of the watchdog timer signal. apparatus. 4. The pseudo normal signal is a signal of the polarity inversion cycle.
A contract characterized by having a duration slightly longer than the period
The watchdog timer device according to claim 1. 5. A method for varying an oscillation frequency of an oscillation circuit
A contract characterized by further comprising an oscillation frequency control unit
The watchdog timer device according to any one of claims 1 to 4 .