JPH0793259B2 - Method for manufacturing semiconductor thin film crystal layer - Google Patents
Method for manufacturing semiconductor thin film crystal layerInfo
- Publication number
- JPH0793259B2 JPH0793259B2 JP506987A JP506987A JPH0793259B2 JP H0793259 B2 JPH0793259 B2 JP H0793259B2 JP 506987 A JP506987 A JP 506987A JP 506987 A JP506987 A JP 506987A JP H0793259 B2 JPH0793259 B2 JP H0793259B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film
- semiconductor thin
- single crystal
- crystal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 61
- 239000010409 thin film Substances 0.000 title claims description 53
- 239000013078 crystal Substances 0.000 title claims description 45
- 238000000034 method Methods 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000010408 film Substances 0.000 claims description 87
- 239000000758 substrate Substances 0.000 claims description 29
- 238000002844 melting Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 238000001953 recrystallisation Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 50
- 229910004298 SiO 2 Inorganic materials 0.000 description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 17
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 13
- 238000010894 electron beam technology Methods 0.000 description 7
- 238000000137 annealing Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910021486 amorphous silicon dioxide Inorganic materials 0.000 description 1
- 238000002048 anodisation reaction Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000005350 fused silica glass Substances 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、絶縁膜上に半導体薄膜結晶層を成長させる方
法に係わり、特に絶縁膜に設けた開口部をシードとして
用いる半導体薄膜結晶層の製造方法に関する。The present invention relates to a method of growing a semiconductor thin film crystal layer on an insulating film, and particularly uses an opening provided in the insulating film as a seed. The present invention relates to a method for manufacturing a semiconductor thin film crystal layer.
（従来の技術） 絶縁基板上の単結晶薄膜は、SOS（サファイア上のシリ
コン）の例でも判るように、次に述べるようなを利点を
有する。即ち、 単結晶薄膜を島状に分離し或いは誘電体により分離
することによって、素子間の分離が容易且つ完全とな
る。(Prior Art) A single crystal thin film on an insulating substrate has the following advantages, as can be seen in the example of SOS (silicon on sapphire). That is, by separating the single crystal thin film into islands or by separating with a dielectric, the separation between the elements becomes easy and complete.
単結晶薄膜上にMOSインバータ回路を作るときは、
基板バイアス効果がないことからスイッチング速度が速
い。When making a MOS inverter circuit on a single crystal thin film,
The switching speed is high because there is no substrate bias effect.
寄生浮遊容量が小さく、高速化をはかり得る。 The parasitic stray capacitance is small, and the speed can be increased.
等の利点を有する。And so on.
ところで、SOSでは下地基板として単結晶サファイアが
必要となるため、価格が高くなることが問題点として残
っている。そこで、溶融水晶板やSiウェハを酸化して形
成した非晶質SiO2膜或いはSiウェハ上に堆積したSiN,Si
O2膜上に半導体膜を更に堆積したものを使用する試みが
ある。このようなSOI（絶縁膜上のシリコン）構造は、
最近発達したビームアニール法によって部分的に可能に
なっている。即ち、Siを例にとると、単結晶Si基板を酸
化し、SiO2膜を形成した後、この一部分を除去すること
によって開口し、次に多結晶Si膜を全面に被着し、Si基
板表面からSiO2膜上まで多結晶Si膜を連続して延在させ
る。その後、エネルギービームを照射すると、Si基板表
面で溶融した多結晶Si膜は基板から液相エピタキシャル
成長によって単結晶化し、さらにビームの走査方向に沿
ってSiO2膜上の多結晶Si膜もそれに引続き単結晶化され
ると云うものである。By the way, SOS requires a single-crystal sapphire as a base substrate, so that the cost remains to be a problem. Therefore, an amorphous SiO 2 film formed by oxidizing a fused quartz plate or a Si wafer or SiN, Si deposited on a Si wafer
There have been attempts to use a semiconductor film further deposited on the O 2 film. Such an SOI (silicon on insulating film) structure is
Partly enabled by the recently developed beam annealing method. That is, taking Si as an example, a single-crystal Si substrate is oxidized to form a SiO 2 film, and then an opening is formed by removing a part of this, and then a polycrystalline Si film is deposited on the entire surface to form a Si substrate. A polycrystalline Si film is continuously extended from the surface to the SiO 2 film. After that, when the energy beam is irradiated, the polycrystalline Si film melted on the surface of the Si substrate becomes a single crystal by liquid phase epitaxial growth from the substrate, and the polycrystalline Si film on the SiO 2 film continues to be monocrystalline along the beam scanning direction. It is said to be crystallized.
しかしながら、この種の方法にあっては次のような問題
があった。即ち、開口部上に被着したSiを溶融せしめる
のに必要なエネルギーは、SiO2膜上でのそれと比較して
高くなる。これは、Siの熱伝導率がSiO2のそれよりも大
きいため、Si基板上のSi膜では熱が基板下方に伝導して
いく割合が大きくなり、基板表面近くの温度がSiO2膜上
のSi膜よりも同一供給エネルギー条件の下では低くなる
ためである。これを解決するためにエネルギーを大きく
すると、SiO2膜上のSi膜表面の平滑性が失われる現象が
見られ、従来の方法では絶縁膜上に表面平坦性の優れた
Si単結晶層を得ることは困難であった。そして、３次元
ICを実現するには、この欠点が解決すべき大きな問題と
なっている。However, this type of method has the following problems. That is, the energy required to melt the Si deposited on the opening is higher than that on the SiO 2 film. This is because the thermal conductivity of Si is higher than that of SiO 2 , so that in the Si film on the Si substrate, the rate of heat conduction to the lower side of the substrate is large, and the temperature near the substrate surface is above the SiO 2 film. This is because it is lower than that of the Si film under the same supply energy condition. When the energy is increased to solve this, the phenomenon that the smoothness of the Si film surface on the SiO 2 film is lost is seen. With the conventional method, the surface flatness on the insulating film was excellent.
It was difficult to obtain a Si single crystal layer. And three-dimensional
In order to realize the IC, this drawback is a big problem to be solved.
（発明が解決しようとする問題点） このように従来方法では、絶縁膜上とシード部上とにお
ける熱拡散の度合いが異なるため、ビームアニール時に
おけるシード部上と絶縁膜上との半導体薄膜の温度に大
きな差が生じ、これが良質の半導体単結晶層の成長を妨
げる要因となっていた。また、上記理由から、３次元IC
の製造等に用いる表面平滑性の優れた半導体単結晶層を
得ることは困難であった。(Problems to be Solved by the Invention) As described above, in the conventional method, since the degree of thermal diffusion on the insulating film is different from that on the seed portion, the semiconductor thin film on the seed portion and on the insulating film during the beam annealing is reduced. A large difference occurs in temperature, which is a factor that hinders the growth of a good-quality semiconductor single crystal layer. Also, for the above reasons, 3D IC
It was difficult to obtain a semiconductor single crystal layer having excellent surface smoothness, which is used for manufacturing the above.
本発明上記事情を考慮してなされたもので、その目的と
するところは、再結晶化する半導体薄膜のシード部上と
絶縁膜上との熱的条件を同等のものとすることができ、
絶縁膜上に表面平滑性の優れた良質の半導体単結晶層を
成長させることのできる半導体薄膜結晶層の製造方法を
提供することにある。The present invention has been made in consideration of the above circumstances, and an object thereof is to make the thermal conditions on the seed portion and the insulating film of the semiconductor thin film to be recrystallized equal to each other,
It is an object of the present invention to provide a method for producing a semiconductor thin film crystal layer capable of growing a good quality semiconductor single crystal layer having excellent surface smoothness on an insulating film.
［発明の目的］ （問題点を解決するための手段） 本発明の骨子は、再結晶化する半導体薄膜のシード部と
なる下地半導体領域を絶縁膜で下地基板と分離し、シー
ド部から下地基板への熱伝導を小さくし、シード部上の
半導体薄膜と絶縁膜上の半導体薄膜との熱的条件を近付
けることにある。[Object of the Invention] (Means for Solving the Problems) The gist of the present invention is to separate an underlying semiconductor region, which is a seed portion of a semiconductor thin film to be recrystallized, from an underlying substrate with an insulating film, and then from the seed portion to the underlying substrate. In order to reduce the heat conduction to the semiconductor part, the semiconductor thin film on the seed part and the semiconductor thin film on the insulating film should be close in thermal condition.
即ち本発明は、半導体単結晶基板上に一部開口部を有す
る第１層の絶縁膜を形成したのち、全面に非晶質若しく
は多結晶の半導体薄膜を堆積し、次いでこの半導体薄膜
上でエネルギービームを走査して該薄膜を溶融・再結晶
化せしめて第１層の半導体薄膜単結晶層を形成し、更に
上記第１層の半導体薄膜単結晶層のシード部上に開口部
を有する第２層の絶縁膜を形成したのち、全面に非晶質
若しくは多結晶の半導体薄膜を堆積し、次いでこの半導
体薄膜上でエネルギービームを走査して該薄膜を溶融・
再結晶化せしめて第２層の半導体薄膜単結晶層を形成す
るようにして半導体単結晶基板上に多層の半導体薄膜単
結晶層を形成するようにした半導体薄膜薄膜単結晶層の
製造方法において、下地の半導体薄膜単結晶層上に半導
体素子を形成したのち、該半導体薄膜単結晶層をシード
部を残して酸化処理して絶縁膜とし、該絶縁膜によって
上記シード部が上記基板とは分離するようにした方法で
ある。That is, according to the present invention, after forming an insulating film of a first layer having a partial opening on a semiconductor single crystal substrate, an amorphous or polycrystalline semiconductor thin film is deposited on the entire surface, and then an energy is deposited on the semiconductor thin film. A beam is scanned to melt and recrystallize the thin film to form a first semiconductor thin film single crystal layer, and a second opening having an opening on the seed portion of the first semiconductor thin film single crystal layer. After forming a layer insulating film, an amorphous or polycrystalline semiconductor thin film is deposited on the entire surface, and then the semiconductor thin film is scanned with an energy beam to melt the thin film.
A method of manufacturing a semiconductor thin film thin film single crystal layer, comprising recrystallizing to form a second semiconductor thin film single crystal layer to form a multilayer semiconductor thin film single crystal layer on a semiconductor single crystal substrate, After forming a semiconductor element on the underlying semiconductor thin film single crystal layer, the semiconductor thin film single crystal layer is oxidized to form an insulating film leaving a seed portion, and the insulating film separates the seed portion from the substrate. This is the method.
（作用） 上記方法であれば、シード部となる下地半導体領域が基
板とは絶縁膜で分離されるので、シード部領域から基板
への熱伝導が小さくなり、エネルギービーム照射時のシ
ード部上と絶縁膜上との半導体薄膜の温度差が小さくな
る。従って、半導体薄膜に照射するエネルギービームの
量を最適化することができ、絶縁膜上に良質の半導体単
結晶層を形成することが可能となる。(Operation) In the above method, since the base semiconductor region serving as the seed part is separated from the substrate by the insulating film, heat conduction from the seed part region to the substrate becomes small, and the seed part on the seed part at the time of energy beam irradiation is reduced. The temperature difference between the semiconductor thin film and the insulating film is small. Therefore, the amount of the energy beam with which the semiconductor thin film is irradiated can be optimized, and a good quality semiconductor single crystal layer can be formed on the insulating film.
（実施例） 以下、本発明の詳細を図示の実施例によって説明する。(Examples) The details of the present invention will be described below with reference to illustrated examples.
第１図（ａ）〜（ｇ）は本発明の第１の実施例方法に係
わる半導体薄膜結晶層の製造工程を示す断面図である。
まず、第１図（ａ）に示す如く単結晶Si基板11にゲート
電極12及びソース・ドレイン13,14からなるMOSトランジ
スタを形成し、この上に第１の層間絶縁膜としてのシリ
コン酸化膜（SiO2膜）15を平坦に形成する。続いて、Si
O2膜15の一部に後述するビームアニールの際のシード部
となる開口部16を形成する。その後、第１図（ｂ）に示
す如く、全面に第１の多結晶Si膜17を堆積し、さらにこ
の上にキャップ層としてのSiO2膜18を堆積する。1 (a) to 1 (g) are cross-sectional views showing a manufacturing process of a semiconductor thin film crystal layer according to the method of the first embodiment of the present invention.
First, as shown in FIG. 1 (a), a MOS transistor composed of a gate electrode 12 and source / drain 13 and 14 is formed on a single crystal Si substrate 11, and a silicon oxide film (first interlayer insulating film) is formed on the MOS transistor. SiO 2 film) 15 is formed flat. Then Si
An opening 16 is formed in a part of the O 2 film 15 to serve as a seed portion during beam annealing described later. Thereafter, as shown in FIG. 1 (b), a first polycrystalline Si film 17 is deposited on the entire surface, and a SiO 2 film 18 as a cap layer is further deposited thereon.
次いで、第１図（ｃ）に示す如く、キャップ層18を介し
て多結晶Si膜17に電子ビーム19を照射し走査することに
より、多結晶Si膜17を溶融・再結晶化せしめ、単結晶Si
層17′を形成する。ここで、上記電子ビーム19のビーム
径は100［μｍφ］、走査速度は10［cm/sec］とした。
さらに、ビーム走査の際に、該ビームを走査方向と直交
する方向に高速偏向（周波数50MHz,振幅4mm）すること
により、電子ビーム19を疑似線状ビームとした。Next, as shown in FIG. 1 (c), the polycrystalline Si film 17 is irradiated with an electron beam 19 through the cap layer 18 and scanned to melt and recrystallize the polycrystalline Si film 17 to form a single crystal. Si
Form layer 17 '. Here, the beam diameter of the electron beam 19 is 100 [μmφ], and the scanning speed is 10 [cm / sec].
Further, at the time of beam scanning, the electron beam 19 was made into a pseudo-linear beam by deflecting the beam at a high speed (frequency 50 MHz, amplitude 4 mm) in a direction orthogonal to the scanning direction.
次いで、第１図（ｄ）に示す如くキャップ層18を除去し
た後、単結晶Si層17′にゲート電極22及びソース・ドレ
イン13,14からなるMOSトランジスタを形成する。さら
に、次に形成すべきSi層のシード部となるべき部分21を
残し、単結晶Si層17′を酸化してSiO2膜22を形成する。
この状態で、単結晶Siからなるシード部21は、SiO2膜1
5,22により覆われたものとなり、基板11とは分離される
ことになる。Then, after removing the cap layer 18 as shown in FIG. 1D, a MOS transistor composed of the gate electrode 22 and the source / drain 13 and 14 is formed on the single crystal Si layer 17 '. Further, the single crystal Si layer 17 'is oxidized to form the SiO 2 film 22 while leaving the portion 21 to be the seed portion of the Si layer to be formed next.
In this state, the seed portion 21 made of single crystal Si has the SiO 2 film 1
It will be covered by 5,22 and will be separated from the substrate 11.
次いで、第１図（ｅ）に示す如く、全面に第２の層間絶
縁膜としてのSiO2膜25を堆積し、このSiO2膜25のシード
部21上に開口部26を形成する。その後、第１図（ｆ）に
示す如く全面に第２の多結晶Si膜（半導体薄膜）27を堆
積し、さらにこの上にキャップ層としてのSiO2膜28を堆
積する。Next, as shown in FIG. 1E, a SiO 2 film 25 as a second interlayer insulating film is deposited on the entire surface, and an opening 26 is formed on the seed portion 21 of the SiO 2 film 25. After that, as shown in FIG. 1 (f), a second polycrystalline Si film (semiconductor thin film) 27 is deposited on the entire surface, and a SiO 2 film 28 as a cap layer is further deposited thereon.
次いで、先と同様に第１図（ｇ）に示す如く、電子ビー
ム29を照射走査し、多結晶Si膜27を溶融・再結晶化する
ことによって、SiO2膜25上に単結晶Si層27′が形成され
ることになる。Then, as shown in FIG. 1 (g), the polycrystalline Si film 27 is melted and recrystallized by irradiating and scanning with the electron beam 29, as shown in FIG. 1 (g), so that the single crystal Si layer 27 is formed on the SiO 2 film 25. ′ Will be formed.
このように本実施例方法によれば、絶縁膜としてのSiO2
膜25上に単結晶Si層27′を形成することができる。そし
てこの場合、多結晶Si膜27をビームアニールする際に
は、シード部21となる下地Si領域がSiO2膜15,25により
基板11と分離されているので、シード部21上とSiO2膜25
上とにおける熱的条件は略等しいものとなる。このた
め、ビームアニールの際に多結晶Si膜27をシード部21上
及びSiO2膜25上とで略同じ温度に加熱することができ、
良質の単結晶Si層27′を形成することができる。また、
シード部21上及びSiO2膜25上における多結晶Si膜27のビ
ームアニール時の温度を略等しくできるので、ビームエ
ネルギーを低く抑えることが可能となり、これにより表
面平滑性の向上をはかることができる。従って、３次元
ICの製造等に適用して絶大なる効果が得られる。Thus, according to the method of this example, SiO 2 as the insulating film
A single crystal Si layer 27 'can be formed on the film 25. In this case, when the polycrystalline Si film 27 is beam-annealed, the underlying Si region serving as the seed portion 21 is separated from the substrate 11 by the SiO 2 films 15 and 25, so that the seed portion 21 and the SiO 2 film are separated. twenty five
The thermal conditions in and above are almost equal. Therefore, the polycrystalline Si film 27 can be heated to substantially the same temperature on the seed portion 21 and the SiO 2 film 25 during the beam annealing.
A good quality single crystal Si layer 27 'can be formed. Also,
Since the temperatures at the time of beam annealing of the polycrystalline Si film 27 on the seed portion 21 and the SiO 2 film 25 can be made substantially equal, it is possible to suppress the beam energy to a low level, thereby improving the surface smoothness. . Therefore, three-dimensional
When applied to the manufacture of IC, etc., the great effect can be obtained.
次いで、第２図（ｃ）に示す如く、先の実施例と同様に
全面に多結晶Si膜27及びキャップ層28を形成し、電子ビ
ーム29の照射により多結晶Si膜27を溶融・再結晶化す
る。Then, as shown in FIG. 2C, a polycrystalline Si film 27 and a cap layer 28 are formed on the entire surface as in the previous embodiment, and the polycrystalline Si film 27 is melted and recrystallized by irradiation with an electron beam 29. Turn into.
このような実施例方法であっても、先の実施例と同様の
効果が得られる。また、開口部26を予め単結晶Si膜31で
埋込んでおくことにより、多結晶Si膜27をより平坦に形
成することができる等の利点がある。Even with such an embodiment method, the same effect as that of the previous embodiment can be obtained. In addition, by filling the opening 26 with the single crystal Si film 31 in advance, there is an advantage that the polycrystalline Si film 27 can be formed flatter.
第３図（ａ）〜（ｄ）は本発明の第３の実施例方法を説
明するための工程断面図である。この実施例方法は、単
結晶Si基板のシード部を絶縁分離するようにしたもので
ある。3 (a) to 3 (d) are process sectional views for explaining a third embodiment method of the present invention. In this embodiment, the seed portion of the single crystal Si substrate is insulated and separated.
まず、第３図（ａ）に示す如く、単結晶Si基板41上にシ
リコン窒化膜（Si3N4）膜42を形成し、このSi3N4膜42を
レジスト43をマスクとしてパターニングする。この状態
でB+イオン注入を行い、マスクされていない領域にp+層
44を形成する。First, as shown in FIG. 3A, a silicon nitride film (Si 3 N 4 ) film 42 is formed on a single crystal Si substrate 41, and this Si 3 N 4 film 42 is patterned using a resist 43 as a mask. In this state, B + ion implantation is performed and p + layer is applied to the unmasked area.
Forming 44.
次いで、第３図（ｂ）に示す如く、Si3N442を通してプ
ロンプトイオン注入を行い、450［℃］でN2中の熱処理
を行い注入層をドナー化し、n+層45を形成する。このと
き、p+層44はｎ型化されないような条件を設定する。Then, as shown in FIG. 3B, prompt ion implantation is performed through Si 3 N 4 42, and heat treatment in N 2 is performed at 450 [° C.] to make the implanted layer a donor and form an n + layer 45. At this time, conditions are set such that the p + layer 44 is not made n-type.
次いで、弗化水素中で陽極化成を行う。これにより、ｐ
型層（基板11の表面及びp+層44）は多孔質化するが、ｎ
型層（n+層45）はそのままである。さらに、950［℃］
の水蒸気酸化を行い、第３図（ｃ）に示す如く、多孔質
化したｐ型層を酸化し、SiO2膜46を形成する。このと
き、プロトン注入で発生したドナーは消滅し、絶縁層
（SiO2膜46）で完全に分離された単結晶領域（シード
部）47が残ることになる。Then, anodization is performed in hydrogen fluoride. This gives p
The mold layer (the surface of the substrate 11 and the p + layer 44) becomes porous, but n
The mold layer (n + layer 45) remains. Furthermore, 950 [℃]
Is performed to oxidize the porous p-type layer to form a SiO 2 film 46, as shown in FIG. 3 (c). At this time, the donor generated by the proton injection disappears, and the single crystal region (seed part) 47 completely separated by the insulating layer (SiO 2 film 46) remains.
次いで、第３図（ｄ）に示す如く、全面に層間絶縁膜と
してのSiO2膜48を堆積し、このSiO2膜48の前記シード部
47上に開口部49を形成する。その後、全面に多結晶Si膜
50及び図示しないキャップ層を堆積し、これをビームア
ニールすることにより、先の実施例方法と同様に単結晶
Si層が形成されることになる。Then, as shown in FIG. 3 (d), depositing a SiO 2 film 48 as an interlayer insulating film on the entire surface, the seed portion of the SiO 2 film 48
An opening 49 is formed on 47. After that, a polycrystalline Si film is formed on the entire surface
50 and a cap layer (not shown) are deposited and beam-annealed to obtain a single crystal as in the method of the previous embodiment.
A Si layer will be formed.
なお、本発明は上述した各実施例方法に限定されるもの
ではない。例えば、前記絶縁膜に設ける開口部は直線状
に開口してもよいし、点状に開口してもよい。さらに、
開口部の大きさ等は仕様に応じて適宜定めればよい。ま
た、エネルギービームとしては、電子ビームの代りにレ
ーザビームを用いることも可能である。また、第１及び
第３の実施例を組合わせることにより、第１層及び第２
層の単結晶層形成の双方に本発明を適用することも可能
である。その他、本発明の要旨を逸脱しない範囲で、種
々変形して実施することができる。The present invention is not limited to the method of each of the embodiments described above. For example, the openings provided in the insulating film may be linear or dot-shaped. further,
The size and the like of the opening may be appropriately determined according to the specifications. A laser beam may be used as the energy beam instead of the electron beam. Also, by combining the first and third embodiments, the first layer and the second layer
It is also possible to apply the present invention to both formation of single crystal layers. In addition, various modifications can be made without departing from the scope of the present invention.
［発明の効果］ 以上詳述したように本発明によれば、ビームアニールす
べき半導体薄膜に接触する下地半導体領域の基板への熱
伝導が抑えられるので、シード部及び絶縁膜上の半導体
薄膜の加熱温度を略等しくすることができる。従って、
シード部における半導体薄膜の溶融・再結晶化を容易に
することができ、絶縁膜上に良質の半導体単結晶層を形
成することが可能となる。[Effects of the Invention] As described in detail above, according to the present invention, the heat conduction to the substrate in the base semiconductor region in contact with the semiconductor thin film to be beam annealed is suppressed, so that the semiconductor thin film on the seed portion and the insulating film is suppressed. The heating temperatures can be made substantially equal. Therefore,
Melting and recrystallization of the semiconductor thin film in the seed portion can be facilitated, and a good-quality semiconductor single crystal layer can be formed on the insulating film.
第１図（ａ）〜（ｇ）は本発明の第１の実施例方法に係
わる半導体薄膜結晶層の製造工程を示す断面図、第２図
（ａ）〜（ｃ）は本発明の第２の実施例方法を説明する
ための工程断面図、第３図（ａ）〜（ｄ）は本発明の第
３の実施例方法を説明するための工程断面図である。 11,41……単結晶Si基板、15,25,48……SiO2膜（層間絶
縁膜）、16,26,49……開口部、17,27,50……多結晶Si薄
膜（半導体薄膜）、17′,27′……単結晶シリコン層、1
8,28……キャップ層、19,29……電子ビーム（エネルギ
ービーム）、21,47……シード部、22,46……SiO2膜（シ
ード部分離用絶縁膜）、42……Si3N4膜、43……レジス
ト、44……p+層、45……n+層。1 (a) to 1 (g) are cross-sectional views showing a manufacturing process of a semiconductor thin film crystal layer according to the first embodiment method of the present invention, and FIGS. 2 (a) to 2 (c) are second embodiment of the present invention. FIGS. 3 (a) to 3 (d) are process cross-sectional views for explaining the method of Example 3 of the present invention, and FIGS. 11,41 …… Single-crystal Si substrate, 15,25,48 …… SiO 2 film (interlayer insulating film), 16,26,49 …… Opening part, 17,27,50 …… Polycrystalline Si thin film (semiconductor thin film) ), 17 ', 27' ... single crystal silicon layer, 1
8,28 ...... Cap layer, 19,29 ...... Electron beam (energy beam), 21,47 …… Seed part, 22,46 …… SiO 2 film (seed part isolation insulating film), 42 …… Si 3 N 4 film, 43 …… resist, 44 …… p + layer, 45 …… n + layer.
Claims (3)
第１層目の絶縁膜を形成したのち、全面に非晶質若しく
は多結晶の半導体薄膜を堆積し、次いでこの半導体薄膜
上でエネルギービームを走査して該薄膜を溶融・再結晶
化せしめて第１層の半導体薄膜単結晶層を形成し、更に
上記第１層の半導体薄膜単結晶層のシード部上に開口部
を有する第２層の絶縁膜を形成したのち、全面に非晶質
若しくは多結晶の半導体薄膜を堆積し、次いでこの半導
体薄膜上でエネルギービームを走査して該薄膜を溶融・
再結晶化せしめて第２層の半導体薄膜単結晶層を形成
し、上記開口部を有する絶縁膜を形成したのち、全面に
非晶質若しくは多結晶の半導体薄膜を堆積し、次いでエ
ネルギービームを走査して該薄膜を溶融・再結晶化せし
める工程を繰り返して半導体結晶基板上に多層の半導体
薄膜単結晶層を形成するようにした半導体薄膜結晶層の
製造方法において、上記第１層の半導体薄膜単結晶層上
に半導体素子を形成したのち、該半導体薄膜単結晶層を
シード部を残して酸化処理して絶縁膜とし、該絶縁膜に
よって上記シード部が前記基板とは分離されていること
を特徴とする半導体薄膜単結晶層の製造方法。1. A first-layer insulating film having a partial opening is formed on a semiconductor tube crystal substrate, and then an amorphous or polycrystalline semiconductor thin film is deposited on the entire surface. The semiconductor thin film single crystal layer of the first layer is formed by scanning and scanning the energy beam to melt and recrystallize the thin film, and the first semiconductor thin film single crystal layer has an opening on the seed portion. After forming two layers of insulating film, an amorphous or polycrystalline semiconductor thin film is deposited on the entire surface, and then the semiconductor thin film is scanned with an energy beam to melt the thin film.
After recrystallization, a second-layer semiconductor thin film single crystal layer is formed, an insulating film having the above-mentioned opening is formed, and then an amorphous or polycrystalline semiconductor thin film is deposited on the entire surface, followed by scanning with an energy beam. In the method for producing a semiconductor thin film crystal layer, the step of melting and recrystallizing the thin film is repeated to form a multilayer semiconductor thin film single crystal layer on the semiconductor crystal substrate. After the semiconductor element is formed on the crystal layer, the semiconductor thin film single crystal layer is oxidized by leaving the seed portion as an insulating film, and the seed portion is separated from the substrate by the insulating film. A method for manufacturing a semiconductor thin film single crystal layer.
晶層を形成してなるものであることを特徴とする特許請
求の範囲第１項記載の半導体薄膜単結晶層の製造方法。2. The method for producing a semiconductor thin film single crystal layer according to claim 1, wherein the semiconductor single crystal substrate is formed by forming a single crystal layer on an insulating film.
部内に単結晶半導体膜をエピタキシャル成長せしめるこ
とを特徴とする特許請求の範囲第１項記載の半導体薄膜
単結晶層の製造方法。3. The method for producing a semiconductor thin film single crystal layer according to claim 1, wherein a single crystal semiconductor film is epitaxially grown in the opening before the semiconductor thin film is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP506987A JPH0793259B2 (en) | 1987-01-14 | 1987-01-14 | Method for manufacturing semiconductor thin film crystal layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP506987A JPH0793259B2 (en) | 1987-01-14 | 1987-01-14 | Method for manufacturing semiconductor thin film crystal layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63174308A JPS63174308A (en) | 1988-07-18 |
| JPH0793259B2 true JPH0793259B2 (en) | 1995-10-09 |
Family
ID=11601097
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP506987A Expired - Lifetime JPH0793259B2 (en) | 1987-01-14 | 1987-01-14 | Method for manufacturing semiconductor thin film crystal layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0793259B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2682128B1 (en) * | 1991-10-08 | 1993-12-03 | Thomson Csf | METHOD FOR GROWING HETEROEPITAXIAL LAYERS. |
| US5308445A (en) * | 1991-10-23 | 1994-05-03 | Rohm Co., Ltd. | Method of manufacturing a semiconductor device having a semiconductor growth layer completely insulated from a substrate |
| DE4400985C1 (en) * | 1994-01-14 | 1995-05-11 | Siemens Ag | Method for producing a three-dimensional circuit arrangement |
-
1987
- 1987-01-14 JP JP506987A patent/JPH0793259B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63174308A (en) | 1988-07-18 |
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