JPH0793302B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a multi-layer polysilicon structure.

[Conventional technology]

FIG. 2 is a cross-sectional view showing a method of manufacturing a semiconductor having a two-layer polysilicon structure which has been widely known in the past. In the figure, 11 is a silicon substrate, 12 is a first polysilicon layer (gate electrode), 13 is an interlayer insulating film, and 14 is a second polysilicon layer. In such a semiconductor having a two-layer polysilicon structure, a first polysilicon layer 12 and an interlayer insulating film 13 are formed on a silicon substrate 11 as shown in FIG.
A second polysilicon layer 14 is formed thereon as shown in FIG. In this case, since the second polysilicon layer 14 is the uppermost layer, even if a step is formed on the surface thereof, there is almost no functional problem.

However, with the demand for higher integration, higher density, and higher speed operation of semiconductor devices, the wiring area is substantially reduced to prevent the chip from increasing, the average wiring length is shortened, and the operation speed is delayed by the wiring resistance. A semiconductor device having a multilayer wiring structure (having a polysilicon structure with three or more layers) capable of suppressing the increase has been required. Then, in this multilayer wiring structure, an interlayer insulating film is further formed on the second polysilicon layer, and the third polysilicon layer is formed thereon. Therefore, if there is a step caused by the second polysilicon layer (lower wiring pattern) on the interlayer insulating film,
Step coverage (step coverage) defects may occur in the third polysilicon layer (upper layer wiring pattern). In order to prevent this, planarization treatment of the interlayer insulating film becomes important.

FIG. 3 is a cross-sectional view for explaining an example of the flattening process of the interlayer insulating film. In the figure, 21 is a silicon substrate, 22
Is a first polysilicon layer (gate electrode), 23 is an interlayer insulating film, and 24 is a second polysilicon layer. In this conventional example,
First, as shown in FIG. 1A, a first polysilicon layer 22 is formed on a silicon substrate 21, and a heat-flowable BPSG (boro-phospho-silicate glass) layer is formed thereon as an interlayer insulating film.
The film 23 is formed. After that, heat treatment is applied to the same (b) in FIG.
As shown in, the BPSG film 23 is flattened, and the second polysilicon layer 24 is formed thereon. Then, in order to lower the resistance value of the second polysilicon layer 24, heating and cooling steps for phosphorus diffusion are performed.

Further, in order to obtain a multilayer wiring structure, although not shown, an interlayer insulating film is formed on the second polysilicon layer 24 of FIG. 2B, and a third polysilicon layer is formed thereon. It is formed.

[Problems to be Solved by the Invention]

However, in the conventional manufacturing method shown in FIG. 3, heating and cooling steps for phosphorus diffusion are included after the formation of the second polysilicon layer 24. At this time, the second polysilicon layer 24 is heated by heat. Expansion and contraction caused the following problems. FIG. 4 is a sectional view showing such a problem. As shown in FIG. 4, wrinkles may be formed in the second polysilicon layer 24 near the periphery of the first polysilicon layer 21. Then, the wrinkles of the second polysilicon layer 24 flow into the inside thereof so that the heat-fluidic BPSG 23 is sucked thereinto to form hillocks H. That is, a step is formed in the second polysilicon layer 24 by the phosphorus diffusion step, and therefore, when a third or more polysilicon layer is formed on the second polysilicon layer 24, a problem such as coverage failure occurs. There was a risk of dots.

It should be noted that the hillock H has a distribution density in a plane arrangement as the first polysilicon layer 22 has a larger area and when a plurality of first polysilicon layers 22 are formed on the same silicon substrate 21. The less sparse, the more likely it is to occur, and the range A in Fig. 4
It is unlikely to occur in a portion where the distribution density of the plane arrangement is high as in the above.

Therefore, the present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device having a multi-layer wiring structure which prevents the occurrence of steps and has stable characteristics. Especially.

[Means for Solving the Problems]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first polysilicon layer at a predetermined position on an insulating substrate, and a step of insulating the first polysilicon layer so as to cover the first polysilicon layer. The method includes the steps of forming a heat-fluidic insulating film on a substrate, subjecting the insulating film to heat treatment to planarize the surface, and forming a second polysilicon layer on the insulating film. In the step of forming the silicon layer, a groove portion extending in the direction along the peripheral edge is formed at a position near the peripheral edge on the first polysilicon layer.

[Work]

In the present invention, in the step of forming the first polysilicon layer at a predetermined position on the insulating substrate, a groove extending in the direction along the periphery of the first polysilicon layer is formed near the periphery of the first polysilicon layer. is doing. Therefore, after the second polysilicon layer is formed, even if some slack occurs due to expansion and contraction due to thermal expansion of the second polysilicon layer, for example, when a heating and cooling process for phosphorus diffusion is performed, heat is generated. The insulating film having fluidity does not flow into the wrinkle-shaped slack portion but tries to flow into the groove portion formed in the first polysilicon layer. Therefore, the groove portion of the first polysilicon layer has a function of preventing generation of a lock on the second polysilicon layer near the periphery of the first polysilicon layer.

〔Example〕

 The present invention will be described below based on the illustrated embodiments.

FIGS. 1A and 1B are a cross-sectional view and a plan view for explaining a method for manufacturing a semiconductor device according to the present invention. here,
FIG. 10A shows a state where the second polysilicon layer is formed in the multilayer wiring structure, and FIG. 11B shows a state where the first polysilicon layer is formed. In the figure, 1 is a silicon substrate, 2 is a gate electrode (first polysilicon layer), 3 is a BPSG film as an insulating film, 4 is a second polysilicon layer, and 5 is a characteristic part of the present invention. It is a groove portion formed in the electrode 2.

The method of manufacturing the semiconductor device is basically the same as the process of the conventional example shown in FIG. 3 except that the groove 5 is formed when the gate electrode 2 is formed.

That is, in the first step, the gate electrode 2 is formed at a predetermined position on the silicon substrate 1 by using the photolithography technique. In FIG. 2B, the large-area gate electrode is 2a and the small-area gate electrode is 2b. In this embodiment, the large-area gate electrode 2a is formed in the vicinity of the peripheral edge, and a groove portion 5 having a portion extending in the peripheral edge direction and having a substantially U-shaped planar shape is formed. The groove 5 is formed by photolithography simultaneously with the formation of the gate electrode 2a. Further, the shape of the groove portion 5 may be an appropriate shape determined by various factors such as the thickness and area of the gate electrode 2a, the arrangement of the gate electrodes 2a and 2b, and the heat flow characteristics of BPSG. In the present embodiment, the planar shape of the groove portion 5 is formed in a substantially U shape having no groove portion on the gate electrode 2b side, the width thereof is made constant, and the corner portions are formed at 45 degrees with respect to the peripheral edge of the gate electrode 2a. It is formed to have an angle.

Here, the reason why the groove 5 is formed only in the large-area gate electrode 2a is that hillocks are more likely to be generated as the polysilicon layer has a larger area, and hillocks are rarely generated in the small-area gate electrode 2b. This is because. Further, the reason why the groove 5 has a substantially U-shaped planar shape and the groove is not formed on the side where the gate electrode 2b is located is that hillocks are more likely to occur as the planar arrangement distribution density of the polysilicon layer is sparser. ,
Since there is a property that it hardly occurs when the distribution density of the planar arrangement is dense, the side where the distribution density is dense, that is, the gate electrode 2b side (generally, a small area pattern inside the chip, a large area pattern Since it is formed on the outside of the chip,
This is because it is not necessary to form the groove portion in the case where the distribution density inside the chip becomes dense.

In the next step, an insulating film having thermal fluidity, for example, a BPSG film 3 is formed on the silicon substrate 1 having the gate electrode 2 by a CVD method or the like, and then heat treatment is performed to flatten the BPSG film 3. Here, AsSG (arse
no-silicate glass) and BSG (boro-silicate glass)
May be used.

Further, in the next step, a second polysilicon layer is formed on the flattened BPSG film 3. Thereafter, in order to reduce the resistance value of the second polysilicon layer 4, a heating and cooling process for phosphorus diffusion is performed to form a two-layer polysilicon structure.

In this embodiment, the first polysilicon layer 2 has a groove portion 5 extending in the direction along the peripheral edge in the vicinity of the peripheral edge.
Therefore, even if the second polysilicon layer 4 expands and contracts due to thermal expansion in the heating and cooling process and some slack occurs, the BPSG film having thermal fluidity does not flow into the wrinkled slack portion. , Tries to flow into the groove portion 5 formed in the first polysilicon layer 2a. Therefore, no hillock is generated in the first polysilicon layer 2a.

In the case of a multi-layer wiring structure, an insulating film is formed on the upper surface of the second polysilicon layer 4 by the same process, and the insulating film is formed thereon.
A polysilicon layer (not shown) over the second layer is formed. In this embodiment, as described above, the flat second polysilicon layer 4 free of hillocks can be obtained, so that it is possible to manufacture a semiconductor device having good characteristics without defects such as interlayer leakage.

〔The invention's effect〕

As described above, according to the present invention, the groove portion extending in the direction along the peripheral edge is formed in the vicinity of the peripheral edge of the first polysilicon layer, so that hillocks are generated on the second polysilicon layer. Can be prevented, and patterning in the subsequent steps can be performed in a good state. Therefore, even in the case of the multi-layer wiring structure, there is an effect that a semiconductor device having good characteristics can be manufactured without causing defects such as interlayer leakage.

[Brief description of drawings]

1 (a) and 1 (b) are a cross-sectional view and a plan view for explaining an embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIGS. 2 (a) and 2 (b) are conventional manufacturing methods. 3 (a) and 3 (b) are cross-sectional views showing a conventional method for manufacturing a multilayer wiring structure, and FIG. 4 is a cross-sectional view showing the problems of the conventional example of FIG. 1 ... Silicon substrate (insulating substrate), 2 ... Gate electrode (first polysilicon layer), 3 ... BPSG film (insulating film), 4
...... Second polysilicon layer.

Claims (1)

[Claims] 1. A step of forming a first polysilicon layer at a predetermined position on an insulating substrate, and a heat-flowable insulating film is formed on the insulating substrate so as to cover the first polysilicon layer. And a step of forming a second polysilicon layer on the insulating film by applying a heat treatment to flatten the surface. In the step of forming the first polysilicon layer, the second polysilicon layer is formed on the first polysilicon layer. A method of manufacturing a semiconductor device, comprising forming a groove portion extending in a direction along the peripheral edge at a position near the peripheral edge.