JPH0793322B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more specifically, to an enhancement type and depletion type field effect transistor,
The present invention relates to a semiconductor device that can be formed on the same compound semiconductor substrate.

[Background of the Invention]

In recent years, ultra-high-speed devices using gallium arsenide (GaAs) / aluminum gallium arsenide (AlGaAs) have been developed due to the development of ultra-high-precision crystal growth technologies such as MBE (Molecular Beam Epitaxy) technology and MOCVD (Metal Organic Thermal Decomposition). For example, JP-A-55
-132074) is being realized. Since no good insulating material has been found in GaAs / AlGaAs, Schottky junctions of metals and compound semiconductors are used in the gate structure of various field effect transistors (FETs).

For example, FIG. 1 shows a sectional view of a selectively doped heterojunction FET. 10 is a semi-insulating GaAs substrate, 11 is undoped GaAs,
12 is undoped called a spacer (impurity is not intentionally included, and as a result, an n ^- layer of about 10 ¹⁵ cm ^-3 is often formed)
When the thickness of the AlGaAs layer is e, it is usually about 60Å. 13 is an n-type AlGaAs layer and 14 is an n-type GaAs layer. AlGaAs layers 12, 13
When the total film thickness of is defined as d, it is usually about 500Å.

31 is the gate metal of the enhancement type FET (threshold voltage V _{th to} 0.1 V), and 30 is the depletion type FET (threshold voltage V _th
~ -0.8V; Channel is open at gate voltage V _G = 0V)
Is the gate metal. From a simple calculation, if the doping level of the n-type AlGaAs layer is N _D , the threshold voltage V _th is Can be expressed as

Here, φ _Bn is the height of the Schottky barrier between the gate metal and AlGaAs, ΔE _C is the size of the discontinuity at the conduction band edge between GaAs11 and AlGaAs12, q is the unit charge, and ε is AlGaAs.
, E represents the film thickness of the spacer layer 12, respectively. In order to improve the performance of such an FET, the simplest method is to reduce the film thickness d-e of the n-type AlGaAs layer 13, which is the most effective method. However, it is most desirable that the threshold voltage V _th of the enhancement-type FET is positive and close to 0 due to restrictions on the circuit configuration. Normally, it is set to 0.1 V, and this value is determined in consideration of the degree of fluctuation of the threshold voltage. However, if the film thickness d is reduced while keeping V _th constant, it is necessary to increase the doping level N _D as is clear from the above formula (1), and the maximum doping amount ▲ N ^max _D
The symbol () limits the minimum value (d-e) ^min of the n-type AlGaAs film thickness d-e. In the conventional MBE, it was the mainstream to use Si as an n-type dopant, and it was about (N ^max _D) = 7 × 10 ¹⁸ cm ⁻³ .

That is, for V _{th to} 0.1 V, (d−e) ^{min of} approximately 12
I had to set it to 0Å.

On the other hand, the source / drain current I _{dss in the} pentode region of each field effect transistor is I _dss = w · K (V _G −V _th ) ² …… (using the gate voltage V _G and the threshold voltage V _th. 2) can be expressed as However, w is the gate width of the transistor. One measure giving good transistor performance can be represented by the value of K. That is, it can be generally said that the larger the value of K, the better the device. In order to improve the performance of a normal FET, it is most effective to reduce the film thickness of the active layer doped with impurities (and the layer corresponding thereto). That is, the minimum film thickness is 100Å as long as Si is used as an n-type impurity.
Before and after.

On the other hand, in the high-concentration region of N _D 1 × 10 ¹⁸ cm ^-3 , there was a drawback that it was difficult to obtain good Schottky characteristics. That is, in the enhancement type FET, a gate leak current is generated from a low voltage when the gate voltage is positively applied, which has been a main factor for lowering transistor characteristics. On the other hand, in the case of the depletion type FET, the gate breakdown voltage cannot be sufficiently secured,
The drawback was that it wouldn't completely pinch off.

The same is true for GaAs MESFETs. That is, when the film thickness of the channel layer is reduced to improve the transistor characteristics, the transistor characteristics improve, but the Schottky characteristics of the gate metal deteriorate,
When the circuit is constructed, there is a drawback that the logic amplitude becomes small and the circuit design margin becomes small.

That is, as long as Si, which is the current n-type impurity, is used, the lower limit of the active layer film thickness is around 300Å, which is a limitation for improving the performance of the FET.

[Object of the Invention]

An object of the present invention is to insert a semiconductor layer (called a separation layer), which is not intentionally doped or slightly doped, between the Sn-doped layer and the gate metal so as to reduce the gate leakage current. Enhancement type FET by reducing and changing the thickness of this separation layer
And to provide a new gate structure capable of forming a depletion type FET on the same substrate.

[Outline of Invention]

The basic principle of the present invention will be described first. When a n-type doped channel layer or a semiconductor layer conforming to the channel layer is present in various FETs, a semiconductor layer that does not intentionally contain impurities or is slightly doped (hereinafter referred to as a separation layer) is used. When a metal that is inserted to form a Schottky junction is used for the gate electrode, the threshold voltage V _{th of the} FET can be changed by changing the thickness of the separation layer.
(Or the pinch-off voltage V _P ) can be changed.

Based on this principle, enhancement type FET (E-FE
T: V _th > 0) and depletion type FET (D-FET: V _th <0)
Are formed on the same substrate.

First, a normal n-channel MESFET (metal semiconductor field effect transistor: Metal)
N After quantitatively describes an example in which the present invention to S emiconductor F ield E ffect T ransistor ) using the second FIG
Channel Selectively doped heterojunction type
Doped Heterostructural: S electively D ope
The example was performed d H eterostructure) FET using a third FIG explained.

FIG. 2 shows a cross-sectional structure diagram when the E-FET and D-FET of the GaAs MESFET of the present invention are formed on the same substrate. 10 is a semi-insulating GaAs substrate, 11 is p ^- type undoped GaAs
(Doping level of about 10 ¹⁵ cm ⁻³ ), 15 is an n-type GaAs layer forming an n-type channel, the film thickness is d, and the doping level is N _D. Reference numeral 16 denotes an undoped (or n ⁻ or p ⁻ slightly doped) GaAs or Al _x Ga _1-x As layer having a thickness of C ₁ . 17 designates an undoped (or n ^- or p ^- slightly doped) GaAs or Al _x Ga _1-x As the film thickness layer C ₂ -C ₁
And Reference numeral 31 is a gate metal electrode of the enhancement type FET, and 30 is a gate metal electrode of the depletion type FET. 3
Reference numerals 2, 33 and 34 are ohmic source / drain electrodes.

Ignoring the effect of undoped GaAs layer 11, E-FET and DF
ET threshold voltages V _TE and V _TD are Can be written as Here, V _b1 is a built-in potential, q is a unit charge, and ε is a static dielectric constant of GaAs. However, the expressions (3) and (4) are equations when the doping level of each of the undoped layers 16 and 17 is negligibly small compared to the doping level of the channel layer 15. Further, 16 and 17 are equations for the same GaAs as the channel layer 15. One or both of the undoped layers 16 and 17 are Al _x Ga _1-x As
The equation in the case of substituting for can also be derived from the same kind as the equations (3) and (4). Clearly from equations (3) and (4),
Doping level of doping layer 15 (channel layer)
V _th can be controlled by appropriately selecting the film thicknesses C ₁ and C ₂ of the separation layers (undoped layers) 16 and 17 with N _D and the film thickness d being constant.

In this way, the E-FET and D-FET can be formed on the same substrate by keeping the film thickness and the doping level of the doping layer constant and changing the film thickness of the separation layer.
It is extremely effective for trial production. That is, if such a gate structure is adopted, the transistor performance can be improved by reducing the film thickness of the channel layer, and the deterioration of the Schottky characteristic can be prevented. Further, the E-FET and the D-FET are formed on the same substrate. be able to.

Next, the effect of applying the gate structure of the present invention to an n-channel selectively doped heterojunction FET will be described with reference to FIG. 12 is undoped Al _x Ga called a spacer layer
_{It is a 1-x} As layer, and the mixed crystal ratio x is usually selected to be 0.3 or more. Reference numeral 13 is an n-type doping layer made of Al _y Ga _1-y As, and the mixed crystal ratio y is selected to be about 0.10 to 0.20. Reference numeral 18 denotes a separation layer, which is an undoped (or weakly doped n ⁻ or p ⁻ type) film having a film thickness C ₁ Al _z Ga _{1 -z} As (0 ≦ z ≦
1) is a layer, and 19 is also a separation layer and is normally undoped (or weakly doped n ⁻ or p ⁻ type) GaAs having a film thickness C ₂ -C ₁ . 31 is the metal of the E-FET gate electrode, 30
Is a gate electrode metal of D-FET and 31,32,33 are source / drain metals.

For simplicity, assuming that the Al mixed crystal ratios x of the separation layers 18 and 19, the n-type doping layer 13 and the spacer layer 12 are the same x = 0.3, the effect of the undoped layer 11 of the substrate is usually negligible. , E-FET and D-FET thresholds V _TE and V _TD are Can be written as

The symbol has some parts in common with the formula (1).

That is, as is clear from this equation, by appropriately selecting the film thicknesses C ₁ and C ₂ of the separation layer, the E-FET and D-FET can be realized on the same substrate, and a gate having a better Schottky junction can be realized. Since the electrodes can be formed, the logic amplitude, which is important in the circuit configuration, can be increased.

In particular, if the separation layer is composed of the two-layer films 18 and 19 as shown in FIG. 3 and has a structure capable of selective etching (for example, 18 is an AlGaAs layer 19 and a GaAs layer), the thickness of the separation layer is accurate. Can be controlled.

Conventionally, in the MBE method, silicon (Si) and tin (Sn) have been used as n-type impurities for GaAs and AlGaAs. But usually
Since Sn has a high Sn concentration on the epitaxial surface, it tends to deteriorate the Schottky characteristics, and conventionally, in a normal n-channel GaAs MESFET / selectively doped heterojunction type FET that does not have a separation layer, Si is used as an n-type impurity. It was customary to use.

However, it is known that the maximum doping amount of Sn into GaAs and AlGaAs is nearly one digit higher than that of Si [eg, "Physics and Applications of Semiconductor Superlattices" p.121, Physics Society of Japan, Baifukan 1984]. .

Also, when a separation layer is provided as in the FET related to the present invention, the precipitation of Sn on the epitaxial surface is not a problem.

That is, due to the presence of the separation layer, the active layer of the n-type semiconductor layer that is in direct contact with the gate metal is greatly suppressed, and because of the presence of the spacer layer, Sn does not precipitate to the heterojunction interface, and the active layer of Sn is not deposited. It does not deteriorate.

It is also possible to form a phase correction FET by forming the n-channel FET of the present invention on the same substrate as other p-channel FETs.

Example of Invention

 Hereinafter, the present invention will be described in more detail with reference to Examples.

Example 1 FIGS. 4 (a) to 4 (e) show steps to be performed when the present invention is applied to a FET having a so-called selectively doped heterojunction structure in which a two-dimensional electron gas is used for a channel layer. Insulating GaAs
P ⁻ (up to 5 × 10 ¹⁴ cm ⁻³ ) GaAs on the substrate 10 by MBE method
Layer 11 is grown to 1 μm. Then n ^- type undoped Al _x Ga _1-x
The As (usually x is selected to be 0.3 or more) layer 12 was grown by 60Å. Subsequently, an n-type Al _y Ga _1-y As (usually used in the range of 0.05 to 0.20) layer 13 containing 5 × 10 ¹⁹ cm ^{-3 of} Sn as an n-type impurity is grown to 30 Å to separate the separation layer. As the undoped n ⁻ type Al _z Ga _1-z As (usually used at z of about 0.3) layer 18 was grown to 60 Å. Furthermore, undoped n ^- type
GaAs layer 19 is grown to 100Å and SiO ₂ layer 40 is used for surface protection.
Was formed using the 2000Å CVD method (Fig. 4a).

Next, after performing element isolation by mesa etching, the undoped and separation layers 18 and 19 are removed by etching,
Source / drain electrodes (AuGe / Ni / A
u: 900Å / 150Å / 2000Å) 32,33,34 were formed (Fig. 4b). For the purpose of forming the gate electrode of the E-FET, the undoped GaAs layer 19 is selectively etched with a CCl ₂ F ₂ / He mixed gas, and the separation layer 18 is formed with Ti as a Schottky electrode.
/ Pt / Au (1000Å / 500Å / 2000Å) was formed (Fig. 4c). Then, the step of forming the gate electrode of the D-FET on the undoped GaAs layer was performed (Fig. 4d). Also in this case, Ti / Pt / Au was used as the gate metal. In this way, an E-FET (threshold voltage V _th is 0.18 V in this case) and a D-FET (threshold voltage is -0.72 V in this case) can be formed on the same substrate. did it.

In the present invention, the gate metal is directly bonded to the highly-doped layer, which is a major drawback of the conventional method (conventionally, the E / D FET structure has been realized by changing the thickness of the doped layer). It was possible to overcome the deterioration of the gate electrode characteristics caused by.

Furthermore, by doping with Sn, the conventional AlGaAs film thickness is 300Å
It was possible to reduce the thickness to 150Å.
As a result the value of K that shown in (2) are those in gate length 1μm level been made in the prior 3.5mA / V ² about could be increased up to 7.0 mA / V ^2.

Further, in this embodiment, 19 semiconductor layers of the separation layers 18 and 19 of the D-FET may be n-type doped (FIG. 4).
e19 '). Although the Schottky characteristic is deteriorated by the n-type doping, there is no problem in the case of using the D-FET without pinching off in the circuit.

Example 2 An example of applying the present invention to a GaAs MESFET is shown in FIGS.

Undoped GaA on an insulating GaAs substrate 10 by MBE method.
n-type GaA doped with 4 × 10 ¹⁹ cm ^-3 Sn after growing s layer to 2 μm
The s layer 15 was grown to 30 Å and then Si was doped to about 10 ¹⁴ cm ^-3.
- type Al _x Ga _1-x As (about X～0.3) layer 16 is 100Å growth,
Furthermore, the n ^- GaAs layer 17 doped with Si at about 10 ¹⁴ cm ^-3 is 100 Å
It was grown (Fig. 5a). Next, the GaAs layer 17 of the separation layer is removed by a selective etching method using a mixed gas of CCl ₂ F ₂ / He in the region where the E-FET is formed (FIG. 8B). After removing etching damage by heating at 400 ℃ for 5 minutes,
Highly heat-resistant metal WSi51 (tungsten silicide) was formed on the entire surface at 3000 liters (Fig. 5b). Subsequently, dry etching and photolithography were used to remove WSi (51, 51 ') in the gate electrode portion and to remove other WSi. After depositing 500 Å SiO ₂ by the CVD method, Si 52 was ion-implanted with an acceleration energy of 50 keV and a dose of 3 × 10 ¹³ cm ^-2 . After implantation, lamp annealing is performed at 850 ° C for 15 seconds.
The i atom 53 was activated (Fig. 5c). Then, the required portion of SiO ₂ is removed by etching, and the source / drain metal (Au
Ge / Ni / Au) 32, 33, and 34 were deposited and alloyed at 400 ° C. for 3 minutes to form source / drain electrodes.

By using an active layer doped with Sn as described above, the thickness can be reduced to 130 Å. By using the gate structure of the present invention, the gate leakage current is E-FET and the gate voltage V _G = 1.1.
It becomes almost negligible up to V, and for D-FET
The gate leakage current has been drastically reduced to a value close to 0.8V, which is the height of the SHOTTOKI barrier, which is the original value of GaAs, and the reverse breakdown voltage has also been improved from 0.8V without a separation layer to 5.0V.

In this embodiment, the semiconductor layer 17 forming the top of Separeshiyon layer 16 n ^- is a semiconductor layer, which is necessarily n ^-
It does not have to be a layer. That is, a semiconductor layer doped to a usual ^{concentration of} about 10 ¹⁷ cm ^-3 can be used.

Further, the n-channel FET using the gate structure of the present invention and Sn for the active layer is another p-channel FET [selectively doped heterojunction FET using two-dimensional hole gas, instead of the n-type active layer 15 in Example 2]. It is also effective when forming a complementary FET by forming Be on the same substrate as a p-channel GaAs MESFET or the like which changes Be into a p-type layer containing 4 × 10 ¹⁹ cm ^-3 .
Further, in the above-mentioned embodiment, the thickness and the doping level of the channel layer are shown to be within a specific range, but it can be changed depending on the application field.

〔The invention's effect〕

According to the present invention, a gate structure in which an undoped or slightly doped semiconductor layer (separation layer) is inserted between a gate electrode and a channel layer doped with Sn impurities, and the thickness of the separation layer is changed. In order to make enhancement type FET and depletion type FET separately, it is possible to (1) make the active layer (and the layer corresponding to it) extremely thin, and it is possible to take about twice the current of the conventional FET characteristics. It became.

(2) An enhancement type FET (E-FET) with a small gate leak current and a large logic amplitude can be formed,
And (3) Depletion type FET (D
-FET) can be formed.

Due to the above effects, an extremely excellent E-FET / D-FET can be formed in the same substrate, which makes a particularly excellent contribution to a circuit configuration using both E-FET and D-FET.

[Brief description of drawings]

FIG. 1 is a sectional view of a conventional selectively doped heterojunction FET, FIGS. 2 and 3 are sectional views of a MESFET and a selectively doped heterojunction FET of the present invention, and FIG. 4 is a selectively doped heterojunction of the present invention. FIG. 5 is a process drawing showing an example of a case where the present invention is applied to a GaAs MESFET. 10 ... Semi-insulating GaAs substrate, 11 ... Undoped GaAs layer, 12
…… Undoped Al _x Ga _1-x As layer, 13 …… Sn-doped n-type Al _y G
a _1-y As layer, 14, 15 ...... Sn-doped n-type GaAs layer, 16, 18 ...... undoped (or ^{_{n -) Al z Ga 1-}} z As, 17,19 ...... undoped (or n ^-) GaAs , 31,32 …… Gate electrode, 32,33,34 ……
Source / drain electrodes, 40 ... Protective film made of insulator,
19 '... n-type GaAs.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/812 9171-4M H01L 29/80 H (72) Inventor Yoshihisa Fujisaki 1 Higashi Koigakubo, Kokubunji, Tokyo 280-chome, Central Research Laboratory of Hitachi, Ltd. (72) Inventor Shigeo Goto 1-280, Higashikoigakubo, Kokubunji, Tokyo Metropolitan Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-50-119580 (JP, A) Kai 53-63985 (JP, A) JP 57-193067 (JP, A) JP 58-147158 (JP, A)

Claims (4)

[Claims] 1. In a semiconductor device having a Schottky field effect transistor, an undoped first semiconductor layer formed in contact with a Schottky gate electrode of the Schottky field effect transistor, and the first semiconductor layer. A second semiconductor layer formed in contact with the first semiconductor layer, and the thickness C of the first semiconductor layer is the built-in potential of the Schottky gate electrode is V _bi, and the thickness of the second semiconductor layer is When the impurity concentrations are d and N _D , respectively, (Here, q is a unit charge, and ε is a dielectric constant of the first semiconductor layer). A semiconductor device having a first Schottky field effect transistor set to satisfy the inequality. 2. The semiconductor device according to claim 1, wherein the film thickness C of the first semiconductor layer is (Wherein q is a unit charge, and ε is a dielectric constant of the first semiconductor layer), and a second Schottky field effect transistor is set on the same substrate so as to satisfy the inequality. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 2, wherein the first semiconductor layer of the second Schottky field effect transistor comprises a two-layer film. 4. The semiconductor device according to claim 3, wherein the layer of the two-layer film farther from the Schottky gate electrode is made of AlGaAs, and the layer closer to the Schottky gate electrode is made of GaAs.