JPH0793326B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0793326B2 JPH0793326B2 JP62147262A JP14726287A JPH0793326B2 JP H0793326 B2 JPH0793326 B2 JP H0793326B2 JP 62147262 A JP62147262 A JP 62147262A JP 14726287 A JP14726287 A JP 14726287A JP H0793326 B2 JPH0793326 B2 JP H0793326B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- semiconductor device
- insulating layer
- layer
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
- H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/321—Structures or relative sizes of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Die Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置に関し、特に大電力用半導体装置
の電極が固着される導電層が、熱応力により絶縁層へク
ラツクを生じさせるのを防ぐための、応力集中を緩和す
る構造に関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and particularly to preventing a conductive layer to which an electrode of a high power semiconductor device is fixed from causing a crack in an insulating layer due to thermal stress. Therefore, the present invention relates to a structure for relaxing stress concentration.
トランジスタの大電流容量化の進歩と共に、これらの素
子を組込んだ大電力用パワーモジユールも種々のものが
出現しているが、大容量化に伴う設計上の課題の一つは
組合せ部材の熱膨張係数差により生ずる過大な熱応力の
問題である。Along with the progress of high current capacity of transistors, various power modules for high power incorporating these elements have appeared, but one of the design problems associated with the high capacity is the combination of members. This is a problem of excessive thermal stress caused by the difference in thermal expansion coefficient.
もしこの応力が絶縁層に生じると、破損して絶縁不良を
起すことになるので設計に当つては細心の注意を要す
る。If this stress is generated in the insulating layer, it will be damaged and cause insulation failure, so careful design is necessary.
第５図は従来の大電力用パワーモジユールの一実施例を
示す透視平面図であり、第６図はそのVI−VI線に沿う断
面図である。FIG. 5 is a perspective plan view showing an embodiment of a conventional high power power module, and FIG. 6 is a sectional view taken along line VI-VI thereof.
図において、（１）は放熱板で、銅またはアルミニウム
材により、例えば3mm程度に形成される。（２）は絶縁
層で、例えばセラミツクの溶射、或いはマイラフイルム
の熱圧着もしくは絶縁材をコーテイングして80μｍ程度
に形成され、放熱板（１）に接着される。（３）はベー
ス用導電層、（４）はエミツタ用導電層、（５）はコレ
クタ用導電層で、これらの導電層（３），（４），
（５）は、例えば導箔とアルミニウム箔を予め貼り合せ
て100μｍ程度に形成したものを絶縁層（２）上に接着
し、フオト・リソグラフイ技術により選択エツチングし
て所定の形状に形成される。（６）は銅材より成る約2m
m厚さのヒートシンクで、コレクタ用導電層（５）に接
着される。（７）はトランジスタチツプで、ヒートシン
ク（６）に接着される。（８）はアルミニウム線より成
るリードワイヤで、ワイヤボンデイングによりトランジ
スタチツプ（７）の電極部とベース用導電層（３）、或
いはエミツタ用導電層（４）間を接続する。（９）はベ
ース電極、（10）はエミツタ電極、（11）はコレクタ電
極で、いずれも銅材で形成され、導電層（３），
（４），（５）にそれぞれ接着される。（12）は例えば
プラスチツクより成るケースで、絶縁層（２）上に接着
して組立てられる。（13）は封止樹脂で、シリコンゲル
及びエポキシ樹脂を封入した後200〜300℃の温度で加
熱，硬化される。なお、各部品の接着は半田付けにより
なされる。In the figure, (1) is a heat radiating plate, which is made of copper or aluminum and has a thickness of, for example, about 3 mm. Reference numeral (2) is an insulating layer, which is formed to have a thickness of about 80 μm by, for example, thermal spraying of ceramics, thermocompression bonding of myrafilm or coating of an insulating material, and is bonded to the heat dissipation plate (1). (3) is a conductive layer for a base, (4) is a conductive layer for an emitter, (5) is a conductive layer for a collector, and these conductive layers (3), (4),
(5) is formed into a predetermined shape by, for example, attaching a conductive foil and an aluminum foil in advance and forming them to a thickness of about 100 μm, and adhering them onto the insulating layer (2), and selectively etching them by the photolithography technique. . (6) is about 2m made of copper material
A heat sink of m thickness is adhered to the conductive layer (5) for collector. (7) is a transistor chip, which is bonded to the heat sink (6). Reference numeral (8) is a lead wire made of an aluminum wire, which connects the electrode portion of the transistor chip (7) and the conductive layer for base (3) or the conductive layer for emitter (4) by wire bonding. (9) is a base electrode, (10) is an emitter electrode, (11) is a collector electrode, both of which are made of a copper material, and have conductive layers (3),
It is adhered to (4) and (5) respectively. (12) is a case made of plastic, for example, and is assembled by being bonded onto the insulating layer (2). (13) is a sealing resin, which is heated and cured at a temperature of 200 to 300 ° C. after encapsulating silicon gel and epoxy resin. The components are bonded by soldering.
従来の大電力用パワーモジユールは上記のように構成さ
れ、各電極（９），（10），（11）を介して外部回路
（図示せず）に接続されてその機能を発揮する。The conventional high-power power module is configured as described above, and is connected to an external circuit (not shown) via each electrode (9), (10), (11) to exert its function.
上記のような従来の大電力用パワーモジユールでは、大
容量になる程その配線抵抗を低くするために、導電層
（３），（４），（５）の層厚さは厚く形成される。In the conventional power module for large power as described above, the conductive layers (3), (4) and (5) are formed to have a large layer thickness in order to lower the wiring resistance as the capacity increases. .
ところが、導電層（３），（４），（５）は絶縁層
（２）上に半田付けされているが、その熱膨張係数は前
者が約20×10-6に対して後者のそれは約26×10-6と大き
いため、組立工程中の加熱温度により熱膨張差を生じ、
導電層（３），（４），（５）の下端部に大きな熱応力
が集中して、この部位の絶縁層（２）にクラツクが発生
するという不具合があつた。However, the conductive layers (3), (4), and (5) are soldered on the insulating layer (2), but the coefficient of thermal expansion of the former is about 20 × 10 −6 while that of the latter is about 20 × 10 −6 . Since it is as large as 26 × 10 -6 , a difference in thermal expansion occurs due to the heating temperature during the assembly process,
A large thermal stress is concentrated on the lower ends of the conductive layers (3), (4), and (5), and the insulating layer (2) at this portion is cracked.
しかも、この現象は導電層（３），（４），（５）の層
厚さが厚くなつて、その剛性を増すほど発生し易く、特
に層厚さが100μｍを超えるとその傾向は顕著となり、
パワーモジユールを大容量化する上で障害となつてい
た。Moreover, this phenomenon is more likely to occur as the rigidity of the conductive layers (3), (4) and (5) increases, and the tendency becomes remarkable especially when the layer thickness exceeds 100 μm. ,
It was an obstacle to increasing the capacity of the power module.
この発明は、かかる問題点を解決するためになされたも
ので、大容量化されて導電層の厚みが増しても、絶縁層
にクラツクを生じて絶縁不良を起すことのない半導体装
置を得ることを目的とする。The present invention has been made in order to solve such a problem, and obtains a semiconductor device which does not cause insulation failure due to cracking in the insulating layer even if the capacity is increased and the thickness of the conductive layer is increased. With the goal.
この発明に係る半導体装置は、放熱板に固着された絶縁
層上に、半導体素子と外部電極導電層とが固着された導
電層を接着材により固着したものにおいて、導電層が絶
縁層より歪み易い材料で構成されるとともに導電層の端
縁部を、該導電層の他の部分よりも薄く形成したもので
ある。In the semiconductor device according to the present invention, a conductive layer in which the semiconductor element and the external electrode conductive layer are fixed to each other is fixed to the insulating layer fixed to the heat dissipation plate by an adhesive, and the conductive layer is more easily distorted than the insulating layer. The conductive layer is made of a material and the edge portion of the conductive layer is formed thinner than other portions of the conductive layer.
この発明においては、導電層が絶縁層より歪み易い材料
で構成されるとともに導電層の端縁部が導電層の他の部
分よりも薄く形成されているので、絶縁層とその上に接
着材により固着されている導電層間に熱膨張差を生じて
も導電層下端部の応力集中は緩和され、絶縁層にクラツ
クを生じることはない。なお、この効果は、導電層の厚
みが増す程、導電層の端縁部が薄く形成されていないも
のに比べて顕著となる。In the present invention, the conductive layer is made of a material that is more easily distorted than the insulating layer, and the edge portion of the conductive layer is formed thinner than the other portions of the conductive layer. Even if a difference in thermal expansion occurs between the fixed conductive layers, the stress concentration at the lower end of the conductive layer is relieved and the insulating layer is not cracked. Note that this effect becomes more remarkable as the thickness of the conductive layer increases, as compared with the case where the edge portion of the conductive layer is not formed thin.
第１図は、この発明の大電力用パワーモジユールの一実
施例を示す透視平面図、第２図は、そのII−II線に沿う
断面図であり、（１）〜（13）は上記従来の大電力用パ
ワーモジユールにおけるものと同一又は相当のものであ
る。なお、導電層（３），（４），（５）は100〜150μ
ｍ厚さに形成し、その端縁を傾斜をつけて薄く形成する
のは、導電層（３），（４），（５）をフオト・リソグ
ラフイ技術を用いて選択エツチングにより形成する際、
フオト・レジスト層（図示せず）と導電層（３），
（４），（５）との界面の密着度或いはエツチング時間
を適当に制御する等により実現できた。FIG. 1 is a perspective plan view showing an embodiment of the high power power module of the present invention, and FIG. 2 is a sectional view taken along line II-II thereof, wherein (1) to (13) are the above. It is the same as or equivalent to that in the conventional power module for high power. The conductive layers (3), (4) and (5) are 100 to 150 μm.
When the conductive layers (3), (4), and (5) are formed by selective etching using the photolithography technique, the conductive layers (3), (4), and (5) are formed with a thickness of m
A photo resist layer (not shown) and a conductive layer (3),
This can be realized by appropriately controlling the degree of adhesion at the interface with (4) and (5) or the etching time.
上記のように構成された大電力用パワーモジユールにお
いて、組立工程中の温度により絶縁層（２）と導電層
（３），（４），（５）との間に熱膨張差を生じると、
熱膨張係数の大きな絶縁層（２）は膨張して導電層
（３），（４），（５）を包み込むように湾曲しようと
する。このため、導電層（３），（４），（５）の下端
部に大きな応力が生じるが、導電層（３），（４），
（５）の端縁部が傾斜をつけて薄く形成され、先端部の
剛性が低下しているので、変形されてこの部分の応力集
中は緩和され、絶縁層（２）でのクラツク発生が防止さ
れる。In the power module for high power configured as described above, when a difference in thermal expansion occurs between the insulating layer (2) and the conductive layers (3), (4), (5) due to the temperature during the assembly process. ,
The insulating layer (2) having a large thermal expansion coefficient expands and tries to be curved so as to wrap around the conductive layers (3), (4) and (5). For this reason, a large stress is generated at the lower ends of the conductive layers (3), (4), (5), but the conductive layers (3), (4),
Since the edge of (5) is formed thin with an inclination and the rigidity of the tip is lowered, it is deformed and stress concentration in this part is relieved, and cracking in the insulating layer (2) is prevented. To be done.
なお、上記実施例においては、導電層（３），（４），
（５）の端縁部が直線状の傾斜をつけて形成されたもの
を示したが、形成上の都合から、要すれば第３図の他の
実施例における要部拡大図に示すように曲線状の傾斜を
つけて形成されたものであつても、また、第４図の更に
他の実施例における要部拡大図に示すように、段落状に
形成されたものでも同様の効果を奏することはいうまで
もない。また、トランジスタチツプを１個搭載した大電
力用パワーモジユールの例を示したが、複数個を他の回
路素子と共に搭載するものであつてもよい。In the above embodiment, the conductive layers (3), (4),
Although the edge portion of (5) is formed with a linear inclination, it is shown in the enlarged view of the main portion in another embodiment of FIG. The same effect can be obtained even if it is formed so as to have a curved inclination, or if it is formed in a paragraph shape, as shown in the enlarged view of the main part in yet another embodiment of FIG. Needless to say. Also, an example of a power module for high power in which one transistor chip is mounted is shown, but a plurality of power chips may be mounted together with other circuit elements.
この発明は以上説明したとおり、放熱板に固着された絶
縁層上に接着材により固着された導電層が絶縁層より歪
み易い材料で構成されるとともに導電層の端縁部を、該
導電層の他の部分よりも薄く形成するという簡単な構造
により、組立工程中に受ける加熱に基づく過大な熱応力
の集中を緩和でき、絶縁層のクラツク発生による絶縁不
良を生じない大容量の半導体装置を得られる効果があ
る。As described above, according to the present invention, the conductive layer fixed by the adhesive on the insulating layer fixed to the heat dissipation plate is made of a material that is more easily distorted than the insulating layer, and the edge of the conductive layer is With a simple structure that is thinner than other parts, it is possible to reduce the concentration of excessive thermal stress due to heating that is received during the assembly process, and obtain a large-capacity semiconductor device that does not cause insulation failure due to cracking of the insulating layer. It is effective.
第１図は、この発明の一実施例を示す透視平面図、第２
図は、そのII−II線に沿う断面図、第３図は、この発明
の他の実施例を示す導電層の要部拡大図、第４図は、こ
の発明の更に他の実施例を示す導電層の要部拡大図、第
５図は、従来の大電力用パワーモジユールの一実施例を
示す透視平面図、第６図は、そのVI−VI線に沿う断面図
である。 図において、（１）は放熱板、（２）は絶縁層、（３）
はベース用導電層、（４）はエミツタ用導電層、（５）
はコレクタ用導電層、（６）はヒートシンク、（７）は
トランジスタチツプ、（８）はリードワイヤ、（９）は
ベース電極、（10）はエミツタ電極、（11）はコレクタ
電極である。 なお、各図中、同一符号は同一又は相当部分を示す。FIG. 1 is a perspective plan view showing an embodiment of the present invention, and FIG.
FIG. 4 is a sectional view taken along the line II-II, FIG. 3 is an enlarged view of a main part of a conductive layer showing another embodiment of the present invention, and FIG. 4 shows still another embodiment of the present invention. FIG. 5 is a perspective plan view showing an example of a conventional high power power module, and FIG. 6 is a sectional view taken along line VI-VI thereof. In the figure, (1) is a heat sink, (2) is an insulating layer, and (3)
Is a conductive layer for a base, (4) is a conductive layer for an emitter, (5)
Is a conductive layer for collector, (6) is a heat sink, (7) is a transistor chip, (8) is a lead wire, (9) is a base electrode, (10) is an emitter electrode, and (11) is a collector electrode. In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (4)
り導電層が固着され、該導電層上に半導体素子と外部電
極が適宜固着されて電気的に接続されている半導体装置
において、該導電層が上記絶縁層より歪み易い材料で構
成されるとともに該導電層の端縁部が該導電層の他の部
分よりも薄く形成されていることを特徴とする半導体装
置。1. A semiconductor device in which a conductive layer is fixed on an insulating layer fixed to a heat dissipation plate with an adhesive, and a semiconductor element and external electrodes are appropriately fixed on the conductive layer and electrically connected to each other. A semiconductor device, wherein the conductive layer is made of a material that is more easily distorted than the insulating layer, and an edge portion of the conductive layer is formed thinner than other portions of the conductive layer.
形成されていることを特徴とする特許請求の範囲第１項
記載の半導体装置。2. The semiconductor device according to claim 1, wherein the edge portion of the conductive layer is formed with a linear inclination.
形成されていることを特徴とする特許請求の範囲第１項
記載の半導体装置。3. The semiconductor device according to claim 1, wherein an end edge portion of the conductive layer is formed with a curved slope.
ていることを特徴とする特許請求の範囲第１項記載の半
導体装置。4. The semiconductor device according to claim 1, wherein the edge portion of the conductive layer is formed with paragraphs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62147262A JPH0793326B2 (en) | 1987-06-11 | 1987-06-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62147262A JPH0793326B2 (en) | 1987-06-11 | 1987-06-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63310125A JPS63310125A (en) | 1988-12-19 |
| JPH0793326B2 true JPH0793326B2 (en) | 1995-10-09 |
Family
ID=15426254
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62147262A Expired - Lifetime JPH0793326B2 (en) | 1987-06-11 | 1987-06-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0793326B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09275165A (en) * | 1996-02-07 | 1997-10-21 | Hitachi Ltd | Circuit board and semiconductor device using the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5235580A (en) * | 1975-09-12 | 1977-03-18 | Mitsubishi Electric Corp | Element fixing method of semiconductor device |
| JPS58159336A (en) * | 1982-03-17 | 1983-09-21 | Nec Corp | Semiconductor device |
| JPS60157229A (en) * | 1984-01-25 | 1985-08-17 | Mitsubishi Electric Corp | Insulation type semiconductor device |
-
1987
- 1987-06-11 JP JP62147262A patent/JPH0793326B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09275165A (en) * | 1996-02-07 | 1997-10-21 | Hitachi Ltd | Circuit board and semiconductor device using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63310125A (en) | 1988-12-19 |
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