JPH0793367B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device including a single transistor and a single capacitor, a so-called one-transistor type dynamic memory cell, and a method for manufacturing the same.

[Conventional technology]

Conventionally, as this type of memory cell, a memory cell structure in which a transistor and a capacitor are arranged in series along the depth direction of the groove on the side surface of the groove formed on the main surface of the semiconductor substrate has been proposed. This is described in, for example, Japanese Patent Application No. 59-143230.
No.

FIG. 9 is a sectional view showing an example of the structure of this memory cell,
The transfer transistor 2 and the groove capacitor 3 are arranged in series along the side surface of the groove formed almost vertically in the silicon substrate 1, and the isolation region 4 is arranged at the bottom of the groove. Reference numeral 5 is a self-plate forming one electrode of the capacitor, 6 is a gate electrode and word line of the transfer transistor 2, 7 and 8 are high impurity regions forming source and drain, and 9 is a semiconductor having a conductivity type different from that of the substrate 1. Region, 10 is an isolation oxide film, 11 is a semiconductor region having the same conductivity type as the channel cutting substrate and a high impurity concentration,
12 is a bit line.

In the above structure, since the transistor and the capacitor are arranged in series along the depth direction, the length of the transfer gate for increasing the memory cell capacity and reducing the subthreshold leakage can be achieved without increasing the planar size. It is possible to realize channelization. Further, since the transistor and the capacitor can be formed in a self-aligned manner, there is no need for a margin for alignment between them, and the structure is suitable for increasing the density of memory cells. FIG. 10 shows a plan view of the same structure, in which the memory cells are arranged in an island shape in the intersection region between the bit line 12 and the gate electrode / word line 6 of the transfer transistor 2.

[Problems to be solved by the invention]

However, in the structure as described above, the gate electrode of the transfer transistor is formed in the region 13 surrounding the island-shaped cell region, so that the overlapping area with the substrate is likely to be large and it is difficult to reduce the capacitance between the word line and the substrate. . This not only hinders speeding up due to miniaturization, but also hinders miniaturization of the word line driving circuit and hinders power saving.

[Means for solving problems]

In order to solve such a problem, the present invention forms a lattice-shaped groove formed on a main surface of a semiconductor substrate and a first insulating film on a side surface of the groove to a depth midway of the groove. A first conductive layer, a second conductive layer formed on a predetermined region of the grid-shaped first conductive layer with a second insulating film interposed, and a predetermined region Other than that, an insulating film formed is provided.

Further, in the manufacturing method, a step of forming a lattice-shaped groove on the main surface of the semiconductor substrate, a step of forming a first insulating film on at least a side surface of the groove, and a first conductor up to a predetermined depth in the groove. And a second step on the first conductor.
The step of forming the insulating film, the step of forming the third insulating film in a region other than the partial region where the transistor is formed on the second insulating film, and the process of forming the third insulating film in the partial region on the second insulating film. And a step of forming a second conductor.

[Action]

According to the present invention, the capacitance between the gate electrode of the transfer transistor and the substrate, that is, the word line load capacitance can be reduced, and high speed operation and power saving can be achieved.

〔Example〕

FIG. 1 is a sectional view showing an embodiment of a semiconductor memory device according to the present invention. In FIG. 1, 1 is a p-type silicon substrate, 2 is a transfer transistor, 3 is a groove capacitor formed on a side surface of a silicon island partitioned by lattice-shaped grooves formed on the silicon substrate 1, and 4 is a lattice. The element isolation region formed at the bottom of the groove is formed in the shape of a groove, and 7 is an n ⁺ region that is one of the source and the drain formed on the upper part of the silicon island.
Is a cell plate as a first conductor layer which is insulated from the silicon island via an insulating film 21 and constitutes one electrode of the capacitor, and 6 is a gate electrode and word line of the transfer transistor 2 as a second conductor. , 21,22,23,24,25,26,
27 is an insulating film. Here, the word line 6 runs right and left in the first drawing. FIG. 1 is a sectional view cut out through a center of a silicon island partitioned by a grid-like groove and a contact portion for connecting the n ⁺ region 7 and the bit line 12, The word line 6 is shown in a sectional view as if it were cut off at this contact portion. However, the word line 6 on the transfer transistor 2 and the word line 6 on the insulating film 23 are connected to each other at a portion other than the contact portion. FIG. 2 is a plan view of this semiconductor memory device, in which each memory cell is a bit line.
The gate electrode 6 that is located in the intersection region of 12 and the word line 6 and is shared by the two transfer transistors is limited to the region 13. As is apparent from the figure, since the region where the gate electrode 6 is formed is limited to the region 13, the overlapping area between the gate electrode 6 and the substrate 1 can be reduced. As a result, the word line capacitance can be reduced more easily than in the prior art, and the speed and power consumption can be reduced. In addition,
In this semiconductor memory device, the thick insulating film 10 is provided at the bottom of the groove, but this is for element isolation, and it is not necessarily thick if element isolation can be completed by other means.
Similarly, the channel-cutting p ⁺ region 11 is provided near the groove bottom, but this is not always necessary. Furthermore, it is not necessary to limit the channel cut region 11 to the vicinity of the groove bottom,
As shown in FIG. 3, the high-concentration p ⁺ region 31 may be arranged over the entire surface of the wafer within a predetermined depth range including the vicinity of the groove bottom.

In FIG. 3, 32 is a p layer, 30 is a p layer 32 and ap ⁺ layer 31.
Is a silicon substrate composed of at least two layers.

In the semiconductor memory device described above, the cell plate 5 forming one electrode of the capacitor and the substrate 1 are insulated. This is because it is necessary to apply a potential different from that of the substrate 1 to the cell plate 5 in order to accumulate sufficient charges in the capacitor 3. However, if at least the vicinity of the substrate surface of the side surface of the groove where the capacitor 3 is formed is n-typed, it is possible to accumulate sufficient charges in the capacitor 3 even if the cell plate 5 has the same potential as the substrate 1. Plate 5
And the substrate 1 can be connected at the groove bottom. By adopting such a structure, a voltage generating circuit for supplying the potential of the cell plate 5 and a contact to the cell plate 5 can be omitted, the area can be saved, and the cell plate 5 becomes the substrate potential, so that the noise is reduced. The reliability of the capacitor insulating film can be improved strongly.

A semiconductor memory device having such a structure is shown in FIG. 4 as a second embodiment. In the figure, an n-type region 9 is provided near the substrate surface on the side surface of the groove where the capacitor 3 is formed, and the cell plate 60 is connected to the substrate 1 at the groove bottom. Here, 40 is a separation p ⁺ region, and 50 and 70 are insulating films. In FIG. 4, the same or corresponding parts as those in FIG. 1 are designated by the same reference numerals. In the illustrated semiconductor memory device, the cell plate 60 and the substrate 1 are connected at the groove bottom, but this is not always necessary. Further, the n-type region of the capacitor 3 is provided near the side surface of the groove. However, as shown in FIG. 5, for example, the n-type region 80 is formed on the entire surface of the cell within a predetermined depth range where the capacitor is formed. The structure may be provided across.

In addition, in FIGS. 4 and 5, p ⁺ for separation is provided near the bottom of the groove.
The area 40 is provided, but this is not always necessary.
Further, similarly to the channel-cutting p ⁺ region 11 described in the first embodiment shown in FIGS. 1 and 2, the separating p ⁺ region 40 is not limited to the vicinity of the groove bottom portion, and a predetermined region including the groove bottom portion vicinity is included. Of course, the structure may be such that the p ⁺ region 31 is arranged over the entire surface of the wafer within the depth range of.

Next, an embodiment of a method of manufacturing a semiconductor memory device having the structure shown in FIG. 1 as the final shape will be described with reference to FIG. First, the first thermal oxide film 81 is formed on the substrate 1, and the n ⁺ layer 7 is formed on the surface of the substrate 1 by the ion implantation method. Next, a silicon nitride film 82 and a silicon oxide film 83 are sequentially deposited on the first thermal oxide film 81 by a known deposition method to form a multilayer film. Then, after a resist is attached to the entire surface, a grid-shaped resist pattern 84 is formed by a lithography process. (FIG. 6A) Using the resist pattern 84 as an etching mask, the multilayer film is removed by reactive ion etching (RIE) to expose the surface of the substrate 1. (FIG. 6B) After removing the resist pattern 84, the substrate 1 is etched by reactive ion etching using the multilayer film as a mask to form a groove. After that, in order to remove the contamination and damage caused by etching, after cleaning the inside of the groove with hydrofluoric nitric acid-based solution,
A thermal oxide film 85 is formed on the inner surface of the groove by a thermal oxidation method, and ap ⁺ region 11 is formed in the vicinity of the groove bottom flat surface by an ion implantation method. (FIG. 6 (c)) Next, a silicon nitride film 86 is deposited in the groove by a known technique, and the silicon nitride film 86 deposited on the flat surface is removed by reactive ion etching to remove only the substrate surface at the bottom of the groove. Expose. (FIG. 6 (d)) Then, thermal oxidation is performed in a mixed atmosphere of hydrogen and oxygen to selectively form the isolation oxide film 10 only on the groove bottom, and then the silicon nitride film 86 and the oxide film 85 are formed. remove. (FIG. 6 (e)) Next, after forming an oxide film 21 on the substrate surface in the groove by a thermal oxidation method,
The polycrystalline silicon 5 to be the cell plate is embedded in the groove by a known technique. (FIG. 6 (f)) After that, the upper end of the polycrystalline silicon 5 is removed by etching by reactive ion etching so that the upper end thereof is located at a predetermined position in the groove, and then the multilayer films 83, 82, 81 on the main surface of the substrate are removed. .
At this time, the portion of the oxide film 21 on the inner surface of the groove above the upper end of the polycrystalline silicon 5 is removed. (FIG. 6 (g)) Next, after an oxide film 22 is formed on the exposed portion of the surface of the silicon substrate 1 by a thermal oxidation method, a silicon oxide film 23 is formed by a known method and embedded in the groove. Then, it is etched back by reactive ion etching to remove the silicon oxide films 23 and 22 on the main surface of the substrate, and the main surface of the substrate is made substantially flat. (FIG. 6 (h)) After forming the oxide film 24 on the main surface of the substrate, a resist is attached to the entire surface, and a transfer transistor window opening resist pattern 87 is formed by a lithography process. (FIG. 6 (i)) Next, using the resist pattern 87 as a mask, the oxide film 23 in the opened region is removed. At this time, the oxide films 24 and 22 in this window opening region are also removed. After removing the resist pattern 87, an oxide film 25 is formed by a thermal oxidation method or the like, and then polycrystalline silicon 6 is deposited on the main surface of the substrate including the window opening region by a known method. (FIG. 6 (j)) After that, a resist is attached, patterning as a word line is performed by lithography, and processing is performed by dry etching using this resist pattern as a mask. Next, after removing the resist pattern, a silicon oxide film 26 is formed by a known method, a resist is attached again, and a pattern 88 as a bit line contact hole is formed by lithography, and using this as a mask, reactive ions are formed. By removing the oxide film 26, the polycrystalline silicon 6 and the oxide film 24 by etching, the substrate 1 of the contact portion is removed.
Expose the surface. (FIG. 6 (k)) Next, after removing the resist pattern 88, an oxide film 27 is formed on the surface of the polycrystalline silicon 6 on the side surface of the bit line contact hole by thermal oxidation. At this time, since an oxide film is also formed on the surface of the substrate 1 which is the bit line contact portion, the oxide film is removed by reactive ion etching to expose the surface of the substrate 1 and then aluminum 12 for the bit line is attached. Then, a bit line is formed through a lithography process and an etching process to obtain a final shape. (FIG. 6 (l)) In the above example, the isolation oxide film 10 was formed by the thermal oxidation method (FIG. 6 (e)), but the oxide film may be formed by the CVD method or the like. In this case, after the ion implantation for forming the channel cut region 11 (corresponding to FIG. 6 (c)), the silicon oxide film is buried in the trench by a known method, and then the silicon oxide film is removed to a predetermined area by reactive ion etching. It should be removed to make it thick. After that, the polycrystalline silicon 5 may be formed, and the same steps as those in the first embodiment (FIG. 6 (f) and thereafter) may be performed.

Incidentally, as described above in the embodiment of the semiconductor memory device,
The isolation oxide film does not necessarily have to be thick, and in that case, a series of steps for forming the oxide film 10 (FIG. 6 (d),
(Corresponding to (e)) can be omitted.

Furthermore, in the embodiment, the high-concentration region 11 for channel cutting is formed in the vicinity of the groove bottom by the ion implantation method, but it is not necessary to limit to the ion implantation method. Further, the formation position does not have to be limited to the vicinity of the groove bottom, and the high concentration region may be formed within the predetermined depth range including the groove bottom over the entire surface of the wafer. In this case, for example, as a substrate
A wafer in which a p layer is laminated on the p ⁺ layer by an epitaxial method may be used, and the groove may be formed so that the bottom of the groove reaches the underlying p ⁺ layer. The high-concentration region may be omitted, and in this case, the high-concentration region forming ion implantation step (FIG. 6C) may be omitted.

As described in the second embodiment of the semiconductor memory device, the n-type region 9 may be provided near the side surface of the groove in which the capacitor 3 is formed. The manufacturing method of the embodiment having FIG. 4 as the final process drawing will be described below with reference to FIG. Similar to the first embodiment of the semiconductor memory device shown in FIG. 1, a thermal oxide film is formed on the substrate 1.
After forming 81, the n ⁺ layer 7 is formed, and then the silicon nitride film 8 is formed.
2. A silicon oxide film 83 is deposited, a resist is attached, and a lithography process is performed to form a grid-shaped resist pattern 84. Using this as a mask, the multilayer films 83, 82 and 81 are etched to expose the surface of the substrate 1. (FIG. 7A) After removing the resist pattern 84, a groove having a predetermined depth is formed by using the multilayer films 83, 82 and 81 as a mask, and after cleaning the inside of the groove with a hydrofluoric / nitric acid solution, a known method is used. Thereby, a silicon oxide film 91 is formed. (FIG. 7 (b)) Next, the oxide film 91 deposited on the flat surface is removed by reactive ion etching to expose the substrate surface at the bottom of the groove. At this time, the oxide film 91 remains on the side surface of the groove. (FIG. 7 (c)) Using the oxide film 91 and the multilayer films 83, 82, 81 as a mask, a groove is formed again by reactive ion etching, and the inside of the groove is washed with a hydrofluoric / nitric acid solution. (FIG. 7 (d)) Next, polycrystalline silicon 92 to which phosphorus is added is embedded in the groove, and this is used as an impurity diffusion source to thermally diffuse the substrate 1 in the groove.
An n-type region 9 is formed near the exposed portion of the surface. At this time, the oxide film 91 functions as a diffusion mask, and prevents the region other than the capacitor portion on the side surface of the groove from being n-typed. (FIG. 7 (e)) Next, after removing the phosphorus-doped polycrystalline silicon 92, an oxide film is formed.
91 and the multilayer films 83, 82 and 81 are used as a mask to form a groove again by reactive ion etching so that the groove bottom is located at a predetermined position below the n-type region 9, and then the inside of the groove is washed with a hydrofluoric nitric acid-based solution. To do. (FIG. 7 (f)) Next, after forming the thermal oxide film 50, a p ⁺ region 40 is formed in the vicinity of the groove bottom by ion implantation, and the oxide film 50 on the groove bottom flat surface is removed by reactive ion etching. , Groove bottom only substrate 1
Expose the surface. (FIG. 7 (g)) Next, after the polycrystalline silicon 60 is embedded in the groove, the polycrystalline silicon 60 is removed by reactive ion etching so that the upper end of the polycrystalline silicon 60 is at a predetermined position, and then the silicon oxide film 83 is removed. remove. At this time, the oxide film 91 is also removed. Next, after removing the silicon nitride film 82 and the oxide film 81, an oxide film 70 is formed by thermal oxidation. (FIG. 7 (h)) After that, according to the same steps as those of the first embodiment (corresponding to FIG. 6 (g) and thereafter), the silicon oxide film 23 is embedded in the groove, and then reactive ion etching is performed. By etching back to remove the oxide films 23 and 70 on the main surface of the substrate 1 to make the main surface substantially flat, and then form a thermal oxide film 24 on the main surface of the same substrate, and through a resist adhesion and lithography process, a resist pattern Form 93. (FIG. 7 (l)) The silicon oxide film 23 and the thermal oxide film 70 in the region opened by using the resist pattern 93 as a mask are removed, but at this time, the oxide film 24 in the region is also removed. Resist pattern 93
After removing the thermal oxide film 25, the polycrystalline silicon 6 is formed on the main surface of the substrate 1 including the window opening region. (7th
(J) Next, after processing the polycrystalline silicon 6 as a word line by dry etching through resist adhesion and a lithography process, the resist is removed and the silicon oxide film is removed.
26 is deposited, and a resist pattern 94 as a contact hole is formed again through the lithography process. Using this as a mask, the silicon oxide film 26, the polycrystalline silicon 6 and the oxide film 24 are removed to expose the surface of the substrate 1 in the contact portion. Let (FIG. 7 (k)) The resist pattern 94 is removed, and a thermal oxide film 27 is formed on the surface of the polycrystalline silicon 6 on the sidewall of the contact hole by thermal oxidation. At this time, since an oxide film is also formed on the surface of the substrate 1 in the contact portion, the oxide film is removed by reactive ion etching, the surface of the substrate 1 is exposed again, and then the aluminum 12 for bit line is attached and the lithography is performed. A bit line is formed through a process and an etching process to obtain a final shape. (FIG. 7 (l)) In the second embodiment of the manufacturing method described above, n
Although phosphorus-doped polycrystalline silicon 92 is used as an impurity diffusion source for forming the shaped region 9, other phosphorus-doped glass or a gas such as POCl ₃ may be used. Alternatively, the n-type region 9 may be formed by an ion implantation method. Changes in the process in this case will be described with reference to FIG. First 7th
Similar to the embodiment shown in the figure, after forming the lattice-shaped grooves, the side surfaces of the grooves are covered with the silicon oxide film 91 and the surface of the substrate 1 at the flat portion of the groove bottom is exposed (corresponding to FIG. 7C). (FIG. 8A) Next, after forming the thermal oxide film 95, the multilayer films 81, 82, 83 and the oxide film are formed.
Using 91 as a mask, an n-type region 9 is formed in the vicinity of the groove bottom by ion implantation. (FIG. 8B) Next, after removing the oxide film 95 by reactive ion etching, the oxide film 91 and the multilayer films 81, 82, and 83 are used as masks to set the bottom of the groove to a predetermined level below the n-type region 9. The groove is formed again so as to be positioned, and then the inside of the groove is washed with a hydrofluoric / nitric acid solution.
(FIG. 8 (c)) Thereafter, according to the same process as in the second embodiment of FIG. 7, after the inner surface of the groove is oxidized, the groove bottom portion near the substrate surface is formed by ion implantation.
The steps after the formation of the p ⁺ region 40 (corresponding to FIG. 7 (g)) are advanced to obtain the final shape shown in FIG. 8 (d).

In the second embodiment described above, in forming the n-type region, the multilayer films 81, 82, 83 and the silicon oxide film 91 are used as a mask to prevent the parts other than the capacitor part from being n-typed. However, for example, before forming the multilayer films 82, 83, etc., ion implantation is performed over the entire surface of the cell region, and as shown in FIG. 5, n-type is formed within a predetermined depth range where the capacitor 3 is formed. If the region 80 is formed, the above-mentioned mask is not necessary, and it is possible to use the same process as that of the first embodiment of the method for manufacturing the semiconductor memory device.

In addition, in the second embodiment, the cell plate 60 and the substrate 1 are connected at the groove bottom, but it is not always necessary to make the connection, and the reactivity performed after the formation of the p ⁺ region 40 near the groove bottom is performed. The step of removing the oxide film 50 on the flat surface of the groove bottom portion by ion etching (FIG. 7 (g)) can be omitted.

In addition, the formation of the p ⁺ region 40 near the bottom of the groove is limited to the ion implantation method just as in the case of forming the high concentration region for channel cutting described in the first embodiment of the method for manufacturing a semiconductor memory device. No need. Further, a method of using an epitaxial wafer in which a p layer is laminated on ap ⁺ layer as a silicon substrate and forming a groove so that the groove bottom reaches the underlying p ⁺ layer is of course applicable. In addition, p ⁺ region 40
Can be omitted, and in this case, the ion implantation step for forming the p ⁺ region 40 (FIG. 7 (g)) can be omitted.

The manufacturing methods described above are examples of the present invention, and the present invention is not limited thereto. For example,
As the material of the cell plate and the gate electrode of the transfer transistor and the word line, other crystalline silicon was used as a material that can be formed by the CVD method or the like and can be surface-oxidized. Other metals or their silicides may be used. Similarly, the bit line is not limited to aluminum, and another metal, silicide, or the like can be used. Further, the various oxide films used as the insulating film and the like are not limited to these. For example, other insulating films such as PSG, BPSG, and silicon nitride film may be used, and the formation method thereof is also limited. is not. In addition, in each of the embodiments, a p-type silicon substrate is used as the substrate 1,
Needless to say, when a substrate having opposite polarities is used, the polarities of the regions are also reversed accordingly.

〔The invention's effect〕

As described above, according to the present invention, the lattice-shaped grooves formed on the main surface of the semiconductor substrate and the first insulating film formed on the side surface of the groove to the middle depth of the groove are formed. A conductor layer, a second conductor layer formed on a predetermined region of the first conductor layer formed in a grid pattern with a second insulating film interposed therebetween, and formed on a region other than the predetermined region. By providing the insulating film, the transfer transistor region can be limited, the capacitance between the gate electrode of the transfer transistor and the substrate, that is, the word line load capacitance can be reduced, and high speed and power saving can be achieved. is there.

Further, in the manufacturing method, a step of forming a lattice-shaped groove on the main surface of the semiconductor substrate, a step of forming a first insulating film on at least a side surface of the groove, and a first conductor up to a predetermined depth in the groove. And a second step on the first conductor.
Forming an insulating film, forming a third insulating film in a region other than the partial region where the transistor is formed on the second insulating film, and forming a third insulating film in the partial region on the second insulating film. By including the step of forming the second conductor, the capacitor can be formed in a self-aligned manner, the alignment margin with the groove is not required, and the alignment margin for forming the transfer transistor region is provided for forming the bit line contact. It is possible to increase the density of the memory cells because it can be included in the alignment margin.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a plan view thereof, FIG. 3 is a sectional view showing a modification of the first embodiment, and FIG. Is a sectional view showing a second embodiment, FIG. 5 is a sectional view showing a modification thereof, FIG. 6 is a sectional view showing an embodiment of a method for manufacturing the semiconductor memory device of FIG. 1, and FIG. 2 is a sectional view showing an embodiment of a method for manufacturing the semiconductor memory device of FIG. 2, FIG. 8 is a sectional view showing a modification thereof, FIG. 9 is a sectional view showing an example of a conventional semiconductor memory device,
FIG. 10 is a plan view thereof. 1 ... Substrate, 2 ... Transfer transistor, 3 ...
Capacitor, 4 ... Isolation area, 5,60 ... Cell plate,
6 ... Gate electrode and word line, 7 ... n ⁺ region, 9,80 ...
n-type region, 10 ... Isolation oxide film, 11,40 ... p ⁺ region, 12
... bit line, 13 ... area, 21,22,23,24,25,26,27,50,
70 ... Insulating film, 30 ... Silicon substrate, 31 ... P ⁺ layer, 32 ...
... p layer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazushige Minegishi 3-1, Morinosato Wakamiya, Atsugi City, Kanagawa Prefecture At Nippon Telegraph and Telephone Corporation Atsugi Telecommunications Research Laboratories (72) Inventor Takashi Morie, 3-1, Morinosato Wakamiya, Atsugi City, Kanagawa Japan (56) References JP 61-174670 (JP, A) JP 61-179571 (JP, A) JP 61-198772 (JP, A)

Claims (2)

[Claims] 1. A semiconductor memory device comprising a single transistor and a single capacitor, wherein a lattice-shaped groove formed on a main surface of a semiconductor substrate and a first insulating film on a side surface of the groove are interposed. A first conductor layer formed to a depth in the middle of the groove, and a second conductor layer formed on a predetermined region of the first conductor layer formed in a grid pattern with a second insulating film interposed therebetween. Of the conductor layer and a third insulating film formed in a region other than the predetermined region, and a capacitor is provided in a region where the first conductor layer is formed on the side surface of the island-shaped cell partitioned by the groove. And a transistor is formed on the side surface of the groove in the region where the second conductor layer is formed. 2. A method of manufacturing a semiconductor device comprising a single transistor and a single capacitor, wherein a step of forming a grid-like groove on the main surface of a semiconductor substrate and a first groove on at least a side surface of the groove. A step of forming an insulating film, and a step of forming a capacitor-forming first conductor up to an intermediate depth in the groove on the side surface of the island-shaped cell partitioned by the groove, A step of forming a second insulating film on the first conductor formed in a grid pattern, and a step of forming a third insulating film on a portion of the second insulating film other than a partial region where a transistor is formed. And a step of forming a second conductor in the partial region on the second insulating film.