JPH0793372B2 - Semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor memory device having a memory mole structure of 1 transistor / 1 capacitor.

[Technical Background of the Invention and Problems Thereof] Conventionally, as a memory device formed on a semiconductor substrate,
A MOS dynamic RAM (dRAM) is known in which a memory cell is composed of a MOS transistor and one MOS capacitor. In this dRAM, information is stored depending on whether or not electric charge is accumulated in the MOS capacitor, and information is read out by discharging the electric charge of the MOS capacitor to the bit line through the MOS transistor and detecting the potential change. Done by. Due to recent advances in semiconductor technology, particularly advances in microfabrication technology, increasing the capacity of dRAM is rapidly progressing.

The biggest problem in increasing the capacity of the dRAM is how to keep the capacity of the MOS capacitor small while keeping the memory cell area small. The magnitude of the potential change at the time of reading information from the dRAM is determined by the amount of charge stored in the MOS capacitor, and the minimum required amount of charge is determined by considering the operating margin and the margin for noise such as α-ray incidence. Since the amount of accumulated charge is determined by the capacitance of the MOS capacitor and the applied voltage, and the applied voltage is determined by the power supply voltage, it is necessary to secure the capacitance of the MOS capacitor above a certain value.

In order to increase the capacity of the MOS capacitor, it is necessary to reduce the film thickness of the gate insulating film used, increase the dielectric constant, or increase the area. However, reducing the insulating film thickness has a limit in reliability.
Increasing the dielectric constant can be considered, for example, by using a nitride film (Si ₃ N ₄ film) instead of the oxide film (SiO ₂ film), but this is also not practical because it has a problem mainly in reliability. Then, in order to secure the required capacitance, it is necessary to secure the area of the MOS capacitor above a certain value, which reduces the area of the memory cell and achieves high density and large capacity of the dRAM. It is a big obstacle.

As a method of increasing the capacity of the MOS capacitor without increasing the occupied area of the memory cell, a lattice-stripe-shaped groove is provided in the semiconductor substrate, and the area surrounded by this groove is defined as one memory cell area, and the bottom of the groove is As the isolation region, one in which a MOS capacitor is formed on the side surface of the groove has been proposed (JP-A-59-72161). Its structure is shown in FIG. Reference numeral 61 denotes a P-type Si substrate in which a lattice-striped groove 62 is formed, and a capacitor electrode 64 is embedded in the groove 62 on a sidewall of the groove via a capacitor insulating film 63, and an island region surrounded by the groove is formed. A MOS capacitor is formed so as to surround the. Groove 6
A p ⁺ type layer 65 for element isolation is formed on the bottom of 2. M
The OS transistor is configured by forming a gate electrode 67 on a flat portion of the substrate in a region surrounded by the groove 62 with a gate insulating film 66 interposed. 68 is an n ⁺ type layer that serves as a drain, 69 is an SiO ₂ film, and 70 is a metal wiring that serves as a bit line.

In this structure, since the side surfaces of all the grooves are used as MOS capacitors, there is an advantage that a large capacitance can be easily obtained. On the other hand, the island region surrounded by the groove corresponds to one memory cell region, and the contact hole is formed in the center of the island region, and the gate electrode of the MOS transistor is formed around the contact hole. The area is large, and there is a drawback that the occupied area of the memory cell as a whole cannot be sufficiently reduced.

Further, since only one memory cell can be formed in one island region, there is a problem that the degree of integration cannot be increased.

[Object of the Invention]

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor memory device in which an occupied area of a memory cell is reduced and a sufficient capacitor capacity is realized.

[Outline of Invention]

According to the present invention, a plurality of island-shaped semiconductor layers separated by lattice-shaped grooves are formed on a substrate, and a memory cell having a one-transistor / one-capacitor structure is formed in each island-shaped semiconductor layer. In this case, the MOS capacitor is formed by using the side wall of the groove with the capacitor electrode buried up to the middle of the groove, and the MOS transistor is also formed by using the side wall of the groove with the gate electrode embedded on the capacitor electrode. It is formed. Therefore, only the drain region of the MOS transistor is provided on the upper surface of the island-shaped semiconductor layer surrounded by the groove.

Further, an insulating film is buried in the side walls of the island-shaped semiconductor layer which face each other, and the capacitor electrode and the gate electrode are buried in the other trenches. Therefore, a 2-cell / island configuration is achieved.

〔The invention's effect〕

According to the present invention, not only the MOS capacitor but also the MOS transistor is formed by utilizing the side wall of the groove, so that the memory cell occupying area can be made smaller than the conventional one, and the capacitor capacity is smaller than that of the island-shaped semiconductor layer. A sufficiently large value can be secured by using the side surface that surrounds. Therefore, a highly integrated dRAM can be realized.

In addition, since a 2 cell / island configuration is possible, high integration is possible.

Further, according to the present invention, since the capacitor electrode and the gate electrode of the transistor are both embedded in the lattice stripe groove,
It is possible to make the substrate surface flat after these electrodes are formed, which facilitates the formation of fine patterns in the subsequent metal wiring process.This contributes to higher integration and reliability of dRAM. Contribute.

Example of Invention

 Examples of the present invention will be described below.

FIG. 1 shows a dRAM structure of one embodiment, showing a plan view, and FIGS. 2 (a) to (i) are cross-sectional views of the manufacturing process at the position AA '.

That is, the p ⁻ Si layer 12 is provided on the p ⁺ type si substrate 11, and a trench reaching the p ⁺ Si substrate 11 is dug in the field region to form Si islands in an array. In the Si island, the SiO ₂ film 15 is embedded in the groove in one direction, the capacitor electrode 19 is embedded in the lower portion of the remaining groove, and the gate electrode 22 is provided in the upper portion of the groove. The gate electrode 22 is continuously provided in each cell to form a word line. A drain 23 is provided above the Si island, and an Al 25 that is a bit line is arranged orthogonal to the word line.

Therefore, two dRAM cells are arranged on the Si island with the SiO ₂ film 15 interposed therebetween by utilizing the side walls.

At the time of manufacture, a low impurity concentration p ⁻ type Si layer 12 is epitaxially grown on a high impurity concentration p ⁺ type Si substrate 11, and a silicon oxide film 13 is formed in a portion where an island-shaped semiconductor region is formed,
This is patterned using the photoresist 14 as a mask (FIG. 2A).

Next, using these as a mask, the p ⁻ -type Si layer 12 is etched by reactive ion etching (RIE) to form lattice-striped grooves on the Si substrate 11.
Reach and form. Then, the CVD SiO ₂ film 15 is flatly embedded in this groove (FIG. 2B).

Next, a photoresist mask 16 is provided in a stripe shape across a plurality of Si islands, and this is used as a mask to form a CVD SiO ₂ film.
15 is etched by RIE. (Fig. 2c). As a result, the trenches between the Si islands are filled with the CVD SiO ₂ film in the word line arrangement direction.

After that, a PSG film (not shown) is CVD-deposited on the entire surface, and a heat treatment is performed to diffuse phosphorus to the side wall of the Si island where the oxide film 15 has been removed to form an n ⁻ -type layer 17. The film is removed to form a thermal oxide film of about 100 Å as the capacitor insulating film 18 (Fig. 2d).

Next, the first-layer polycrystalline silicon film 19 is deposited on the entire surface.
At this time, the surface of the polycrystalline silicon film 19 is flattened as shown (FIG. 2e). Then, the polycrystalline silicon film 19 is entirely etched and left at the bottom of the groove to form a capacitor electrode. The capacitor electrode 19 is formed in a state where it is embedded in the groove halfway.

After that, the capacitor insulating film 18 is removed, and a p ^- type layer 20 serving as a channel region of the transistor is formed on the sidewall and the upper surface by a BSG film (not shown) or the like (FIG. 2f). At this time, the n ⁻ -type layer 16 serving as the substrate-side electrode of the capacitor recedes due to diffusion when the p ⁻ -type layer 20 is formed. In order to compensate for this, it is desirable that the thickness of the capacitor electrode is selected to be slightly thicker by drawing in this receding amount in advance and the surface of the capacitor electrode 19 is slightly etched after the p ⁻ type layer 20 is formed.

After that, a thermal oxide film having a thickness of, for example, about 200Å is formed on the surface of each p ⁻ type layer as the gate insulating film 21, and then the second-layer polycrystalline silicon film used as the gate electrode of the MOS transistor.
22 is deposited by CVD (Fig. 2g). As is clear from the figure, the surface of the second-layer polycrystalline silicon film 22 is not flattened as in the case of the first-layer polycrystalline silicon film. Then, the polycrystalline silicon film 22 is entirely etched by anisotropic etching such as RIE to form a gate electrode 23 while leaving the sidewall of the Si island and the sidewall of the buried oxide film 15 self-aligned. Thus, the gate electrodes 23 connected in the vertical direction form a word line. After that, for example, arsenic is ion-implanted to form the n ⁺
A multilayer 23 is formed (Fig. 2h).

Finally, the CVD oxide film 24 is formed on the entire surface, and the drain of the memory cell in the lateral direction is connected to this, and the Al wiring that becomes the bit line
Form 25 (Fig. 2i).

Thus, the gate electrode is arranged on the side wall of the Si island, and two memory cells are arranged on one Si island to provide a dRAM cell having a large capacitor capacitance and a high density.

FIG. 3 shows the extraction of the word line, which is taken along the line B- in FIG.
The B'section is shown.

The line indicated by (I) in FIG. 1 indicates the boundary between the peripheral circuit region and the memory cell array region. In this example, the word lines are twisted 90 ° and led out on the peripheral p ⁻ -type flat Si layer 12. This can be formed as follows.
That is, as shown in the upper part of FIG.
After depositing the second layer 22, the second-layer polycrystalline silicon film 22 deposited on the step of the region shown as (II) in FIG. 1 is removed by wet etching using a resist mask (not shown). . Next, a new resist mask 31 is used to cover the second-layer polycrystalline silicon film 22 (III) at the lead-out portion (FIG. 3a), and then the second-layer polycrystalline silicon film 22 by RIE described in FIG. 2 (h). The entire surface of is etched. As a result, the word line is twisted 90 ° and extended to the peripheral portion as shown in FIG. 3 (b). If desired, contact may be made with Al on this extension.

In the above derived example, the second-layer polycrystalline silicon film 22 in the portion (II) of FIG. 1 was removed using the photoresist mask. However, instead of such selective removal, the following method is also possible.

That is, prior to the step of FIG. 2A, a V groove reaching the Si substrate 11 is formed by taper etching in the p ⁻ type Si layer at the boundary between the peripheral circuit of FIG. 1 and the memory cell array region. . As a result, for example, in the step portion of the p ⁻ type Si layer 12 at the boundary I,
Have a 45 ° inclination. By doing so, when the resist pattern 31 is placed on the second-layer polycrystalline silicon film 22 in the step of FIG. 3A and the entire surface is etched by RIE, adjacent word lines are automatically separated.

In the above embodiments, the Si islands have a rectangular plane pattern rotated by 45 °. However, as shown in FIG. 4 (a), it may have a shape before rotation, a circle as shown in FIG. 4 (b), or an elliptical oval pattern as shown in FIG. 4 (c).

These shapes are based on the 1cell / is previously proposed by the present inventor.
It can be applied to a land type memory cell (Japanese Patent Application No. 60-80619).

FIG. 5 shows an example in which the circular pattern of FIG. 4 (b) is applied to such an example, (a) is a plan view, (b),
(C) shows AA 'and BB' cross sections, respectively. The oxide film 15 and the resist mask 16 for patterning the oxide film 15 are not provided, and the subsequent process is performed in the same process as that shown in FIGS.

That is, the Si island is surrounded by the laminated structure of the capacitor electrode and the gate electrode all around, and has a 1 cell / island structure, and the second layer polycrystalline silicon film 22 is formed in the step of FIG. A continuous word line is formed by growing the groove to be thicker than 1/2 of the groove width between Si islands in the word line formation direction.

By the way, in the above description, the pair of bit lines (BL ₁ , BL ' ₁ ) and (BL ₂ , BL' ₂ ) connected to the sense amplifier are connected to the Si islands every other pair, and the folded bit line structure is formed. However, the open bit line configuration may be used.
Further, the isolation between the elements was performed by the p ⁺ type substrate 11, but without using such an epitaxially grown wafer, a p ⁻ type Si substrate was used, and the field insulating film was formed to a constant thickness at the groove bottom between the elements. It is also possible to adopt a method of embedding or forming a p ⁺ layer below it.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2 is a process sectional view thereof, FIG. 3 is a sectional view of a lead-out portion, FIG. 4 is a plan view showing an example of a Si island, and FIG. FIG. 6 is a sectional view showing a conventional example.

Claims (1)

[Claims] 1. A groove is provided in a field region of a semiconductor substrate,
One conductivity type island-shaped semiconductor region formed surrounded by the groove,
An insulating film buried in the groove of the first facing sidewall portion of the island-shaped semiconductor region, and a capacitor electrode and a gate electrode sequentially buried in the groove of the second facing sidewall portion of the semiconductor island region. And a reverse conductivity type region provided on the upper surface of the island-shaped semiconductor region, wherein each of the island-shaped semiconductor regions is formed with two memory cells separated by the insulating film. .