JPH0793411B2 - Charge amplification semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device for charge amplification, and is used, for example, in a semiconductor device monolithically integrated with a photodiode or a junction type charge transfer element.

[Conventional technology]

A charge amplification circuit as shown in FIG. 4 is used as an output amplification section of a photodiode or as an output section of a junction type charge transfer element. As shown in the figure, the input charge is input to the gate Q ₁ of the p-channel junction type FET (p-FET) Q ₁ , where it is voltage-converted and amplified. In addition, an n-channel junction type FET is provided at the node T connected to the gate G ₁ of the p-FET Q _1.
The drain D _{2 of} (n-FET) Q ₂ is connected, and this n
Periodically pulse is applied to the gate G ₂ of -FETQ _2.
Therefore, when the n-FET Q ₂ is ON, the input charge at the node T is reset.

The p-FET Q ₁ for charge amplification is realized on a semiconductor substrate as shown in FIG. 5, for example. The figure (a) is the top view, and the figure (b) is the sectional view on the AA line. As shown,
An n-type island region 12 surrounded by a p-type isolation region 11 is formed on the p-type substrate 10. In the n-type island region 12, a p-type source region 21, a p-type drain region 31 and an n-type gate region are formed.
41 is formed. directly below the n-type gate region 41 n ⁺ -type buried layer 60 is formed, the n ⁺ -type buried layer 60 is connected to the n ⁺ -type region 61 for ohmic contact. And p
The mold region 51 functions as a channel.

On the other hand, the reset n-FET Q ₂ is realized on a semiconductor substrate as shown in FIG. 6, for example. The figure (a) is the top view, and the figure (b) is the sectional view on the AA line. As shown, n-type island region surrounded by p-type isolation region 11
12 includes n ⁺ type source region 22, n ⁺ type drain region 32 and p
A mold gate region 42 is formed. The n-type island region 12 immediately below the p-type gate region 42 functions as a channel.

Such a charge amplification circuit is used in combination with a junction type charge transfer device (J-CCD) as shown in FIG. 7, for example.
That is, in the n-type island region 12, p-type regions 91 and 92 are formed in addition to the n ⁺ -type source region 22, the n ⁺ -type drain region 32, and the p-type gate region 42 that form the n-FET Q ₂ . . The p-type region 91 functions as the output gate OG of the junction type charge transfer device,
The p-type region 92 functions as a transfer gate and is supplied with the transfer clock φ. The connection between the source S ₂ of the gate G ₁ and n-FETG ₂ of p-FETs Q ₁ is realized by a wiring 93 due to Al.

[Problems to be Solved by the Invention]

However, such a conventional technique has a problem that the floating diffusion capacitance C _fd shown by the dotted line in FIG. 4 increases. This will be described with reference to FIG. Of the parasitic capacitance shown by the dotted line in the figure, C _L is the Al wiring
93, C _{1 to} C ₃ are generated in the n-type island region 12 where the n-FET Q ₂ is formed, and C _gs and C _gd are p−
That between the gate and source of the FETs Q ₁ and occurs in between the gate and the drain, C _sub is intended to occur between the p-FETs Q ₁ and p-type substrate 10.

When the parasitic capacitance C _{fd in} FIG. 4 increases due to the generation of these parasitic capacitances, the charge-voltage conversion gain of the charge amplification circuit becomes low, and the KTC noise accompanying the periodic reset also becomes large. Specifically, in the configuration of FIG. 7, n
-Change in signal charge of n ⁺ type source region 22 of FETQ ₂ (Δq)
On the other hand, since the p-FET Q _{1 functions} as a charge amplification element, the voltage change ΔV of the output V _out is ΔV = K · Δq / C _T. Then, since this K is a constant, n-FETQ ₂
The total capacitance C _T connected to the n ⁺ type source region 22 is the parasitic capacitance C _L , C
_{The more subs} increase, the lower the gain.

Therefore, it is an object of the present invention to provide a charge amplification semiconductor device that can simultaneously achieve an increase in charge-voltage conversion gain and an improvement in S / N ratio.

[Means for Solving the Problems]

A semiconductor device for charge amplification according to the present invention includes a p-channel junction type FET for charge amplification that converts input charges into a voltage, and an n-channel junction type FET for resetting that resets input charges.
Are formed in the same island region surrounded by the isolation region. Here, a photodiode for supplying an input charge or a junction type charge transfer element may be monolithically integrated in the island region.

[Action]

According to the present invention, since the p-channel junction type FET for charge amplification and the n-channel junction type FET for reset are formed in the same island region, it is possible to eliminate the parasitic capacitance due to the wiring, and to reduce the substrate and the gate. The parasitic capacitance between the regions can also be reduced.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows the main part of the charge amplification device according to the first embodiment,
The figure (a) is a top view and the figure (b) is the sectional view on the AA line. As shown in the figure, the single n-type island region 12 surrounded by the p-type isolation region 11 has a p-FET Q for charge amplification.
₁ p-type source region 21, p-type drain region 31, n-type gate region 41, p-type region 51 as a channel, and n ⁺ -type buried layer 60 are formed, and an n-FET Q ₂ structure for resetting is formed. An n ⁺ type drain region 32 and a p type gate region 42 are formed. Therefore, the gate G ₁ and n−F of p-FET Q ₁
Since wiring such as Al connecting the source S _{2 of} ETQ ₂ is not required,
Is totally gone wiring capacitance indicated by C _L in FIG. Also,
Since the p-FETQ ₁ and the n-FETQ ₂ are formed in the same n-type island region 12, the parasitic capacitance (C ₁ and C _{sub in} FIG. 8) with the p-type substrate 10 becomes the same. , The total capacity value can be reduced. Therefore, the capacitance shown as C _{fd in} FIG. 4 is reduced, so that a high charge-voltage conversion gain and an improvement in S / N ratio can be achieved at the same time.

FIG. 2 shows an output part of the junction type charge transfer device according to the second embodiment. FIG. 2 (a) is a plan view, FIG. 2 (b) is a sectional view taken along line A ₁ -A ₁ , FIG. 2 (c). FIG. 3 is a sectional view taken along line A ₂ -A ₂ . Also in this embodiment, p-FET Q ₁ for charge amplification and n-F for resetting
ETQ ₂ is formed in the same n-type island region 12. And
In this n-type island region 12, a p-type region that functions as an output gate OG
91 and a p-type region 92 to which the transfer clock φ is applied are also formed. Therefore, similarly to the first embodiment, it is possible to increase the gain and improve the S / N ratio by reducing the capacitance.

FIGS. 3 (a) and 3 (b) are plan views of the junction type charge transfer device according to the second embodiment in which a part of the output part is changed.
In the structure of FIG. (A) is a second view, which has changed the direction of the p-FETs Q ₁ by 90 °, FIG. (B) is of p-FETs Q ₁ p
The type drain region 31 is common to the p-type isolation region 11. Also in these devices, the p-FET Q ₁ for charge amplification and the n-FET Q ₂ for reset have the same type island region.
Since it is formed of 12, the parasitic capacitance can be reduced.

〔The invention's effect〕

As described above in detail, in the present invention, p for charge amplification is used.
Channel junction type FET and n channel junction type FET for reset
Since formed in the same island region, it is possible to eliminate the accompanying parasitic capacitance (C _L) to the wiring, and a parasitic capacitance between the substrate and the gate region (C _1, C _sub) can be reduced. Therefore, it is possible to provide a charge amplification semiconductor device that can simultaneously achieve an increase in charge-voltage conversion gain and an improvement in S / N.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a charge amplification device according to a first embodiment of the present invention, FIG. 2 is a diagram showing a configuration of an output part of a junction type charge transfer device according to a second embodiment, and FIG. FIG. 4 is a diagram showing a partially modified configuration of the second embodiment, FIG. 4 is a circuit diagram of a general charge amplification circuit, and FIG. 5 is a configuration of a p-channel junction type FET for charge amplification. FIG. 6 is a diagram showing the configuration of an n-channel junction type FET for resetting, FIG. 7 is a diagram showing the configuration of the output part of a conventional junction type charge transfer device, and FIG. 8 is a parasitic capacitance. FIG. Q ₁ ... p-channel junction FET (p-FET) for charge amplification, Q ₂
... Reset n-channel junction FET (n-FET), 10 ...
… P-type substrate, 11 …… P-type isolation area, 12 ……
n-type island region, 21 ... p-type source region, 22 ... n ⁺ type source region, 31 ... p-type drain region, 32 ... n ⁺ type drain region, 41 ... n-type gate region, 51 ... p-type channel region,
60 …… n ⁺ type buried layer, 61 …… n type channel region, 93 …… wiring.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/339 21/8232 27/146 29/762 29/812 7514-4M H01L 27/06 F 7376 -4M 27/14 A 9056 -4M 29/76 301 C (56) Reference JP 62-296467 (JP, A) JP 60-247956 (JP, A) JP 61-267358 (JP, A) JP-A-60-223161 (JP, A)

Claims (3)

[Claims] 1. A p-channel junction type FET for charge amplification, which is formed on the same substrate, for converting an input charge into a voltage, and an n-channel junction type FET for resetting the input charge.
A charge amplification semiconductor device including a FET, comprising: the p-channel junction type FET and the n-channel junction type FET
Is formed in the same island region surrounded by an isolation region made of a material of the substrate or a material having substantially the same conductivity as the material of the substrate. 2. A semiconductor device for charge amplification according to claim 1, wherein photodiodes for supplying the input charges are monolithically integrated in the island region. 3. The charge amplifying semiconductor device according to claim 1, wherein junction type charge transfer elements for supplying the input charges are monolithically integrated in the island regions.