JPH0793431B2 - Method for manufacturing substrate of vertical conductivity modulation type MOSFET - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a vertical conductivity modulation type MOSFET (hereinafter referred to as an IGBT).
(Hereinafter abbreviated as ").

[Conventional technology]

Conventionally, as a power switching element, a vertical MOSFET and an IGBT in which a region of a conductivity type opposite to that of the source is added to the drain side are known. The IGBT is an element that combines the high-speed switching characteristics of the vertical MOSFET and the low impedance of a bipolar transistor. Has been attracting attention.

Fig. 6 shows a partial cross-sectional view of an N-channel IGBT. The main components of the IGBT are the P ⁺ region 1 of the collector, the N ⁺ region 2 of the buffer layer, the N ^- region 3 of the base layer, and the channel. A P base region 4, a P ⁺ emitter region 5, an N ⁺ source region 6, a polysilicon gate 7 formed on the channel forming region via a gate oxide film, an insulating film 8 and a source electrode 9.
This IGBT has an N channel MOS at the base of a PNP transistor composed of P ⁺ collector region 1, N ⁻ base region 3 and P base region 4.
It is operated by supplying current from the FET.

FIG. 7 is a partial cross-sectional view showing only the portion of the silicon substrate of the IGBT, and common portions with FIG. 6 are represented by the same symbols. That is, as shown in FIG. 7, the silicon substrate 10 of the IGBT is composed of P ⁺ region 1 (collector), N ⁺ region 2 (buffer layer), and N ⁻ region 3 (base layer). Conventionally, it is performed by the epitaxial growth method. First, the P ⁺ region 1 which is the collector region is a low resistance P type
A CZ silicon wafer is used, and a buffer layer N ⁺ is formed on top of this.
Region 2 and N ⁻ region 3 to be a base layer are sequentially deposited by epitaxial growth to form. The thickness of the main part of the substrate 10 is, for example, as shown in Table 1.

The specific resistance of N ⁺ region 2 is 0.1 to 0.2 Ωcm, and that of N ⁻ region 3 is several tens.
~ 100 Ωcm. The epitaxial growth method has good thickness controllability and can obtain a junction with a sharp concentration gradient.
The impurity concentration distribution of the silicon substrate manufactured by the epitaxial growth method is characterized in that it changes stepwise at the junction.

[Problems to be Solved by the Invention]

As described above, the silicon substrate used for the IGBT is manufactured by the epitaxial growth method. However, the epitaxial growth method requires a high level of technology, crystal defects are liable to occur, especially when a thick epitaxial layer is stacked, and the yield is significantly reduced, and the epitaxial growth apparatus itself is extremely expensive, making it easy to perform large-scale processing. Therefore, the cost of the silicon substrate is also high, and the price of the finally obtained IGBT cannot be avoided.

The present invention has been made in view of the above points, and an object thereof is to provide an inexpensive and easy substrate manufacturing method in place of an epitaxial growth method for a silicon substrate for an IGBT.

[Means for Solving the Problems]

The present invention forms all required conductivity type regions in a silicon substrate by an impurity diffusion process, and is performed as follows.

First, N-type impurities are diffused from both sides of an N-type silicon plate having a predetermined thickness, and then P-type impurities are diffused to form a P-type region from both surfaces to a certain depth.
By forming a silicon plate consisting of 5 layers up to a depth of up to 90 μm as a region where the N-type impurity concentration is higher than that of the N-type silicon plate, the silicon plate is ground and removed from one surface to a predetermined thickness. , A remaining P-type region, a high-impurity concentration N-type region, and an N-type region are produced, and this is used as the substrate of the IGBT.

[Action]

Since the silicon substrate for the IGBT obtained by the method of the present invention uses the diffusion method, the shape of the impurity concentration distribution is different from that of the silicon substrate by the epitaxial growth method, and the voltage drop of the present invention is the same at the same turn-off time due to the characteristics of the IGBT. The substrate using the substrate according to (1) is slightly higher than the conventional device, so that for the substrate of the diffusion method, the N ⁺ region, that is, the buffer layer is made considerably thicker, and the thickness of the N ⁻ region, that is, the base layer is reduced to form an epitaxial substrate. It is possible to give almost the same characteristics.

〔Example〕

FIG. 1 shows a manufacturing process of a silicon substrate according to the method of the present invention. FIG. 1 is a cross-sectional view of the manufacturing process sequence and regions of each conductivity type formed in the silicon wafer corresponding to the manufacturing process order. Are written in parallel as.

In Fig. 1, first, it has a resistance determined by the breakdown voltage of the IGBT.
N ^- silicon crystal is pulled up and N ^- region 3 (Fig. 7)
A silicon plate is obtained (a). Crystal pulling is performed by the FZ method, which easily obtains high resistance and has good controllability of resistance. Next, diffusion is performed from both sides of this silicon plate using POCl ₃ or the like to form an N ⁺ region 2 (FIG. 7) to be a buffer layer (b). Next, P ⁺ region 1 (7th
(D) is performed to form (c). Thus, as shown in FIG. 1, N ⁺ , P symmetrical about the N ⁻ region 3 in the thickness direction is formed.
It is possible to obtain a silicon plate composed of 5 layers having ⁺ regions. Finally, this is ground and removed from one surface in the thickness direction until the N ⁻ region 3 has a predetermined thickness, whereby a silicon substrate 10 similar to that shown in FIG. 7 is completed (d).

FIG. 2 shows a schematic impurity concentration distribution of the IGBT substrate manufactured by thermal diffusion and grinding as described above. As shown in FIG. 2, the impurity concentration distribution of the substrate obtained by thermal diffusion shows a Gaussian distribution in the N ⁺ region 2 (buffer layer) and P ⁺ region 1 (collector region), and this point junction has a stepwise shape. The state of impurity distribution is different from that of the substrate obtained by the epitaxial growth method.

Therefore, the IGBT using the diffusion wafer has a characteristic difference from the IGBT using the epitaxial wafer. It is IG
The main characteristics of BT are the voltage drop (V _on ) when a constant current is applied and the switching speed (t
_off ) (hereinafter referred to as a trade-off). FIG. 3 is a schematic diagram showing this trade-off in comparison between a diffusion wafer and an epitaxial wafer.
In FIG. 3, the curve (a) is for the wafer by the diffusion method and the curve (b) is for the wafer by the epitaxial method. In the diffusion method, the thickness of the N ⁺ region 2 to be the buffer layer is 30 μm is there. Since the IGBT is required to have a low V _{on and a} short t _off, it can be seen from the trade-off curve in FIG. 3 that the diffusion wafer is generally inferior to the epitaxial wafer in trade-off. That is, the on-voltage is higher in the diffusion wafer for the same turn-off time.
The curve (c) in FIG. 3 will be described later.

Peak concentration N _b N ⁺ region 2 in Figure 2 the thickness of the N ⁺ region 2 of the silicon substrate used in this trial IGBT causes for better diffusion wafer becomes higher V _on than the epitaxial wafer
The reason is that it is not sufficiently large when d _N = 30 μm. Epitaxial wafer is N ⁺ region 2 which becomes the buffer layer
The impurity concentration and the thickness of can be set individually as separate parameters during crystal growth. However, in the diffusion wafer, these cannot be set independently, and there is a fixed relationship between the impurity concentration and the thickness. FIG. 4 is a diagram showing the relationship between N _{b and} d _{N in} the diffusion experiment. As shown in Fig. 4, in the diffusion method, N _b increases rapidly with the increase of d _N. Therefore, the present inventor produced a diffusion wafer for IGBT using the thickness of the buffer layer as a parameter and prototyped an element using this, and as a result, as the buffer layer becomes thicker, the trade-off relationship is shown by the dotted line curve ( It was found that the result becomes as shown in (c) and approaches the curve (b), that is, the case of using an epitaxial wafer.

When the relationship between d _N and V _on is obtained for a device having a constant t _off , the diagram of FIG. 5 is obtained. The dotted line in FIG. 5 represents an IGBT using an epitaxial wafer as a substrate, and a partially dotted solid curve represents an IGBT using a diffusion wafer according to the present invention as a substrate. As can be seen from FIG. 5, d _N of the diffusion wafer is
In the range of 60 to 90 μm, V _on starts to decrease, and V _on is improved. However, at this level, the on-voltage is still higher in the diffusion wafer than in the epitaxial wafer, and the trade-off is slightly inferior.

This can be done as follows. Since the epitaxial wafer has the impurity concentration distribution curve that changes stepwise at the junction as described above, the breakdown voltage is purely determined by the thickness of the N ⁻ region that serves as the base layer, but the diffusion wafer is as shown in FIG. because it becomes impurity concentration distribution curve, the breakdown voltage the N ^- well region, the N ⁺ region serving as a buffer layer N ^-
The low impurity concentration on the region side also contributes. Therefore, the N ^- region of the diffusion wafer is about 1
The thickness can be reduced. When the thickness of the N ⁻ region is reduced by about 10%, the IGBT trade-off relationship is further improved even when an epitaxial wafer is used as a substrate, and the curve in FIG. 5 can be moved downward as a whole. The optimum position is almost the same as that of the epitaxial wafer.

Although the present invention has been described with respect to the N-channel IGBT,
The method of the present invention can be applied in principle to a P-channel device in which the conductivity type of each semiconductor region is reversed.

〔The invention's effect〕

Instead of a silicon wafer deposited by an epitaxial growth method as a silicon substrate used for an N-channel IGBT, in the present invention, as described in the embodiment, first, an N ^- silicon wafer is prepared and N-type impurities are thermally diffused from both surfaces thereof to form an N-type impurity. ^{A +} region is formed, P-type impurities are thermally diffused from both sides to form a P ⁺ region, and then the remaining silicon wafer is ground and removed from one side to a predetermined thickness in the thickness direction and is used as a substrate. As a result, the epitaxial wafer requires advanced technology and can be obtained from the viewpoint of equipment cost.
While the IGBT element is expensive, it is possible to realize a substrate that is inexpensive and easy to manufacture. Regarding the deterioration of the element trade-off characteristics due to the difference in impurity concentration distribution between the diffusion wafer and the epitaxial wafer, the diffusion depth of the N ⁺ region serving as the buffer layer should be made larger than that of the epitaxial wafer to be 60 to 90 μm. N serving as a base layer ^-
The solution is to reduce the thickness of the area.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a silicon substrate by the method of the present invention, FIG. 2 is a diagram schematically showing an impurity concentration distribution of a silicon substrate obtained by the method of the present invention, and FIG. 3 is a method of the present invention. IGBT using the silicon substrate obtained by the method and the conventional IGBT using the silicon substrate of the epitaxial wafer
Schematic trade-off characteristic diagram shown in comparison with
The figure shows the impurity peak concentration (N _b ) in the N ⁺ region in the diffusion experiment.
Preparative thick (d _N) and a line diagram showing the relationship, FIG. 5 is the relationship between the thickness of the substrate of the N ⁺ region for the IGBT element having a constant turn-off time (d _N) and on-voltage (V _on) FIG. 6 is a cross-sectional view of the essential parts of the IGBT, and FIG. 7 is a partial cross-sectional view of the substrate only. 1: P ⁺ region, 2: N ⁺ region, 3: N ⁻ region.

Claims (1)

[Claims] 1. A method of manufacturing a silicon substrate of a vertical conductivity modulation type MOSFET, which comprises first diffusing first conductivity type impurities from both sides of a first conductivity type silicon plate having a predetermined thickness, Then, impurities of the second conductivity type are diffused to form a second conductivity type region from both surfaces to a predetermined depth, and a first conductivity type silicon plate to a depth of 60 to 90 μm from the second conductivity type region. After forming a silicon plate composed of five layers to be a region having a high conductivity type impurity concentration, the silicon plate is ground and removed from one surface to a predetermined thickness to remove the remaining second conductivity type region and high impurities. A method of manufacturing a substrate of a vertical conductivity modulation type MOSFET, characterized in that a silicon plate composed of a concentration first conductivity type region and a first conductivity type region is used as a substrate.