JPH0793611B2 - Time division multiple processing circuit test method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] Concerning a test method of a time division multiplex processing circuit, a time division multiplex processing circuit capable of shortening a test pattern by performing a circuit operation equivalent to processing of a single channel For the purpose of providing a test method, time-division multiplex for generating output by performing a predetermined calculation in time-division by sequentially using parameters for the number of channels stored in memory for input data of plural channels. In the processing circuit, a test parameter generating means for generating a test parameter for a single channel in the time division multiplex processing circuit, and a switching means for giving the test parameter to the time division multiplex processing circuit instead of the output of the memory. Is provided, and input of a single channel is continuously given to each channel as input data of the time division multiplexing processing circuit to generate an output. It is configured by performing a test.

[Industrial application field]

The present invention relates to a test system for a time division multiplex processing circuit, and particularly for a time division multiplex processing circuit that uses a memory for parameter delay, by performing a circuit operation equivalent to single channel processing in a test mode. The present invention relates to a time division multiplexing processing circuit test method capable of shortening an input pattern.

ADPCM (Ada that performs time division multiplexing of multi-channel data
In the case of ptive differential pulse code modulation (encoder), etc., if a parameter such as a quantization step size or various coefficients of an adaptive filter is properly used for each channel by using a memory, it is attempted to sufficiently test the circuit. Then, it is usually necessary to perform a test using a long test pattern.

In such a case, it is desired to shorten the test pattern by performing a circuit operation equivalent to the single channel processing.

[Conventional technology]

FIG. 4 shows a schematic configuration of a conventional time-division multiplex ADPCM encoder. 11 is an input register (IN), 12 is a logarithmic area for converting μ-law or A-law compressed PCM data into linear PCM data. / Linear domain (P / L) converter, 13 is a subtractor (SU
B), 14 is a quantizer (Q), 15 is a selector (SEL) for switching between an operation as an encoder and an operation as a decoder, 16
Is inverse quantizer (Q ^-1 ), 17 is adder (ADD), 18 is linear
Linear area / logarithmic area (L / P) converter that converts PCM data to μ-law or A-law compressed PCM data, 19 is a coding corrector (CA) that corrects coding, and 20 is an operation as an encoder. Selector (SEL) that switches the operation as a decoder and decoder, 21 is a predictor (PRE), 22 is an output register (OUT), 23 is a bus,
24 is a random access memory (RAM).

Further, FIG. 5 shows the area division of the RAM. For example, when the number of channels of the multiplex processing is 8, the memory area of the RAM of 256 words × 16 bits is divided into eight areas CH1 to CH8. Then, the parameters for each channel are stored.

Fig. 6 shows the operation time chart in the normal mode, where ch1 to ch are set in one frame of 125 μs (8 kHz).
The 8 input signals S for 8 channels are time-division multiplexed, and the rising edge of the 8 kHz signal indicates the position of the leading channel of the input signal S.

The ADPCM encoder shown in FIG. 4 corresponds to the 1 shown in FIG.
The input signal time width for channels is the basic unit of time division multiplexing processing. Therefore, the configuration of the ADPCM encoder shown in FIG. 4 is also divided into blocks 1 to 7 for each block that can be processed in this time width. Has been done.

The operation in the normal mode will be described below with reference to FIGS. 4 and 6. When the circuit of FIG. 4 operates as an encoder, it is assumed that the selectors 15 and 20 are switched to the quantizer 14 side. The description of the operation of the decoder is omitted.

Now, the input signal S of ch1 is the input register 11 in block 1
After being converted into a signal SL in the logarithmic domain to a linear domain signal SL in the P / L converter 12 in block 2, the subtractor 13 calculates the difference from the prediction value SE given from the RAM 24 via the bus 23. Be taken. The error (difference) signal D is quantized in the quantizer 14 in the block 3 by the quantization step size Y given from the RAM 24 via the bus 23 to obtain the ADPC.
The M signal I is derived.

In block 4, the ADPCM signal I that has passed through the selector 15 is dequantized by the dequantizer 16 by the quantizing step size Y similarly given from the RAM 24 via the bus 23 and converted into the reproduction error signal DQ. RAM24 in the adder 17
Is added to the predicted value SE given via the bus 23 to generate the reproduction signal SR.

The reproduced signal SR is sent to the predictor 21 and used for calculation of the predicted value in the next sample over blocks 5 to 7.
At this time, the filter coefficients An, Bn, etc. of the adaptive filter are read from the RAM 24 via the bus 23 into the predictor 21 and used for the calculation. In block 7, the quantizer 14 generated
The ADPCM signal I is output via the output register 22.

The next input signal S of ch2 is also processed in the same manner as ch1, but is always located in the block immediately before ch1. For example, when ch1 is in block 3, ch2 is in block 2, and at this time, in block 1, ch3 is being input.

Since the processing of the time-division-multiplexed input signal is performed in such a time relationship, the timing of reading out various parameters required for calculation from the RAM 24 also needs to correspond to each channel. For example, when the parameter Y of the quantization step size of ch1 is read in the block 3, the predicted value SE of ch2 must be read in the block 2.

[Problems to be Solved by the Invention]

The ADPCM encoder shown in FIG. 4 has a RAM 24 for allowing parameters such as quantization step size and adaptive filter coefficient to be given different values for each channel. Each value is stored.

When a test is performed in the circuit shown in FIG. 4, a test input is given from the outside. However, in such a time division multiplexing processing circuit, a long test pattern is required to sufficiently test the circuit. Becomes

This is because the circuit shown in FIG. 4 performs time division multiplexing processing, and thus requires an input pattern whose number is the number of channels being multiplexed.

For example, if one word consists of 8 bits and 8 channels, a 64-bit pattern is required to test 1 sample. Therefore, if an attempt is made to increase the number of samples, the test pattern may be significantly long. I cannot avoid becoming.

The present invention is intended to solve such a problem of the prior art, and a time division multiplexing processing circuit capable of shortening a test pattern by performing a circuit operation equivalent to processing of a single channel. The purpose is to provide a test method.

[Means for Solving the Problems]

According to the present invention, as shown in the principle configuration of FIG. 1, a predetermined calculation is performed in a time-divisional manner by sequentially using parameters for the number of channels stored in the memory 1 for input data of a plurality of channels. In the time division multiplex processing circuit 2 for generating an output, a test parameter generating means 3 and a switching means 4 are provided, and an input of a single channel is continuously given to each channel as input data of the time division multiplex processing circuit 2. It is designed to generate an output and perform a test.

Here, the test parameter generating means 3 is for generating the test parameters for a single channel in the time division multiplexing processing circuit 2, and the switching means 4 is not the output of the memory 1 but the test parameter generating means. The test parameters from 3 are given to the time division multiplexing processing circuit 2.

[Action]

In the normal mode, the time division multiplexing processing circuit 2 sequentially uses the parameters for the number of channels stored in the memory 1 for the input data of a plurality of channels, performs a predetermined calculation in time division, and generates an output. .

On the other hand, in the test mode, the test parameter generating means 3 generates the test parameters for a single channel in the time division multiplex processing circuit 2 and the test parameter generating means 3 via the switching means 4. The test parameters are switched so as to be supplied to the time division multiplexing processing circuit 2 instead of the output of the memory 1.

At the same time, as input data of the time division multiplexing processing circuit 2, a single channel input is continuously applied to each channel to generate an output.

As a result, the time division multiplexing processing circuit 2 can perform a circuit operation equivalent to that at the time of processing a single channel, and therefore, compared with the conventional time division multiplexing processing circuit as shown in FIG. , The test input pattern can be shortened to a fraction of the number of multiplexed channels.

〔Example〕

FIG. 2 shows an embodiment of the present invention,
The same components as those in the figure are indicated by the same numbers, 25 is a test parameter generation circuit, and 26 is a selector (SEL).

In FIG. 2, the selector 26 is the RAM 24 in the normal mode.
, And the operation in this case is performed in the same manner as in the conventional case shown in FIG.

On the other hand, in the test mode, the selector 26 is switched to the side of the test parameter generating circuit 25, and the time division multiplexing ADPCM is used.
The encoder operates according to the single channel parameters generated by the test parameter generating circuit 25.

Fig. 3 shows the operation time chart in the test mode. In one frame of 125 µs (8 kHz), ch1
As input signals S for 8 channels of ~ ch8, input data n, n + 1, ..., N + 7 of a single channel are sequentially given, and in the next frame, input data n + 8, n + 9, ... It has been shown to be given.

In this case, the test parameter generation circuit 25 generates a parameter for a single channel corresponding to the input of a single channel, and inputs this parameter to the time division multiplexing ADPCM encoder via the selector 26.

Therefore, in the test mode, the time division multiplex ADPCM encoder shown in FIG. 2 performs the circuit operation equivalent to the single channel processing, and the parameters necessary for the operation in each operation block also generate the test parameter. By inputting from the circuit 25, channel-specific parameters are replaced with sample-specific parameters.

〔The invention's effect〕

As described above, according to the present invention, in the normal mode, the parameters for the number of channels stored in the memory are sequentially used for the input data of a plurality of channels, and a predetermined calculation is performed in a time division manner to generate an output. In the time-division multiple processing circuit, in the test mode, by inputting the test input of a single channel continuously and giving the operation parameters corresponding to the single channel, the circuit equivalent to the single channel processing Since the operation is performed, the test input pattern can be shortened to 1 / the number of multiplexed channels in the normal mode, as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing an operation time chart in a test mode, and FIG. Split multiplex ADPC
FIG. 5 is a diagram showing a schematic configuration of the M encoder, FIG. 5 is a diagram showing RAM area division, and FIG. 6 is a diagram showing an operation time chart in the normal mode. Reference numeral 1 is a memory, 2 is a time division multiplexing processing circuit, 3 is a test parameter generating means, and 4 is a switching means.

Claims (1)

[Claims] 1. A time division multiplex processing circuit for generating output by performing a predetermined calculation in time division by sequentially using parameters for the number of channels stored in a memory (1) for input data of a plurality of channels. In (2), a test parameter generating means (3) for generating a test parameter for a single channel in the time division multiplexing processing circuit (2), and replacing the test parameter with the output of the memory (1). And a switching means (4) for supplying to the time division multiplex processing circuit (2), and inputting a single channel as input data of the time division multiplex processing circuit (2) is continuously given to each channel to generate an output. A time-division multiple processing circuit test method characterized by performing the test.