JPH0793631B2 - Loop data transmission system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a loop data transmission system, and more particularly to a data transmission system having a speed lower than a minimum data transmission speed determined from a frame format of a transmission line.

(Prior Art) Conventionally, in a loop-type data transmission method that transmits data at a speed lower than the minimum data transmission rate determined by the frame format of the transmission line, a multipoint sampling method is used to format data at a minimum data transmission rate or higher. Is converted to
As shown in FIG. 3, the data is transmitted frame by frame by dividing it into several bits. In FIG. 3, F is a symbol indicating frame synchronization.

(Problems to be Solved by the Invention) Since the above-described conventional data transmission method is a multipoint sampling method, a transmission rate that is five times or more the actual data transmission rate is adopted, and therefore an extra transmission band is used. It has the drawback of being necessary.

An object of the present invention is to provide a received data clock extraction circuit and a received data frame synchronization circuit to the data transmission device connected to a loop type cyclic digital data transmission line that connects a plurality of data transmission devices with a looped transmission line. Provided, the subchannel number synchronized with the frame number and the transmission data from the terminal device is inserted into a predetermined subchannel,
Loop-type data transmission system configured to monitor the subchannel number, branch the data of the corresponding subchannel number, and then send the received data to the terminal device to eliminate the above-mentioned drawbacks and eliminate the need to use an extra transmission band. To provide.

(Means for Solving Problems) A loop data transmission system according to the present invention includes a transmission frame format generation circuit, a frame number generation circuit, a master station reception data frame synchronization circuit, and a reception data frame buffer memory circuit. , A master station data transmission device having a signal insertion circuit, a reception data clock extraction circuit, a slave station data frame synchronization circuit, a sub-channel setting switch, and a branching / insertion circuit. The device is configured by connecting a plurality of loop-shaped loops with a transmission line.

The transmission frame format generation circuit is for generating a transmission frame format including a synchronization bit signal, a frame number signal time slot, and a data time slot by a master clock.

The frame number generation circuit is for generating a frame number by the output of the transmission frame format generation circuit.

The master station reception data frame synchronization circuit is for determining frame synchronization according to a data frame received from another device and establishing synchronization.

The reception data frame buffer memory circuit temporarily stores data from another device according to the frame synchronization of the reception data frame synchronization circuit and reads the stored data according to the synchronization bit signal of the transmission frame format.

The signal insertion circuit is for multiplexing the synchronization bit signal of the transmission frame format generation circuit, the frame number signal of the frame number generation circuit, and the reception data and transmitting the multiplexed data to the outside.

The reception data clock extraction circuit is for extracting a clock from data from another device.

The slave station reception data frame synchronization circuit determines the frame synchronization according to the data frame received from another device, establishes the synchronization, and outputs the timing signal of the data time slot for dropping / adding and the time slot of the frame number signal. It is for reading the frame number from and outputting the frame number.

The add / drop circuit inserts the designated sub-channel number for transmitting and receiving data and the transmission data into the data time slot of the frame number having the same value as the sub-channel number, and inserts the sub-channel number in the data time slot. It is for monitoring, branching the data of the corresponding sub-channel number, and sending the received data to the outside.

(Example) Next, this invention is demonstrated with reference to drawings.

FIG. 1 is a block diagram showing an embodiment of a loop type data transmission system according to the present invention.

In FIG. 1, reference numeral 1 denotes a data transmission device serving as a master station,
Reference numeral 4 is a data transmission device serving as a slave station, 5 is a master clock generation circuit, 6 is a transmission frame format generation circuit, 7 is a frame number generation circuit, 8 is a reception data frame synchronization circuit for master station, and 9 is a reception data frame pattern. A far memory circuit, 10 a signal insertion circuit, 11 a received data clock extraction circuit, 12 a slave station received data frame synchronization circuit, 13
Is a branching / inserting circuit, 14 is a data transmission path, and 15 is a sub-channel setting switch.

In FIG. 1, a loop-type data transmission path is constituted by a data transmission device 1 which is a master station and data transmission devices 2 to 4 which are slave stations, and the data transmission device 1 which is a master station outputs from a master clock generation circuit 5. The received data frame buffer memory circuit 9 stores the data input from the data transmission line 14 at a predetermined address in the received data frame buffer memory circuit 9 after the received data frame synchronization circuit 8 determines whether or not the data is input.

Therefore, in synchronization with the frame read timing signal from the transmission frame format generation circuit 6, the output of the reception data frame buffer memory circuit 9 for reading the reception data accumulated at a predetermined address and the reception data frame buffer memory for reading the accumulated reception data The output of the circuit 9, the synchronization bit signal (F) from the transmission frame format generation circuit 6, and the frame number signal from the frame number generation circuit 7 synchronized with the frame number count signal from the transmission frame format generation circuit 6 are signaled. It is multiplexed by the insertion circuit 10 and output to the data transmission line 14.

In the data transmission devices 2 to 4 serving as slave stations, the reception data clock extraction circuit 11 extracts a clock from the reception data of the data transmission line 14, the reception data frame synchronization circuit 12 determines synchronization, and the data time is dropped / inserted. The timing signal of the slot is output, the frame number is read from the time slot of the frame number signal, and the frame number is sent to the branch / insert circuit 13. Therefore, in the add / drop circuit 13, the frame number signal (NO) added by the frame number generation circuit 7 of the data transmission device serving as the master station.
Then, the frame from which the setting number of the sub-channel setting switch of its own station matches and the data from the connected terminal device and the sub-channel number specified by the sub-channel setting switch are inserted. Further, only the data whose sub-channel number is the same as the sub-channel setting number of its own station is discriminated from the received data and branched, and the data is sent to the connected terminal device.

Next, the operation of the present invention will be described with reference to the time chart of FIG.

FIG. 2 shows the output data to the data transmission line 14 of the data transmission devices 1 to 4, and each of them shows a time-sequential sequence. In FIG. 2, the data transmission device 1 serving as the master station cyclically transmits frames with frame numbers # 1 to # 4, and the data transmission device 2 serving as the slave station assigns the subchannel number # 1 to the frame with frame number # 1. Insert data A and. On the other hand, the data transmission device 3 serving as a slave station
In the data transmission device 4 serving as a slave station, the sub-channel number # 1 is determined, the data A is branched, the data B and the sub-channel # 1 are added to the frame of the frame number # 1, and the data is returned. To do.

The data returned from the data transmission device 4, which is a slave station, is
The data transmission apparatus 1 serving as the master station receives the transmission delay correction by the received data frame buffer memory circuit 9 and adds a new frame number that does not match the subchannel number.
In the data transmission device 2 serving as a slave station, the subchannel number # 1 is determined from the received data, and the data B is branched.

(Effect of the Invention) As described above, according to the present invention, by adding a number to a frame and further adding a sub-channel number which is the same as the frame number to the transmission data, the frame number after the transmission delay correction in the loop data transmission is added. Regardless of updating, data can be transmitted to the sub-channel number once every multiple frames, and can be divided into a transmission band that is an integral fraction of the minimum data transmission rate determined by the frame format. Moreover, there is an effect that the number of multiplexed lines can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a loop type data transmission system according to the present invention. FIG. 2 is a time chart showing the data transmission of FIG. FIG. 3 is a time chart showing data transmission according to the prior art. 1 to 4 ... data transmission device 5 ... master clock generation circuit 6 ... transmission frame format generation circuit 7 ... frame number generation circuit 8 ... master station data frame synchronization circuit 9 ... reception data frame buffer memory circuit 10 …… Signal insertion circuit 11 …… Received data clock extraction circuit 12 …… Received data frame synchronization circuit for slave station 13 …… Branch / insertion circuit 14 …… Data transmission line 15 …… Sub channel setting switch F …… Synchronization Bit signals # 1 to # 4 ... Frame number

Claims (1)

[Claims] 1. A transmission frame format generation circuit for generating a transmission frame format including a sync bit signal, a time slot of a frame number signal, and a data time slot by a master clock, and an output of the transmission frame format generation circuit. A frame number generation circuit for generating a frame number, a master station reception data frame synchronization circuit for determining frame synchronization according to a data frame received from another device and establishing synchronization, and the reception data frame synchronization circuit A received data frame buffer memory circuit for temporarily storing data from another device in accordance with the frame synchronization of, and reading the stored data according to the synchronization bit signal of the transmission frame format; and a synchronization bit of the transmission frame format generation circuit. A signal, a frame number signal of the frame number generation circuit, and a signal insertion circuit for multiplexing the received data read from the received data frame buffer memory circuit and transmitting the multiplexed data to the outside; A reception data clock extraction circuit for extracting a cloak from the data from the other device, and a data time slot for branching / inserting, determining frame synchronization according to the data frame received from the other device to establish synchronization. It outputs the timing signal, reads the frame number from the time slot of the frame number signal, and outputs the frame number, the slave station reception data frame synchronization circuit, and the specified sub channel number and transmission data for transmitting and receiving data. The data number of the frame number that has the same value as the channel number. A branching / inserting circuit for inserting into a time slot, monitoring the subchannel number in the data time slot, branching the data of the corresponding subchannel number, and sending the received data to the outside. A loop-type data transmission method, which is configured by connecting a plurality of data transmission devices that will be established as slave stations by a transmission line in a loop.