JPH0793643B2 - Carrier signal reproduction circuit - Google Patents

Description

The present invention relates to a carrier signal reproducing circuit in 16QAM (16-ary quadrature amplitude modulation).

[Conventional technology]

16QAM is a technology for transmitting high-speed data, for example, a digitized video signal using a signal line having a relatively good C / N, such as a CATV signal line (for example, Japanese Patent Publication No. 58-23022). Gazette).

And 16QAM is superior in terms of band utilization efficiency. In addition, 16QA which transmits data with fixed reference phase
With M, the hardware configuration becomes simple.

[Problems to be solved by the invention]

In 16QAM, where the reference phase is fixed and data is transmitted, in order to minimize code errors on the receiving side, when the carrier signal is regenerated, the reference phase of the regenerated carrier signal must be strict. Therefore, the carrier signal reproducing circuit becomes complicated.

[Means for solving problems]

The digital data Sd to which the synchronous data 00H having a predetermined value is added every predetermined period Th,
In h, when reproducing the carrier signal from the 16QAM signal Sm in which 16QAM is performed so that the level and phase of the carrier signal So become a predetermined reference value, the period Th of the synchronous data 00H is detected from the 16QAM signal Sm, This detected sync data 00H
PLL in reference to 16QAM signal Sm only during period Th (70)
Is locked and the carrier signal So is taken out from the locked PLL (70).

[Action]

The period Th of the synchronous data 00H is detected from the 16QAM signal Sm, and the 16QAM is detected only in the detected period Th of the synchronous data 00H.
The signal Sm is referred to, the PLL (70) is locked, and the carrier signal So is extracted from the locked PLL (70).

〔Example〕

First, as a prerequisite technique, an example of a 16QAM transmission circuit and a reception circuit for transmitting data with a fixed reference phase will be described.

FIG. 2 shows a transmitting circuit and FIG. 3 shows a receiving circuit.

Then, in the transmission circuit, for example, an NTSC color video signal Sa is transmitted through the terminal (11) to the A / D converter (1
Is supplied to the 2), at the frequency f _b (3 times the frequency 3f _b of 3.58 MHz) from the burst signal Sb contained is supplied to the clock generation circuit (31) to the signal Sa, and the burst signal Sb A clock CK ₃ synchronized with the clock signal CK ₃ is formed, and this clock CK ₃ is supplied to a converter (12) to convert the signal Sa into a digital signal Sd of 8 bits with one sampling having a sampling frequency of 3f _b . At this time, as shown by the solid line in FIG. 4, the pedestal level (0
IRE) is signal Sd 40H, sync tip level (-40 IR
A / D conversion is performed with the polarity and ratio such that E) becomes 08H.

Further, the signal Sd is supplied to the correction circuit (13), and the clock CK ₃ is supplied to the correction circuit (13). As shown by a broken line in FIG. The level is corrected from 08H to 00H, and the corrected signal Sd is supplied to the addition circuit (14) and the clock CK ₃ is supplied to the M-sequence generation circuit (32) to form the M-sequence scrambled signal Ss. This signal Ss is supplied to the adder circuit (14), and the signal Sd is applied to the sync tip portion (period T
The section excluding h) is scrambled. The scramble by the signal Ss is an operation for eliminating the correlation of the signal Sd (Sa).

Then, this scrambled signal Sd is supplied to the conversion circuit (15), and at the same time as the frequency of 6 times the burst signal Sb from the clock generation circuit (31) and this signal Sb.
Clock CK ₆ synchronized with the retrieved, this clock CK ₃
And the clock CK ₃ are supplied to the conversion circuit (15) to output the signal Sd.
, Each sample 8 bits is divided into 4 bits. That is, assuming that the bits b _{7 to} b ₀ are the MSB to LSB of one sample of the signal Sd in order, the bits b ₇ and b ₃ , b ₆ and b ₂ , during one sample period of the signal Sd (the cycle of the clock CK ₃ ), b ₅ and b ₁ , b
₄ and b ₀ are taken out every 1/2 sample period (cycle of clock CK ₆ ).

And these extracted bits b ₇ and b ₃ , b ₆ and b ₂ , b ₅
b ₁ , b ₄ and b ₀ are respectively supplied to the binary transversal filters (16A) to (16D) and demodulated on the receiving side so that the baseband signal is exactly the Nyquist first reference (impulse response waveform axis). The spectrum is corrected in the time domain so as to satisfy (equal interval intersection with). In addition,
At this time, in the clock generation circuit (31), a clock CK ₁₂ having a frequency double that of the burst signal Sb12 and synchronized with this signal Sb is formed, and this clock CK ₁₂ is supplied to the filters (16A) to (16D). It

When the output signals of the filters (16A) to (16D) are signals Ba to Bd, respectively, the signal Ba is added to the adder circuit (17A).
And the signal Bb is supplied to the attenuator (17B) to reduce its level to 1/2 and then supplied to the adder circuit (17A), which is indicated by Bi = Ba + 1 / 2Bb from the adder circuit (17A). The added signal Bi obtained is taken out. In this case, for the sake of simplicity, if the signals Ba and Bb from the filters (17A) and (17B) are rectangular wave signals, the signal Ba of the signal Ba supplied to the adder circuit (17A) is changed as shown in FIG. Level (peak value) is +
1 or -1, and the level of the signal Bb is +1/2 or -1
Since it is / 2, the level of the addition signal Bi is any one of +1.5, +0.5, -0.5, and -1.5 corresponding to the levels of the signals Ba and Bb.

In addition, the signal Bc from the filter (16C) is added to the adder circuit (17C).
The signal Bb from the filter (16D) is set to 1/2 level by the attenuator (17D) and then supplied to the adder circuit (17C) to generate the added signal Bq represented by Bq = Bc + 1 / 2Bd. Taken out. The signal Bq is also one of the four values, like the signal Bi.

Then, these signals Bi and Bq are low-pass filters (18A),
It is supplied to (18C) to remove unnecessary components and then supplied to the double-balance type balanced modulation circuits (21A) and (21C) as a modulation input, and at a predetermined frequency in the oscillation circuit (35), for example, 130MHz. The oscillation signal So is formed, and this oscillation signal So is supplied to the phase shift circuit (36) so that the phases are mutually changed.
The carrier signals Ci and Cq differ by 90 °. These signal Ci and Cq
Are supplied to the modulation circuits (21A) and (21C) and are balanced-modulated by the signals Bi and Bq to extract the modulated signals Si and Sq. The signals Si and Sq are supplied to the addition circuit (22) and Sm = Si ＋ Sq
The addition signal Sm represented by is extracted.

In this case, the signal Sm can be shown as in FIG.
That is, since the signals Ci and Cq have a phase difference of 90 °, if the phase axes of the signals Ci and Cq are I axis and Q axis,
These I axis and Q axis are orthogonal to each other. And signal C
Levels (peak values) of signals Bi and Bq that are modulating i and Cq
Takes only ± 1.5 or ± 0.5 on the I-axis and Q-axis. Therefore, points marked with "X" are points (significant points) that the signal Sm can take. Further, the possible points (x mark) of this signal Sm are shown by the original signals Ba to Bd, that is, the code arrangement is shown in FIG. Therefore,
The signal Sm is a 16QAM modulated signal.

Then, in this signal Sm, a point R of Ba to Bd = "0000"
Has a phase of 255 ° with respect to the I axis and a level of However, it is Sd = 00H that Ba ~ Bd = "0000" continues.
, That is, the sync chip period Th of the video signal Sa
It is time for That is, this point R corresponds to a synchronization pulse.

Further, since the sync chip portion of the video signal Sa is 00H, the point R is continuous in the sync chip period Th. Therefore, in the signal Sm, when the level and the phase of the point R are continuous for the period Th, it is the sync tip portion.

Then, the signal Sm is supplied to the bandpass filter (23) to remove unnecessary components, then taken out to the terminal (24), and further sent to, for example, the CATV line (25).

Also, in the receiving circuit, the signal Sm from the line (25)
However, through the terminal (41), a bandpass filter (4
2) is supplied to the AGC circuit (43) and becomes a signal Sm of a constant level, and this signal Sm is the synchronous detection circuit (44A), (44A).
C) and the reference carrier regeneration circuit (61)
Is supplied to the reference carrier signal So (details will be described later), and this signal So is supplied to the phase shift circuit (62) to be demodulated carrier signals Ci and Cq. These signals Ci and Cq are detected by the detection circuit. Signals Sm to Signals Bi and B supplied to (44A) and (44C)
q is demodulated, and the signal Bi is the voltage comparison circuit (51A) to (51C).
Is supplied to the reference circuit and the voltage is compared with the reference voltages Va to Vc whose levels are 1, 0 and -1, respectively, as shown in FIG.
From A) to (51C), when Bi ≧ Va, Bi ≧ Vb, Bi ≧ Vc, the comparison outputs that become “1” are taken out, and the comparison outputs are supplied to the conversion circuit (52A). Bit signal Ba, Bb
And the signals Ba and Bb are supplied to the conversion circuit (53).

Further, similarly, the signal Bq from the detection circuit (44C) is supplied to the voltage comparison circuits (51D) to (51F) and compared with the voltages Va to Vc, and the comparison output is supplied to the conversion circuit (52C). The original signals Bc and Bd are converted, and the signals Bc and Bd are supplied to the conversion circuit (53).

Then, for example, the comparison output of the comparison circuit (51E) is supplied to the clock reproduction circuit (65) to form the clock CK ₆ ,
This clock CK ₆ is supplied to the conversion circuit (53) and the signal Ba
~ Bd is converted into a signal Sd, and this signal Sd is supplied to the descrambling circuit (54) and the clock recovery circuit (6
5) the clock CK ₃ is supplied to descramble the signal Sd, the descrambled signal Sd is supplied to the D / A converter (55), and the clock regeneration circuit (65) supplies the clock CK ₃ Is supplied and the signal Sd is the original NTS
C Color video signal Sa is converted and this signal Sa is
6) Taken out.

FIG. 1 shows an example of a carrier reproducing circuit (61) according to the present invention, and FIG. 9 shows the waveform of each part thereof (hereinafter this diagram is referred to as a waveform diagram).

Then, in this carrier reproduction circuit (61), (70)
Indicates a PLL, the signal Sm from the AGC circuit (43) is supplied to the phase comparison circuit (71), and the oscillation signal S ₀ whose free-running frequency is equal to the carrier frequency of the signal Sm is extracted from the VCO (74). , This signal S ₀ is supplied to the comparison circuit (71)
The phases of Sm and S ₀ are compared, and the comparison output S ₁ is supplied to the gate circuit (72).

In this case, the signal Sm is fixed to the level and phase of the point R described above for the period Th in the sync tip portion, but becomes the level and phase of the point X corresponding to the level of the signal Sa in other periods. ing. Therefore, the signal in A of the waveform diagram
A waveform of Sm is shown, which is a sine wave having a constant level and a constant phase in the sync tip period Th, and a level and a phase corresponding to the level of the signal Sa in the other period Td.

Then, in the comparison circuit (71), such a signal Sm
Since the signal S ₀ and the signal S ₀ are compared in phase, the phase comparison output S ₁ in the period Th becomes a constant level DC signal if the signal S ₀ is locked to the signal Sm, and if not locked. , A DC signal whose polarity and level change at a speed corresponding to the phase difference between the signals Sm and S ₀ , as shown in B of the waveform diagram. Further, the period Td becomes an alternating signal corresponding to the signal Sm.

Therefore, in the gate circuit (72), a pulse Ph
As a result, only the signal S ₁ in the period Th is extracted, and the extracted signal S ₁ is supplied to the low-pass filter (73) and the DC signal having the polarity and the level corresponding to the phase difference between the signals Sm and S ₀ in the period Th. And this signal is supplied to the VCO (74) as its control signal. Therefore, in the steady state,
The oscillation signal S ₀ of the VCO (74) is phase-locked with the signal Sm in the period Th, that is, becomes an oscillation signal of a constant phase having a phase difference of 90 ° with respect to the point R described above.

Then, the signal S ₀ is supplied to the phase circuit (62) to be carrier signals Ci, Cq, and further, the signals Ci, Cq are supplied to the detection circuits (44A), (44C) and the signal Sm to the signal Bi. , Bq
Is demodulated.

Further, (80) shows a detection circuit in the sync tip period,
The signal Sm from the AGC circuit (43) is supplied to the phase comparison circuit (81), the signal S ₀ is supplied to the comparison circuit (81), and the signal S ₁ is also extracted from the comparison circuit (81). Signal S ₁
Is supplied to the limiter amplifier (82) and is limited, so that the level of the DC signal Sh in the period Th is fixed to +1 (maximum value) or -1 (minimum value) as shown in C of the waveform diagram. ₂ and this signal S ₂ is a square circuit (83)
Is supplied and squared, the DC signal Sh in the period Th becomes a signal S ₃ of "1" level as shown in D of the waveform diagram. It should be noted that this signal S ₃ has a level of either “0” or “1” corresponding to the signal Sa in the period Td.

Then, the signal S ₃ is supplied to the clear input CL of the counter (84), and the clock CK ₃ is supplied from the clock reproduction circuit (65) to the counter (84) as a count input. Therefore, the counter (84) counts the clock CK ₃ , but the signal S ₃ frequently repeats “0” and “1” during the period Td, and when S ₃ = “0”, the counter (84 ) Is cleared, the count value of the counter (84) does not increase so much as shown in E of the waveform diagram, and the carry output CY thereof remains "0". However, in the period Th, the state of S ₃ = “1” does not continue for 20 sample periods and the counter (84) is not cleared, so the count value of the counter (84) gradually increases, and The carry output CY becomes "1" at some point.

Then, the carry output CY is supplied to the shaping circuit (85) to be a pulse Ph having a predetermined pulse width in the next period Th as shown in F of the waveform diagram, and this pulse Ph is supplied to the gate circuit (72). The DC signal of the period Th of the signal Sm supplied as the control output is supplied to the filter (73). Therefore, in the PLL (70), the signal S ₀ is phase-locked with the signal Sm of the period Th as described above.

In this case, according to the present invention, as is apparent from the above, the structure of the carrier reproducing circuit (61) is simple. Further, the transmitting circuit and the receiving circuit are simple as a whole.

Since the synchronous detection circuit and the phase comparison circuit are essentially the same, the comparison circuit (81) is replaced by the circuit (31) in the above description.
Or it can be combined with (44C).

In the case of a continuous information signal, for example, a voice signal,
In the transmission circuit, after the digital signal Sd, the time axis is compressed for each unit period to form a synchronization period corresponding to the sync tip period Th, and the level of this period is set to 00H. It is sufficient to extend the time axis of.

Further, instead of the carry output CY of the counter (84), the count value of the counter (84) can be decoded to obtain a pulse corresponding to the carry output CY when the count value reaches a predetermined value. Alternatively, instead of the counter (84), the signal S ₃ may be integrated and the level of the integrated output may be determined to obtain a pulse corresponding to the carry output CY in an analog manner.

〔The invention's effect〕

The period Th of the synchronous data 00H is detected from the 16QAM signal Sm, the PLL (70) is locked by referring to the 16QAM signal Sm only in the detected period Th of the synchronous data 00H, and the locked P
Since the carrier signal So is taken out from the LL (70), its configuration is simple.

[Brief description of drawings]

FIG. 1 is a system diagram of an example of the present invention, and FIGS. 2 to 9 are diagrams for explaining the same. (12) is an A / D converter, (15), (52A), (52C),
(53) is a conversion circuit, (21A) and (21C) are balanced modulation circuits,
(31) is a clock generation circuit, (65) is a clock recovery circuit, (44A) and (44C) are synchronous detection circuits, and (51A) to (51).
F) is a voltage comparison circuit, (55) is a D / A converter, (61) is a carrier regeneration circuit, (70) is a PLL, (71) and (81) are phase comparison circuits, (80) is a detection circuit, ( Reference numeral 82 is a limiter amplifier, (83) is a squaring circuit, and (84) is a counter.

Claims (1)

[Claims] 1. Digital data to which a predetermined value of synchronization data is added every predetermined period, so that the level and phase of a modulated signal have a predetermined reference value during the period of the synchronization data. In reproducing the carrier signal of the modulated signal from the 16QAM signal that has been performed, the PLL is locked by referring to the 16QAM signal only in the period of the synchronous data, and the carrier signal is taken out from the locked PLL. In the carrier signal reproducing circuit, a comparator for comparing the phase of the VCO output included in the PLL and the phase of the modulated signal, a limiter for limiting the output of the comparator to a predetermined value, and an output of the limiter A square circuit for squaring, and a carry output is generated when the output of the square circuit is 0 and a predetermined clock is counted for the period of the synchronous data. A counter, a shaping circuit that shapes the carry output into a pulse having a predetermined pulse width, and a gate circuit that controls the supply of the output of the phase comparator included in the PLL to the VCO according to the pulse. A carrier signal reproducing circuit having.