JPH0795392B2 - Dynamic RAM - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a dynamic RAM (random access memory), for example, a technique effectively used for a dynamic RAM accessed in units of 4 bits. It is a thing.

[Conventional technology]

As a high-speed access in the dynamic RAM, there is a nibble mode in which address progress is performed in synchronization with the column address strobe signal ▲ ▼ to transfer data in time series. As a dynamic RAM having such a nibble mode, for example, Hitachi, Ltd., Showa 60
Issued in September, "Hitachi IC Memory Data Book" Page 269-Page 275
There is. The nibble mode is applied to a dynamic RAM that is accessed in units of 1 bit, and the nibble address uses 1 bit each of a row (X) system and a column (Y) system.

[Problems to be solved by the invention]

The inventor of the present application has examined adding the above-mentioned nibble mode function to a dynamic RAM that is accessed in a unit of a plurality of bits such as 4 bits. In this case, for example, a total of 16 memory cells, each selected from 4 memory blocks by 4 bits, are selected. In order to lead to external terminals in 4-bit units by row and column addresses from the conventional ones, the information of the memory cells arranged on the right side (left side) in the semiconductor chip is arranged on the left side (right side). A signal line for leading to the external terminal is required. As a result, 16 pairs of common data lines need to be arranged so as to penetrate through the main amplifier group as described above. Therefore, it has been found that the design of the main amplifier becomes complicated and the area occupied by the main amplifier increases.

An object of the present invention is to provide a dynamic RAM that simplifies a main amplifier while realizing a nibble mode in units of a plurality of bits.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM accessed in units of a plurality of bits, continuous access synchronized with a column address strobe signal is performed by a nibble address consisting of only a column address signal.

[Work]

According to the above means, the signal path between the memory block and the main amplifier and the data input / output circuit can be completely separated, so that the number of signal lines penetrating through the main amplifier can be halved.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a dynamic RAM according to the present invention. Although not particularly limited, each circuit block shown in the figure is formed on a semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique, though not particularly limited thereto.

Although not particularly limited, this embodiment shows an example in which a nibble mode is added to a dynamic RAM which is accessed in units of 4 bits. The main blocks in the figure are drawn according to the actual geometrical arrangement on the semiconductor chip.

The memory array is composed of four memory blocks M1 to M4. The memory blocks M1 to M4 are arranged such that the memory blocks M1 and M2 and the memory blocks M3 and M4 are divided into right and left with the column decoder YDCR as a center. Further, the memory blocks M1 and M2 and M3 and M4 are arranged separately above and below centered on the row decoders XDCR1 and XDCR2, respectively.

The addresses AX and AY are supplied from a common external address terminal in time series in synchronization with the row address strobe signal ▲ ▼ and the column address strobe signal ▲ ▼. The address buffer ADB receives the row address signal AX supplied in time series, forms an internal address signal ax, and transmits it to the row decoders XDCR1 and XDCR2. A signal line for transmitting the internal address signal ax is provided so as to penetrate through the column decoder YDCR (not shown). The row decoders XDCR1 and XDCR2 decode the address signal ax and perform word line selection operations of the memory blocks M1, M2 and M3, M4 in synchronization with a word line selection timing signal (not shown).

The address buffer ADB also receives the column address signal AY supplied in time series and receives the internal address signal ay.
Is formed and transmitted to the column decoder YDCR. Of these internal address signals ay, for example, 2-bit address signals ayn-1 and ayn are supplied to the counter circuit COUNT as nibble addresses. The column decoder YDCR is
The rest of the address signals ay except the nibble address signals ayn-1 and ayn are decoded and synchronized with the data line selection timing signal (not shown) to generate memory blocks M1, M2 and M, respectively.
Generates data line selection signals for M3 and M4. Each memory block
It is to be understood that M1 to M4 include a column switch circuit that receives the data line selection signal and connects the complementary data line of the selected memory array to the common complementary data line.

Although not shown, each of the memory blocks M1 and M4 includes a sense-up circuit, an active restore circuit and a precharge circuit if necessary, corresponding to a complementary data line to which the memory cells are coupled.

In this embodiment, since the nibble mode is realized in units of 4 bits, the address selection operation by the row decoders XDCR1 and XDCR2 and the column decoder YDCR selects the memory cells of 4 bits from each of the memory blocks M1 to M4. I do. Therefore, the column decoder YD
Between the CR and the memory blocks M1, M2 and M3, M4 on the left and right of the CR, eight pairs of common complementary data lines (one pair is represented by one line in the figure) are arranged.

Eight main amplifiers MA1 and MA2 are provided corresponding to these eight pairs of common complementary data lines. Eight pairs of common complementary data lines pass through for transmitting write signals in these main amplifiers MA1 and MA2.

The output terminal of the main amplifier MA1 is a multiplexer MPX.
It is connected to the input terminal of the data output circuit DOB1 including (column selection circuit). The data output circuit DOB1 has external terminals D1 and D
It consists of two circuits corresponding to 2. This allows
The multiplexer MPX selects two out of the eight constituting the main amplifier MA1 according to the address incremented by the counter circuit COUNT and supplies them to the corresponding two circuits of the data output circuit DOB1.

Similarly to the above, the output terminal of the main amplifier MA2 is connected to the input terminal of the data output circuit DOB2 including the multiplexer MPX (column selection circuit). Data output circuit DOB2
Is composed of two circuits corresponding to the external terminals D3 and D4. As a result, the multiplexer MPX selects two out of the eight constituting the main amplifier MA2 according to the address incremented by the counter circuit COUNT and supplies them to the corresponding two circuits of the data output circuit DOB2. It

The external terminals D1 and D2 are connected to the input terminals of a data input circuit DIB1 composed of two circuits. At the output of these two circuits, a multiplexer MPX similar to the above is provided. Configure the data input circuit DIB1 according to the address incremented by the counter circuit COUNT 2
The output terminals of one circuit are connected to two pairs of common complementary data lines among the eight pairs of common complementary data lines. As above,
The external terminals D3 and D4 are connected to the input terminals of a data input circuit DIB2 composed of two circuits. At the output of these two circuits, a multiplexer MPX similar to the above is provided. The output terminals of the two circuits forming the data input circuit DIB2 are connected to two pairs of common complementary data lines of the eight pairs of common complementary data lines according to the address incremented by the counter circuit COUNT.

The counter circuit COUNT uses the nibble address signal ayn-1.
And ayn are supplied as initial values, a counting operation (address stepping operation) is performed by using the signal C supplied in synchronization with the column address strobe signal ▲ ▼ as a clock, and a multiplexer select signal (decode signal according to this address) ) Is formed. As a result, in synchronization with the column address strobe signal CAS, a read / write operation in units of 4 bits can be continuously performed a maximum of 4 times.

The timing control circuit TC has a row address strobe signal ▲ ▼, a column address strobe signal ▲ ▼ and a write enable signal ▲ that are supplied from external terminals.
In response to .tau., The operation mode is identified and various timing signals such as a word line selection timing signal and a data line selection timing signal are generated accordingly. For example, in the above-mentioned nibble mode, a row address strobe signal
When the column address strobe signal ▲ ▼ is set to the high level and then to the low level again while ▼ is maintained at the low level, the signal C is generated, the counter circuit COUNT performs the address step operation, and the step The multiplexer MPX is switched according to the address.

In this embodiment, since the nibble operation is performed by using the column address signals ayn-1 and ayn, the common complementary data lines can be distributed right and left completely independently. That is, the address for selecting the 4-bit common data line (main amplifier) from the 16-bit common complementary data line is performed only by the column address. As a result, it is possible to divide each of the right and left by 8 bits and select 2 bits from each. As a result, for example, the common complementary data lines (input / output lines) corresponding to the left (right) memory blocks M1, M2 (M3, M4) are connected only to the left (right) main amplifier MA1 (MA2). It will be one. As a result, the number of common complementary data lines passing through the main amplifier MA1 (MA2) can be reduced to 8 pairs. Therefore, the occupied area of the signal line passing through the main amplifier MA1 (MA2) can be reduced. Therefore, the main amplifier can be easily designed and the occupied area can be reduced.

The operation and effect obtained from the above embodiment is as follows. That is, a dynamic RAM that is accessed in units of multiple bits
In the above, by performing the continuous access in synchronization with the column address strobe signal by the nibble address including only the column address signal, the signal path between the memory block and the main amplifier and the data input / output circuit can be completely separated. . As a result, the number of signal lines penetrating through the main amplifier can be halved, so that the main amplifier can be easily designed and the occupied area can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor. For example, in byte mode where continuous access is performed 8 times in units of 4 bits,
Various combinations such as a nibble mode in which continuous access is performed four times in 8-bit units can be adopted.

Further, the memory block and its address selection circuit adopt various embodiments such as divided into smaller parts in order to shorten the wiring lengths of the data lines and word lines to which the memory cells are coupled. Is something that can be done.

INDUSTRIAL APPLICABILITY The present invention can be widely used for dynamic RAMs that perform memory access in units of multiple bits.

〔The invention's effect〕

The following is a brief description of an effect obtained by the representative one of the inventions disclosed in the present application. That is, by adding a function to perform continuous access in synchronization with a column address strobe signal by a nibble address consisting of only a column address signal to a dynamic RAM accessed in units of multiple bits, a memory block, a main amplifier, and a data The signal path with the input / output circuit can be completely separated. As a result, the number of signal lines penetrating through the main amplifier can be halved, so that the design can be facilitated and the occupied area can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. M1 to M4 …… Memory block, XDCR1, XDCR2 …… Row decoder, YDCR …… Column decoder, ADB …… Address buffer, MA1, M2 …… Main amplifier, DOB1, DOB2 …… Data output circuit, MPX …… Multiplexer, DIB1, DIB2 …… Data input circuit, COUNT …… Counter circuit, TG …… Timing control circuit

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Claims (1)

[Claims] 1. A memory array to be accessed in units of M × N bits, a first common data line group provided corresponding to a plurality of first data lines of the memory array, and the memory array. A second common data line group provided corresponding to the plurality of second data lines and a row address signal which is supplied in synchronization with the row address strobe signal, and decodes the received row address signal and the row address signal. A row address decoder for selecting a word line and an address signal of a first plurality of bits of a column address signal supplied in synchronization with a column address signal are received and decoded to decode a plurality of first address of the memory array. A plurality of data lines to be selected among the data lines are coupled to the first common data line group, and the plurality of second data lines are connected.
Column decoder for coupling a plurality of data lines to be selected to the second common data line group, and a second plurality of bit address signals among the column address signals at the start of stepping. A counter that is received as a value and is incremented by a clock signal that is formed based on the column address strobe signal; a first plurality of external terminals and a second plurality of external terminals, each of which has a predetermined number of M pieces. A terminal, which is provided corresponding to the first common data line group, is sequentially selected by the output of the counter, and outputs data to the first plurality of external terminals in time series over N times. A plurality of data output circuits and a second common data line group, which are sequentially selected by the output of the counter and are connected to the second plurality of external terminals N times. A second plurality of data output circuits for outputting data in time series, and a plurality of bit write signals supplied from the first plurality of external terminals are time-series over N times based on the counter output. A plurality of bit write signals supplied from the first plurality of data input circuits for transmitting to the first common data line corresponding to the above and the second plurality of external terminals are transmitted N times based on the counter output. And a second plurality of data input circuits for transmitting to the second common data line corresponding to each other in time series, and a dynamic RAM.