JPH0795396B2 - Control method of semiconductor memory device having radiation resistance - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device such as an LSI memory, and more particularly to a storage device control method with improved radiation resistance.

[Conventional technology]

Figure 4 shows the CM used in the conventional static memory.
It is a circuit diagram of an OS memory cell.

In the circuit of FIG. 4, four N-channel field effect transistor Q ₁₁ to Q ₁₄ and using the two P-channel field effect transistor Q _15, Q _16, the drain of Q _11, the Q ₁₂ gates, Q The drain of _{13 and} the drain of Q ₁₅ and the gate of Q ₁₆ are connected to form the first node N _1, and the gate of Q ₁₁ , the drain of Q ₁₂ , the drain of Q ₁₄ , the gate of Q _{15 and} the gate of Q _{16 are connected.} Connect the drains of each to the second node N
₂ , the gate of Q _{13 and} the gate of Q ₁₄ are connected to the word line W, the source of Q ₁₃ is connected to one bit line B _1, and the source of Q ₁₄ is connected to the other bit line B _2. a source connected to the source and Q ₁₆ of Q ₁₅ to the power supply Vcc, Q ₁₁ and
The source of Q ₁₂ is connected to GND.

In the circuit of Figure 4 such above, the "1" and "0" of the information is stored in correspondence with the voltage V ₂ at the node N voltage V ₁ of the ₁ and node N _2, the voltage V ₁ and V ₂ is electrically held by cross-coupled transistors Q ₁₁ , Q ₁₂ , Q ₁₅ and Q ₁₆ .

At the time of reading, the bit lines B ₁ and B ₂ are pulled up, and one of the transistors Q ₁₁ and Q ₁₂ , whichever is conducting, lowers one bit line to the low level, The stored information is read to.

For example, if V ₁ > V ₂ , the word line W becomes high level, and the transistor Q ₁₂ is turned on via the transistor Q ₁₄ which is conductive.
Pulls bit line B ₂ low.

At the time of writing, the write circuit forcibly determines the state of the cell via the bit line and the transistors Q ₁₃ and Q ₁₄ (V ₁
> V ₂ or V ₁ <V ₂ ) to write.

Note that the main role of the transistors Q ₁₅ and Q ₁₆ is to replenish the charge lost from the node on the high level side of the nodes N ₁ or N ₂ at the time of reading or holding information. .

[Problems to be Solved by the Invention] In the memory cell as described above, the state of the cell must be arbitrarily set from the outside at the time of writing,
Further, at the time of reading, it must be possible to drive the bit line according to the state of the cell and read the stored information on the bit line. That is, the cell has a destructive operation at the time of writing and a non-destructive operation at the time of reading. When designing a cell, both of these fundamentally conflicting requirements must be met. Therefore, most important is the gain ratio and circuit symmetry of the transistors Q ₁₁ (or Q ₁₂ ) and Q ₁₃ (or Q ₁₄ ) that play a major role in operation.

Note that circuit symmetry means that transistor Q ₁₁ (or Q
₁₃ ) and Q ₁₂ (or Q ₁₄ ) have the same device parameters such as gain and threshold voltage.

Since the memory cell requires circuit symmetry as described above, the following problems occur in the case of a cell exposed to radiation such as an LSI used in outer space.

That is, the values of device parameters such as the threshold voltage of the MOS transistor and the gain constant change when the radiation is applied.

Moreover, the fluctuation value is significantly different depending on the bias condition,
It is known that the higher the gate voltage is in the case of an N-channel field effect transistor and the lower the gate voltage is in the case of a P-channel field effect transistor, the larger the fluctuation amount.

In the cell shown in FIG. 4, since the values of the voltages V ₁ and V ₂ are always different, the transistors Q ₁₁ and Q ₁₂ , Q ₁₃ and Q ₁₄ ,
The bias conditions for each pair of Q ₁₅ and Q ₁₆ are different.

Therefore, if the same information is held for a long period of time, that is, if the bias condition of the transistor does not change for a long period of time, the deterioration of the transistor under the bias condition with large fluctuation progresses and the fluctuation value of the device parameter changes. There is a problem that the circuit symmetry of the cell is broken, which causes the destruction of the stored information in the cell at the time of reading, the inability to write, the reduction of the noise margin at the time of standby, etc., which causes a malfunction.

The present invention has been made in order to solve the problems of the prior art as described above, and provides a control method of a storage device capable of suppressing deterioration of device parameters due to radiation and maintaining circuit symmetry for a long period of time. It is intended to be provided.

[Means for solving problems]

To achieve the above object, in the present invention, a positive signal line D provided between a cell array and an external circuit is provided in the middle of a pair of data lines consisting of a positive signal line D and its complementary signal line,
A semiconductor memory device provided with an information conversion circuit for switching between two types of electrical connections (D and D, and) or (D and, and D) according to an external control signal is used. A control step of repeatedly switching at times other than the normal access time, a control step of inverting the stored information of all cells in the cell array through the information conversion circuit at each switching time, and the external time at the normal access time The circuit is configured to perform a control step of always transmitting and receiving a signal of normal polarity via the information conversion circuit.

With the above-mentioned configuration, in the present invention,
By inverting the stored information in the cell at an appropriate cycle by an external control signal, the bias condition of the transistor can be prevented from being biased to one side for a long period of time, thus suppressing fluctuations in device parameters and circuit asymmetry. Is possible.

In addition, in another configuration of the present invention, as a semiconductor memory device to be used, in addition to the above configuration, inversion information writing including at least a latch circuit and a switch circuit which operate in response to second and third external control signals. And a circuit in which the data line is branched and connected to the input of the inversion information writing block and the output of the inversion information writing block is connected to the data line. A control step in which an external control signal is repeated to switch at a time other than a normal access, and the cell array through the inversion information writing block or the information conversion circuit and the inversion information writing block at each switching. Control step to invert the stored information of all the cells in the cell and the information change to the external circuit at the time of normal access. And configured to perform a control step of performing always exchange signals normal polarity through the circuit.

It is to be noted that the one in which the stored information is inverted only through the inversion information writing block corresponds to, for example, the embodiment of FIG. 3 described later, and the storage information is inverted through the information conversion circuit and the inversion information writing block. What is caused corresponds to, for example, the embodiment shown in FIG.

With the above configuration, when inverting the information already stored in the memory, it is not necessary to read out the information once, and it is possible to process everything inside the memory by giving an external control signal. Becomes

Example of Invention

FIG. 1 is a first embodiment of a semiconductor memory device used in the present invention.

In FIG. 1, 1 is a cell array, 2 is a row selection circuit, 3
Is a column selection circuit and multiplexer, 4 is a word line, 5
Is a bit line, 6 is an input / output circuit, and 7 is an external terminal.

Reference numeral 8 denotes a data bus connecting the row selection circuit 3 and the input / output circuit 6, which has a positive signal line D and a complementary signal line.

The above configuration is similar to that of a conventional static memory.

The present invention is different in that an information conversion circuit 9 is provided in the middle of the data bus 8.

In FIG. 1, the data bus between the information conversion circuit 9 and the input / output circuit 6 is shown as 8 ', its positive signal line is shown as D', and its complementary signal line is shown as'.

The above information conversion circuit 9 may be any one having a function of inverting the information passing through the data bus 8 according to an external control signal. In the embodiment of FIG. 1, using four transistors Q ₁ to Q _4, applying an external control signal to the terminal T ₅ and T _6, it is constituted thereby to perform switching of information.

That is, the external control signal φ ₁ is applied to the terminal T ₅ , and the terminal T ₆
Is supplied with an external control signal ₁ having a complementarity with φ ₁ .

When φ ₁ is at a high level (therefore, ₁ is a low level), the transistors Q ₁ and Q ₂ are conductive and Q ₃ and Q ₄ are non-conductive, so that terminals T ₁ and T ₃ , T ₂ and T ₄ , And thus the positive signal lines D and D'of the data bus and the complementary signal lines and 'are connected.

On the other hand, when the external control signal φ ₁ is at the low level, the transistors Q ₁ and Q ₂ are non-conductive and the transistors Q ₃ and Q ₄ are conductive.
The terminals T ₁ and T ₄ , T ₂ and T ₃ are connected, respectively, so that the data buses D, ', and D'are connected to replace the positive signal line and the complementary signal line, and the information is inverted. Will be.

In the above structure, the stored information of each cell in the cell array 1 is inverted by switching the external control signals φ ₁ and ₁ at an appropriate cycle.

Hereinafter, the above-mentioned stored information inversion operation will be described.

At the time of the stored information inversion operation, first, the already stored information is read, the information is inverted, and the original cell is written again.

For that purpose, the external control signal φ ₁ may be set to the low level when performing either one of the read operation and the write operation.

Then, the information is inverted by the switching operation of the information conversion circuit as described above.

Further, during the period in which the stored information is inverted, the external control signal φ
Keep ₁ at low level.

In this case, the information conversion circuit 9 writes the inverted information in the cell at the time of writing, and at the time of reading, the stored information of the cell is again inverted and then read out to the outside. Also, except that the level of the external control signal φ ₁ is different, there is no difference in reading and writing of the memory as seen from the outside.

As described above, in the embodiment shown in FIG. 1, the stored information in the cell is inverted at an appropriate cycle. Therefore, even if the stored information seen from the outside of the memory is not changed for a long period of time, the bias condition in the cell is inverted at every predetermined cycle, and only the same transistor is not left under bad conditions for a long time. , The degree of deterioration is averaged.

Therefore, as compared with the conventional storage device, the deterioration of the device parameter is suppressed and the circuit symmetry is better maintained.

It should be noted that the structure becomes more complicated than that of the conventional device due to the provision of the information conversion circuit 9, but a normal cell can be used as it is as a cell which is the largest element for determining the degree of integration. The degree of integration is almost the same as before.

Further, while the memory information of the cell is being rewritten, the memory cannot be accessed, but since the rewriting cycle can be long, no problem occurs in the actual operation.

Since the rewriting cycle of the stored information may be long, it is not always necessary to perform it during the operation period.

For example, the information may be rewritten by switching the external control signal when the power is turned on or when the already stored information is no longer needed.

In this way, the processing for the already written information becomes unnecessary and only the external control signal φ ₁ is switched, so that the operation becomes extremely simple.

Next, FIG. 2 is a second embodiment of the semiconductor memory device used in the present invention.

The embodiment shown in FIG. 2 is obtained by adding an inversion information writing block 10 to the embodiment shown in FIG.

As the inversion information writing block 10, for example, a circuit composed of a latch circuit 11, an amplifier 12 and a switch circuit 13 is used as shown in the figure, and a data bus 8'between the information conversion circuit 9 and the input / output circuit 6 is provided. Connect the input terminals T ₉ and T ₁₀ of the inversion information writing block 10 and connect the output terminals T ₇ and T ₈ thereof to the data bus 8 between the column selection circuit 3 and the information conversion circuit 9. Is configured.

Further, in the inversion information writing block 10, the input terminals T ₉ and T ₁₀ are connected to the input of the latch circuit 11, and the output of the latch circuit 11 is output via the amplifier 12 and the switch circuit 13 to the output terminals T ₇ and Connected to T ₈ .

Further, as the switch circuit 13, for example, a circuit composed of two transistors can be used as illustrated. This circuit has a function of turning on when the external control signal φ ₃ given from the terminal 12 is at high level and turning off when it is at low level.

Next, the operation will be described.

Similar to the normal read operation, the stored information of the selected cell is read by the positive signal line D and the complementary signal line of the data bus 8 and inverted by the information conversion circuit 9.

Then, the inverted information is taken into the latch circuit 11 in the inverted information writing block 10 according to the external control signal φ ₂ .

Next, when the external control signal φ _{3 is set} to the high level to make the switch circuit 13 conductive, the information held by the latch circuit 11 is amplified by the amplifier 12 and then sent to the data bus 8 via the switch circuit 13, This inverts the stored information in the cell.

This operation is performed for all the cells in the cell array 1 to invert the stored information of all the cells.

The external control signal φ _{3 is set} to the low level and the switch circuit 13 is made non-conductive except when the inversion information is written.

By configuring as described above, it is not necessary to read the information to the outside in order to invert the already stored information, and all the inversion storage of the information is processed inside the memory by giving the external control signal. Can be done.

Next, FIG. 3 is a diagram showing a third embodiment of the semiconductor memory device used in the present invention.

The embodiment shown in FIG. 3 is different from the embodiment shown in FIG. 2 in that the branch point from which the input of the inversion information writing block is taken out is changed.

That is, in the embodiment of FIG. 3, the input and output of the inverted information writing block are connected to the data bus 8 which connects the column selection circuit 3 and the information conversion circuit 9.
However, in this case, the input and output are connected so as to be reversed in the inverted information writing block 10.

That is, the positive signal line D of the data bus 8 is connected to the input terminal T ₉ of the inversion information writing block 10, the corresponding output is connected from the output terminal T ₇ to the complementary signal line of the data bus 8, and The complementary signal line of the data bus 8 is connected to the input terminal T ₁₀ of the inversion information writing block 10, and the signal corresponding thereto is connected to the positive signal line D of the data bus from the output terminal T ₈ . .

By connecting the amplified output of the positive signal to the complementary signal line of the data bus and the amplified output of the complementary signal to the positive signal line of the data bus as described above, the inverted write operation of the information signal is reversed. The operation can be performed only by the write block 10.

In this case, the information conversion circuit 9 can be arranged between the input branch point of the inverted information writing block 10 and the input / output circuit 6.

If the inversion information writing block 10 is provided for each bit line pair and the above concept is applied to each bit line, the information of cells (one column of cells) connected to one word line is inverted at once. Therefore, the stored information can be inverted more easily.

Further, in the embodiments of FIGS. 2 and 3, the amplifier 12 may not be provided as long as the state of the cell can be inverted only by the driving force of the latch circuit 11.

Further, in the above-described embodiments, the case where the present invention is applied to the memory cell is illustrated, but the peripheral circuits such as the sense amplifier, the address buffer, the clock generation circuit, etc. are also symmetrical as in the differential amplifier circuit. Since a circuit and a latch circuit having a typical structure are provided, the same problem as in the above memory cell occurs. Therefore, similar effects can be obtained by applying the method of the present invention to these circuits.

For example, if the information conversion circuits are inserted in the front and rear stages of the latch circuit and the information is inverted at an appropriate period to be latched, the device parameters are the same as in the above embodiment even if the information from the outside does not change. It is possible to suppress the deterioration of and improve the circuit symmetry.

〔The invention's effect〕

As described above, in the present invention, since the transistors constituting the memory device are not biased under a bad bias condition for a long period of time, deterioration of device parameters due to radiation is suppressed and circuit symmetry is reduced. Better kept.

In addition, since a normal cell can be used as it is as a cell, which is the largest factor for determining the integration degree, an excellent effect that the radiation resistance of the cell can be improved without lowering the integration degree. Is obtained.

[Brief description of drawings]

1 to 3 are schematic views of semiconductor memory devices used in the present invention, and FIG. 4 is a circuit diagram of a conventional CMOS memory cell. <Explanation of symbols> 8,8 ′ …… Data bus 9 …… Information conversion circuit 10 …… Inverted information writing block 11 …… Latch circuit 12 …… Amplifier 13 …… Switch circuit D, D ′ …… Positive signal line , '... Complementary signal line φ ₁ , ₁ , φ ₂ , φ ₃ ... External control signal

Claims (2)

[Claims] 1. A pair of data lines consisting of a positive signal line D and a complementary signal line provided between a cell array and an external circuit, provided in the middle of (D and D) or (D and). D) Control of switching between two types of electrical connection by using a semiconductor memory device provided with an information conversion circuit for switching in accordance with an external control signal and repeating the above external control signal at times other than during normal access Steps, a control step of inverting the stored information of all cells in the cell array via the information conversion circuit at each switching, and a constant access to the external circuit at the time of normal access via the information conversion circuit. A method of controlling a semiconductor memory device having radiation resistance characteristics, which comprises performing a control step of transmitting and receiving signals of normal polarity. 2. A pair of data lines consisting of a positive signal line D and its complementary signal line provided between a cell array and an external circuit, provided in the middle of (D and D) or (D and). At least an information conversion circuit for switching between the two types of electrical connections of D) according to the first external control signal, a latch circuit and a switch circuit that operate according to the second and third external control signals. A semiconductor memory device comprising: an inversion information writing block having the above; and a circuit in which the data line is connected to an input of the branched inversion information writing block, and an output of the inversion information writing block is connected to the data line. And a control step in which the external control signal is repeated to switch at a time other than a normal access time, and each time the switching is performed through the inversion information writing block or the information conversion circuit. The control step of inverting the stored information of all the cells in the cell array via the reversal information writing block, and the transmission / reception of a signal of normal polarity to the external circuit at the time of normal access via the information conversion circuit. And a method of controlling a semiconductor memory device having radiation resistance characteristics, characterized in that: