JPH0795537B2 - Method for manufacturing semiconductor device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device capable of forming an ion-implanted layer having few crystal defects.

2. Description of the Related Art As a method of forming an element on a semiconductor substrate of a VLSI, a method of implanting an impurity serving as a carrier source into the semiconductor substrate by an ion implantation method and activating by annealing to form a p-type layer or an n-type layer Is widely used because it has good controllability of impurity concentration and depth. However, the ion implantation method causes many crystal defects because the impurity ion particles are implanted into the semiconductor substrate with high energy of 10 keV to 500 keV. Therefore, heat treatment (annealing) at a high temperature of 1000 ° C. or higher is required in order to form an injection layer having good crystallinity. For example, formation of a source / drain region of an n-channel MOS LSI is performed by using Si (10
The arsenic (As) ions are applied to the (100) crystallographic orientation plane of the p-type Si substrate of 0-type p-type 10 to 20 Ω · cm with an acceleration energy of 40 ke.
V is formed at a dose of 5 × 10 ¹⁵ / cm ² . The activation after the implantation is carried out by an ordinary electric furnace (FA) annealing method at a temperature of 1000 ° C. for about 30 minutes. In this case, the junction depth of the injection layer is about 0.2 μm and the sheet resistance is about 4
It becomes 0Ω / □, and in this case, the electrical activation rate with respect to the injected amount of As atoms is as low as 60 to 70%. Also, there are many residual defects after the implantation layer is annealed.

Problems to be Solved by the Invention If the annealing temperature after ion implantation is performed at a high temperature, activation is improved and crystal defects are also reduced, but impurity diffusion from the implanted layer occurs, the junction depth becomes deep, and There are inconveniences such as an increase in capacitance and a decrease in effective gate length. If it is performed at a low temperature, the junction depth can be made shallow, but the activation is low and many crystal defects remain. Further miniaturization is progressing, and it is necessary to reduce the junction depth in the megabit dynamic random access memory (DRAM) process. As an example of this implementation method, in the method of using an ordinary electric furnace for annealing after ion implantation for a long time of about 20 to 30 minutes, the temperature must be set to a low temperature of 900 ° C to 800 ° C. However, at such low temperatures, the activation of implanted ions is about 30% at 900 ° C and about 25% at 800 ° C.
Compared with the usual activation rate of 60 to 70% at 000 ° C and 90% at 1100 ° C, it is very small and has many residual defects. Therefore, when an element is formed, leakage of current at this junction and deterioration of carrier lifetime become major problems.

Means for Solving the Problems A method for manufacturing a semiconductor device of the present invention is: an amorphous layer formed by ion implantation after ion implantation into a semiconductor substrate, recovery of implanted primary defects to a temperature not exceeding 1000 ° C. Characterized in that after performing the first heat treatment for single crystallizing, the second heat treatment is performed for 1 to 500 seconds at a temperature higher than the temperature in the first heat treatment and not exceeding 1050 ° C. .

Then, in the second heat treatment, for example, a lamp annealing method is used.

Action By this two-step annealing at low temperature for a long time and at high temperature for a short time, an injection layer with high crystallinity that suppresses impurity diffusion from the injection layer, has high activation, and reduces crystal defects in the injection layer is formed. be able to.

Example Regarding the annealing method of the ion-implanted layer according to the method of the present invention, the first example will be described with reference to an ion-implanted layer in which As ions are implanted on a Si substrate.
The process steps in the figure will be described.

In Step 1 of Fig. 1, p-type Si (100) with 20 to 20 Ω · cm
Using the substrate, next, in step 2, an ion implantation window is formed by a method of forming a selective oxide film. Then step 3
Then, the acceleration energy of As ions is 40 by the ion implantation method.
An injection amount of 5 × 10 ¹⁵ pieces / cm ² is performed at keV or 20 keV. Next, in step 4, as the first annealing, annealing was performed in an N ₂ gas at 1000 ° C. for 20 minutes in an electric furnace (FA). After this first anneal, the residual defects were measured using thermal wave signals. The results are plotted after FA in FIG. The heat wave signal intensity (TW unit) on the vertical axis is almost proportional to the amount of defects in the injection layer. In this measuring method, the integrated value of the amount of defects from the surface of the Si substrate to a depth of about 3 μm is measured. The measured value of the heat wave signal shows a much larger value for the sample injected at 40 keV than that for the sample injected at 20 keV, indicating that the amount of defects is large. Next step 5
Then, as the second annealing, the short-time annealing method (RT
A lamp annealing using a halogen lamp, which is one of A), was performed in N ₂ at a temperature of 1050 ° C. for 10 seconds. After the second annealing, residual defects were also measured by a heat wave signal.

The heat wave signal after the second annealing is shown in Fig. 2 [FA + RTA (I
I)], the heat wave signal value [FA] after the first annealing
Shows a significant decrease compared to. This indicates that the amount of defects in the injection layer was significantly reduced. This decrease in defect amount was also seen at acceleration energies of 40 keV and 20 keV. For comparison, the heat wave signal intensity when the second short-time annealing was performed at a temperature of 900 ° C. is shown in [FA + RTA (I)], but in this case, it showed an increase.

The junction depth of the As-implanted layer thus formed was 0.2 μm, which was the same for FA alone and FA + RTA (II). This indicates that the second annealing hardly causes diffusion of As from the injection layer even at high temperature because of the short time. For As diffusion, the second annealing time is 500
If the time is longer than the second, the annealing time is about the same as the annealing in the first electric furnace, so that the junction depth is significantly increased, which is not preferable for forming a shallow junction. Further, if it is shorter than 1 second, the annealing effect becomes poor, which is also not preferable.

EFFECTS OF THE INVENTION According to the method of the present invention, the first heat treatment is performed at a temperature for recovering the implanted primary defects and for single crystallizing the amorphous layer formed by ion implantation, and at a temperature not exceeding 1000 ° C. The second heat treatment is performed for 1 to 500 seconds at a temperature higher than that and not exceeding 1050 ° C, so that crystal defects in the ion-implanted layer can be significantly reduced and diffusion of impurities from the ion-implanted layer can be suppressed. Therefore, it is possible to form an impure diffusion layer having good crystallinity with a shallow junction.

[Brief description of drawings]

FIG. 1 is a step exploded view for explaining the process of annealing the ion-implanted layer by the method of the present invention, and FIG. 2 is after the first annealing by electric furnace annealing (FA) and by lamp annealing (RTA). It is a characteristic view of the heat wave signal intensity measured after the second annealing. 1 ... Si substrate preparation step, 2 ... Pattern formation step, 3 ... Ion implantation step, 4 ... First annealing step, 5 ... Second annealing step.

Claims (2)

[Claims] 1. After performing ion implantation on a semiconductor substrate, 10
The first heat treatment is performed for a period of time during which the implanted primary defects are recovered at a temperature not exceeding 00 ° C. and the amorphous layer formed by ion implantation becomes a single crystal, and thereafter, the temperature is higher than the temperature at the time of the first heat treatment. 1st second heat treatment at a temperature not exceeding ℃
A method for manufacturing a semiconductor device, which is performed for about 500 seconds. 2. A method of manufacturing a semiconductor device according to claim 1, wherein a lamp annealing method is used in the second heat treatment.