JPH0795590B2 - Semi-custom semiconductor integrated circuit design method - Google Patents
Semi-custom semiconductor integrated circuit design methodInfo
- Publication number
- JPH0795590B2 JPH0795590B2 JP63276468A JP27646888A JPH0795590B2 JP H0795590 B2 JPH0795590 B2 JP H0795590B2 JP 63276468 A JP63276468 A JP 63276468A JP 27646888 A JP27646888 A JP 27646888A JP H0795590 B2 JPH0795590 B2 JP H0795590B2
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- basic
- semiconductor integrated
- semi
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000000034 method Methods 0.000 title claims description 11
- 230000010354 integration Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 12
- 238000007796 conventional method Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多品種の半導体集積回路を同一の半導体基板
（下地）を用い、配線パターンを選択し、形成すること
により実現するセミカスタム半導体集積回路、特にアナ
ログ回路用のセミカスタム半導体集積回路の設計方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is a semi-custom semiconductor integrated circuit that realizes a wide variety of semiconductor integrated circuits by using the same semiconductor substrate (base) and selecting and forming a wiring pattern. The present invention relates to a method for designing a semi-custom semiconductor integrated circuit for a circuit, particularly an analog circuit.
従来、アナログ用のセミカスタム半導体集積回路では、
トランジスタ同様、抵抗素子、容量素子等の各々の基本
セルを複数個配置して形成した半導体基板（下地）をあ
らかじめ用意しておき、コンタクト形成工程以降の布線
設計及び配線工程のみ行なえばよいので、所定の仕様に
合った半導体集積回路を短納期で得ることができる。第
４図はセミカスタム半導体集積回路の下地のレイアウト
図で、半導体チップ１上には、トランジスタ基本セル2,
抵抗基本セル3,コンデンサ基本セル４が複数個配置され
ている。アナログ回路では、種々の抵抗値を有した抵抗
素子を構成する必要があるが、従来のセミカスタム半導
体集積回路の設計方法では、用いる抵抗マクロセルの種
類は一つであった。Conventionally, in semi-custom semiconductor integrated circuits for analog,
Similar to the transistor, it is sufficient to prepare in advance a semiconductor substrate (base) formed by arranging a plurality of respective basic cells such as a resistance element and a capacitance element, and only perform wiring design and wiring steps after the contact formation step. A semiconductor integrated circuit that meets predetermined specifications can be obtained in a short delivery time. FIG. 4 is a layout diagram of the base of a semi-custom semiconductor integrated circuit.
A plurality of resistance basic cells 3 and a plurality of capacitor basic cells 4 are arranged. In analog circuits, it is necessary to configure resistance elements having various resistance values, but in the conventional method of designing a semi-custom semiconductor integrated circuit, only one kind of resistance macro cell is used.
第５図は下地に形成されている抵抗基本セルを配線によ
り、直・並列接続することだけにより、所望の抵抗値を
実現する抵抗マクロセルの従来例を示すレイアウト図
で、第５図（ａ）は抵抗基本セル３にコンタクト領域６
−1,6−２でそれぞれAlの電極配線５に接続された抵抗
基本素子を２本直列つなぎ、抵抗基本素子の抵抗値の２
倍の抵抗値を有する抵抗マクロセルを構成した例を示
し、第５図（ｂ）は、同様に２本を並列につなぎ、抵抗
基本素子の抵抗値の２分の１抵抗値を有する抵抗マクロ
セルを構成した例を示したものである。FIG. 5 is a layout diagram showing a conventional example of a resistance macro cell that realizes a desired resistance value by simply connecting the resistance basic cells formed on the base by wiring in series / parallel. FIG. Is the resistance basic cell 3 and the contact area 6
-1 and 6-2 connect two resistance basic elements connected in series to the electrode wiring 5 of Al, respectively.
FIG. 5 (b) shows an example in which a resistance macro cell having a double resistance value is constructed. Similarly, two resistance macro cells are connected in parallel, and a resistance macro cell having a resistance value of ½ of the resistance value of the resistance basic element is shown. It shows an example of the configuration.
第６図は、下地に形成されている抵抗基本セルとのコン
タクトの位置を変えることだけにより、抵抗長（la,
lb）を変え、所定の抵抗値を実現する抵抗マクロセルの
従来例を示すレイアウト図である。但し、電極配線は便
宜上示していない。例えば、lb＝la/2とすると、第６図
（ｂ）に示す抵抗マクロセルの抵抗値は第６図（ａ）に
示す抵抗マクロセルの抵抗値の２分の１となる。FIG. 6 shows that only by changing the position of the contact with the basic resistance cell formed on the base, the resistance length (l a ,
FIG. 11 is a layout diagram showing a conventional example of a resistance macro cell that realizes a predetermined resistance value by changing l b ). However, the electrode wiring is not shown for convenience. For example, if l b = l a / 2, the resistance value of the resistance macro cell shown in FIG. 6 (b) becomes one half of the resistance value of the resistance macro cell shown in FIG. 6 (a).
このように従来のセミカスタム半導体集積回路の設計方
法では、抵抗長が一定の抵抗基本素子を直・並列接続し
てなる抵抗マクロセルを使用するやり方と、抵抗基本セ
ルと配線とのコンタクト位置により抵抗長の異なるもの
を実現する抵抗マクロセルを使用するやり方との２種類
があった。As described above, in the conventional method of designing a semi-custom semiconductor integrated circuit, the resistance macrocell is formed by connecting the resistance basic elements with a constant resistance length in series and parallel, and the resistance is changed by the contact position between the resistance basic cell and the wiring. There are two types, a method of using a resistive macro cell that realizes different lengths.
しかしながら、上述した従来のアナログ回路用のセミカ
スタム半導体集積回路の設計方法では、所定の抵抗値を
有する抵抗マクロセルを一種類しか使用しないので、 （１）基本抵抗素子を配線により直・並列接続するやり
方においては、抵抗値設定の分解能に限界があり、低抵
抗値を実現するためには、多くの基本抵抗素子の並列接
続を行なうことになり、多くの抵抗基本セルを使用する
ので、高集積度を実現し難い。However, in the above-described conventional method for designing a semi-custom semiconductor integrated circuit for analog circuits, only one type of resistance macro cell having a predetermined resistance value is used, and therefore (1) basic resistance elements are connected in series / parallel by wiring. In the method, there is a limit to the resolution of resistance value setting, and in order to realize a low resistance value, many basic resistance elements are connected in parallel, and since many resistance basic cells are used, high integration is required. It is difficult to achieve the degree.
（２）コンタクト位置により抵抗長を変えるやり方にお
いては、例えば、抵抗分圧による電圧設定回路または、
抵抗値の比を用いた定電流設定回路において、抵抗の相
対精度が要求されるときでも、各抵抗マクロセルの抵抗
長、コンタクト抵抗の変動により抵抗マクロセル間の抵
抗比が変動してしまうので精度をよくするのが難しい。(2) In the method of changing the resistance length depending on the contact position, for example, a voltage setting circuit by resistance division or
In a constant current setting circuit that uses the ratio of resistance values, even when relative accuracy of resistance is required, the resistance ratio between resistance macrocells varies due to fluctuations in the resistance length of each resistance macrocell and contact resistance. It's hard to do well.
という欠点がある。There is a drawback that.
従って、発明の目的は、抵抗値設定の自由度があり、か
つ、集積度を改善し、さらに相対精度の要求をも満足で
きるセミカスタム半導体集積回路の設計方法を提供する
ことにある。Therefore, an object of the present invention is to provide a method of designing a semi-custom semiconductor integrated circuit which has a degree of freedom in setting a resistance value, improves the degree of integration, and can satisfy the requirement of relative accuracy.
本発明は、下地の抵抗基本セルに一対の電極配線を設け
て所定の抵抗素子を実現するセミカスタム半導体集積回
路の設計方法において、抵抗長が一定の基本抵抗素子に
組合せた第１の抵抗マクロセル及び前記第１の抵抗マク
ロセルにおける前記基本抵抗素子の並列回路の代りに前
記抵抗長が前記基本抵抗素子より小さい抵抗素子を用い
る第２の抵抗マクロセルを必要な相対精度に応じてそれ
ぞれ配置するというものである。The present invention relates to a method of designing a semi-custom semiconductor integrated circuit in which a pair of electrode wirings are provided in a base resistance basic cell to realize a predetermined resistance element, and a first resistance macrocell combined with a basic resistance element having a constant resistance length. And, instead of the parallel circuit of the basic resistance elements in the first resistance macrocell, second resistance macrocells using resistance elements whose resistance length is smaller than the basic resistance element are arranged according to the required relative accuracy. Is.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例を説明するためのレイア
ウト図で、第１図（ａ）は1kΩの抵抗基本セル103、第
１図（ｂ）は２つの抵抗基本セル103を電極配線105によ
り並列に接続した500Ωの第１の抵抗マクロセル、第１
図（ｃ）はコンタクト工程において基本抵抗素子の抵抗
長の1/2の抵抗長となるようにコンタクト領域106−1,10
6−２間の距離を小さくした500Ωの第２の抵抗マクロセ
ルを示す。FIG. 1 is a layout diagram for explaining the first embodiment of the present invention. FIG. 1 (a) shows a 1kΩ resistance basic cell 103, and FIG. 1 (b) shows two resistance basic cells 103 as electrodes. 500Ω first resistive macrocell connected in parallel by wiring 105, first
In the contact process, the contact regions 106-1 and 10 are provided so that the resistance length is half the resistance length of the basic resistance element in the contact step.
Figure 6 shows a 500 Ohm second resistive macrocell with a reduced distance between 6-2.
第２図（ａ）に示す電圧分割回路は、アナログ集積回路
に多く使用されるが、精度のよい分割を行うには抵抗の
相対精度が要求されるので、第１の抵抗マクロセルを使
用する。R1＝1kΩとして基本抵抗素子を、R2＝500Ωと
して基本抵抗素子を２個並列に接続した第１の抵抗マク
ロセルを使用すればよいのである。The voltage divider circuit shown in FIG. 2 (a) is often used in analog integrated circuits, but the first resistor macrocell is used because relative precision of resistors is required to perform accurate division. It suffices to use a basic resistance element with R 1 = 1 kΩ and a first resistance macrocell with two basic resistance elements connected in parallel with R 2 = 500 Ω.
第２図（ｂ）に示すエミッタホロワ回路では、抵抗R
3（＝500Ω）の精度はそれほど問題とならないので第２
のマクロセルを使用すればよい。In the emitter follower circuit shown in FIG. 2 (b), the resistor R
Since the accuracy of 3 (= 500Ω) does not matter so much,
You can use the macro cell.
第３図は本発明の第２の実施例を説明するためのレイア
ウト図である。半導体基板上に、拡散層からなる抵抗基
本セル203を形成したものを下地とし、下地に形成され
た抵抗基本セルの形状、コンタクト領域206の位置を変
えることなく、布線工程と同時にそれらの抵抗値を変更
するために、拡散層に選択的に不純物をイオン注入して
低抵抗領域207,207′を形成する。第３図（ａ）は1kΩ
の抵抗基本セルを示し、第３図（ａ）は電極配線205に
より基本抵抗素子を２本並列に接続した500Ωの第１の
抵抗マクロセルを示し、第３図（ｂ）は基本抵抗素子の
抵抗長の1/2の抵抗長となるように低抵抗領域207′を選
択的に加えた500Ωの第２の抵抗マクロセルを示す。FIG. 3 is a layout diagram for explaining the second embodiment of the present invention. A semiconductor substrate on which a resistance basic cell 203 formed of a diffusion layer is formed is used as a base, and the resistance basic cell formed on the base is not changed in shape and the position of the contact region 206 without changing the resistance of the wiring process and the resistance of the resistance basic cell. In order to change the value, impurities are selectively ion-implanted into the diffusion layer to form low resistance regions 207 and 207 '. Figure 3 (a) shows 1kΩ
FIG. 3 (a) shows a 500Ω first resistance macro cell in which two basic resistance elements are connected in parallel by electrode wiring 205, and FIG. 3 (b) shows the resistance of the basic resistance element. A second resistance macrocell of 500 Ω is shown in which a low resistance region 207 'is selectively added so that the resistance length is ½ of the length.
以上の実施例において、第２の抵抗マクロセルの抵抗長
は基本抵抗素子の1/2としたが、1/2,1/3,1/4としてもよ
いのである。In the above embodiments, the resistance length of the second resistance macro cell is 1/2 of the basic resistance element, but it may be 1/2, 1/3, 1/4.
以上、説明したとおり、本発明をよれば必要な回路特性
に適した抵抗素子のマクロセルを同一配線設計上で選択
することにより、抵抗値設定の自由度があり、かつ素子
使用数の少ない抵抗マクロセルの使用と、基本抵抗素子
を直並列接続することにより、他の抵抗マクロセルとの
相対精度の高い抵抗マクロセルの使用とが可能であり、
各回路内での抵抗素子の使用条件に応じてマクロセルを
選択し、抵抗基本セル数の削減と抵抗の相対精度要求へ
の対応が同時に計れるという効果がある。As described above, according to the present invention, by selecting a macro cell of a resistance element suitable for necessary circuit characteristics on the same wiring design, there is a degree of freedom in resistance value setting and a resistance macro cell with a small number of elements used. It is possible to use a resistance macro cell with high relative accuracy to other resistance macro cells by connecting the basic resistance element in series and parallel,
The macro cell is selected according to the usage condition of the resistance element in each circuit, and it is possible to simultaneously reduce the number of basic resistance cells and meet the relative accuracy requirement of resistance.
第１図（ａ），（ｂ）及び（ｃ）はそれぞれ本発明の第
１の実施例を説明するための抵抗基本セル、第１の抵抗
マクロセル及び第２の抵抗マクロセルのレイアウト図、
第２図（ａ）は電圧分割回路の回路図、第２図（ｂ）は
エミッタホロワ回路の回路図、第３図（ａ），（ｂ）及
び（ｃ）はそれぞれ本発明の第２の実施例を説明するた
めの抵抗基本セル、第１の抵抗マクロセル及び第２の抵
抗マクロセルのレイアウト図、第４図はセミカスタム半
導体集積回路の下地のレイアウト図、第５図（ａ）及び
（ｂ）はそれぞれ基本抵抗素子の直列接続した抵抗マク
ロセル及び並列接続した抵抗マクロセルのレイアウト
図、第６図（ａ）及び（ｂ）はそれぞれ基本抵抗素子及
びコンタクト領域間の距離を基本抵抗素子より短くした
抵抗マクロセルのレイアウト図である。 １……半導体チップ、２……トランジスタ基本セル、3,
103,203……抵抗基本セル、４……コンデンサ基本セ
ル、5,105,205……電極配線、6,6−1,6−2,6′−1,6′
−2,106,106−1,106−2,206……コンタクト領域、207,2
07′……低抵抗領域。1 (a), (b) and (c) are layout diagrams of a resistance basic cell, a first resistance macro cell and a second resistance macro cell for explaining a first embodiment of the present invention, respectively.
2 (a) is a circuit diagram of a voltage dividing circuit, FIG. 2 (b) is a circuit diagram of an emitter follower circuit, and FIGS. 3 (a), (b) and (c) are the second embodiment of the present invention. A layout diagram of a resistance basic cell, a first resistance macro cell and a second resistance macro cell for explaining an example, FIG. 4 is a layout diagram of a base of a semi-custom semiconductor integrated circuit, and FIGS. 5 (a) and 5 (b). 6A and 6B are layout diagrams of a resistance macrocell in which basic resistance elements are connected in series and a resistance macrocell in which parallel connection is performed, and FIGS. 6A and 6B are resistances in which the distance between the basic resistance element and the contact region is shorter than that of the basic resistance element. It is a layout diagram of a macro cell. 1 ... Semiconductor chip, 2 ... Transistor basic cell, 3,
103,203 ... Resistance basic cell, 4 ... Capacitor basic cell, 5,105,205 ... Electrode wiring, 6,6-1,6-2,6'-1,6 '
-2,106,106-1,106-2,206 ... Contact area, 207,2
07 '... Low resistance region.
Claims (1)
計された抵抗基本セルから必要個数を選んで所望の抵抗
値の抵抗マクロセルを構成するセミカスタム半導体集積
回路の設計方法において、前記抵抗基本セルの両端部に
一対の電極配線を接続してなる第１の抵抗値の基本抵抗
素子より低抵抗の抵抗マクロセルを複数個使用する際
に、必要な相対精度に応じて、複数の前記基本抵抗素子
を並列接続したものと前記抵抗基本セルに、少なくとも
２の正整数をＮとして、前記第１の抵抗値のＮ分の１の
第２の抵抗値となるように一対の電極配線を設けたもの
とを使い分けそれによって相対精度と集積度の双方を確
保することを特徴とするセミカスタム半導体集積回路の
設計方法。1. A method for designing a semi-custom semiconductor integrated circuit, wherein a required number is selected from a plurality of resistor basic cells designed in advance to have the same size, and a resistor macrocell having a desired resistance value is formed. When a plurality of resistance macrocells having a resistance lower than that of the basic resistance element having the first resistance value, which is formed by connecting a pair of electrode wirings to both ends of the basic cell, are used, a plurality of the basic macrocells are provided depending on relative accuracy required A pair of electrode wirings are provided in the resistance basic cell in which the resistance elements are connected in parallel and the resistance basic cell has a second resistance value of 1 / N of the first resistance value, where N is at least a positive integer. A method for designing a semi-custom semiconductor integrated circuit characterized in that both the relative accuracy and the degree of integration are ensured by selectively using the ones.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63276468A JPH0795590B2 (en) | 1988-10-31 | 1988-10-31 | Semi-custom semiconductor integrated circuit design method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63276468A JPH0795590B2 (en) | 1988-10-31 | 1988-10-31 | Semi-custom semiconductor integrated circuit design method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02122545A JPH02122545A (en) | 1990-05-10 |
| JPH0795590B2 true JPH0795590B2 (en) | 1995-10-11 |
Family
ID=17569870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63276468A Expired - Fee Related JPH0795590B2 (en) | 1988-10-31 | 1988-10-31 | Semi-custom semiconductor integrated circuit design method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0795590B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0496351A (en) * | 1990-08-13 | 1992-03-27 | Matsushita Electron Corp | Semiconductor device and manufacture thereof |
| JP3006804B2 (en) * | 1991-07-31 | 2000-02-07 | 日本電気株式会社 | Gate array type semiconductor integrated circuit device and clock skew adjustment method for clock driver thereof |
| JP2792280B2 (en) * | 1991-08-30 | 1998-09-03 | 日本電気株式会社 | Master slice type prescaler circuit |
| JPH06216353A (en) * | 1993-01-14 | 1994-08-05 | Nippon Telegr & Teleph Corp <Ntt> | Basic cell of ECL circuit and method of forming the same |
| JP6284295B2 (en) * | 2012-09-14 | 2018-02-28 | エイブリック株式会社 | Voltage divider circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58112343A (en) * | 1981-12-26 | 1983-07-04 | Olympus Optical Co Ltd | Semiconductor and manufacture thereof |
| JPS6031263A (en) * | 1983-08-01 | 1985-02-18 | Nec Corp | Semiconductor integrated circuit device |
| JPS62134961A (en) * | 1985-12-09 | 1987-06-18 | Fuji Electric Co Ltd | Semiconductor integrated circuit device |
-
1988
- 1988-10-31 JP JP63276468A patent/JPH0795590B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02122545A (en) | 1990-05-10 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |