JPH0795594B2 - Semiconductor switching element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a semiconductor switching element having an anode short structure, wherein a buffer layer having a higher impurity concentration than the base layer is provided between the anode short structure and the base layer. By sandwiching the anode short distance d of the anode short structure to about twice or more the carrier diffusion length L (d <2L), the normal withstand voltage can be easily obtained and the rise of the on-voltage can be suppressed. It also enables high-speed switching.

[Industrial application field]

The present invention relates to a semiconductor switching element including various thyristors such as SI (electrostatic induction) thyristors and GTOs, and more particularly to improvement of an anode short structure thereof.

[Conventional technology]

Some of the semiconductor switching elements as described above incorporate a so-called anode short structure for the purpose of shortening the turn-off time and reducing switching loss. As an example, FIG. 5 shows a schematic sectional structure of a conventional planar type SI thyristor.

The SI thyristor shown in the same figure is a so-called buried type in which a gate 2 made of ap ^{+ type} semiconductor layer is embedded in a base layer 1 made of an n ^{− type} semiconductor layer, and a cathode 3 made of an n ^{+ type} semiconductor layer is formed thereon. It has a gate structure. In addition, gate 2
Although only a part of it is shown, a large number of p ⁺ regions are also embedded at a predetermined interval in parallel with the surface of the figure between the two adjacent regions (p ⁺ regions) shown in the figure. , Those
A channel (portion indicated by a broken line) is formed in the n ^- region sandwiched between the p ⁺ regions. Further, a gate electrode 5 is formed on the gate 2 via a contact recess 4 and a cathode electrode 6 is formed on the cathode 3.

On the other hand, the opposite surface of the base layer 1, disposed alternately an anode short regions 8 of the anode (anode region) 7 and the n ⁺ -type semiconductor layer made of p ⁺ -type semiconductor layer on the anode electrode 9 It has an anode short structure. Here, the short-circuit rate (width of the anode short-circuit area / width of the anode 7) is set to, for example, about 20 to 30%, and the anode short-circuit interval (distance between two adjacent anode short-circuit areas 8) d is several hundred μm. It has become a degree.

In such an anode short structure, the potential for electrons is lower in the anode short region (n ⁺ region) 8 than in the anode (p ⁺ region) 7. For this reason,
Turn-off, electrons came flowing at drift velocity V _d to the anode 7 side of the base layer 1 from the cathode 3 side, along both surface diffusion rate V _K of the anode 7, as shown in FIG. 5 ( «
After moving at V _d ), it can flow into the anode electrode 9 through the anode short region 8. Therefore, the turn-off time can be greatly shortened as compared with the case without the anode short structure.

[Problems to be solved by the invention]

In the conventional SI thyristor described above, when a reverse bias is applied between the gate and anode (between G and A), the depletion layer spreads toward the anode side in the base layer 1 having a low impurity concentration, and the final Specifically, when the depletion layer reaches the anode 7, a short circuit occurs between the gate and anode, and so-called punch through occurs. Therefore, in order to obtain a normal withstand voltage, it is necessary to make the base layer 1 thick so that the depletion layer does not reach the anode 7. From this, the conventional thickness t of the base layer 1 is, for example,
It is as thick as 350-400 μm.

However, if the base layer 1 is thick in this way, the carrier transit time at turn-on and turn-off becomes long, and despite the provision of the anode short structure,
There is a problem that the switching speed becomes slow. Furthermore,
In the on-state, the base layer 1 can be considered as a kind of conductor, so that if the base layer 1 is thick, the resistance increases by the thickness of the base layer 1 and thus the on-voltage increases. Such a problem similarly occurs in various semiconductor switching elements other than SI thyristors.

In view of the above problems, it is an object of the present invention to provide a semiconductor switching element that can easily obtain a normal operating breakdown voltage and that enables high-speed switching without increasing the on-voltage.

[Means for solving problems]

A semiconductor switching element according to the present invention includes an n-type semiconductor layer (for example, an n ⁻ layer) having a low impurity concentration and a base layer formed between the base layer and an anode short structure below the base layer. A buffer layer made of a semiconductor layer (for example, n layer) having a higher impurity concentration is provided, and the anode short distance d in the anode short structure is approximately twice the carrier diffusion length L in the base layer or the buffer layer. Is equal to or less than (d2L).

[Action]

In the present invention, since the buffer layer having an impurity concentration higher than that of the base layer exists between the base layer and the anode region, the expansion of the depletion layer in the base layer toward the anode side does not occur after reaching the buffer layer. Hardly progresses. That is, the expansion of the depletion layer can be suppressed by the buffer layer. From this, to obtain the same breakdown voltage as before,
The base layer can be made extremely thin.

When the base layer is thin in this way, carrier transit time at turn-on and turn-off is shortened. Moreover, d
Since the width of the anode region is very narrow due to the 2L, most of the carriers (electrons) flowing at the drift velocity V _d from the cathode side at turn-off do not reach the anode region, and the velocity remains almost unchanged. Then, it is quickly extracted to the anode electrode through the anode short region. That is, the turn-off time is further shortened.

Further, in the on-state, since the base layer is thin, the resistance of the base layer is correspondingly reduced, so that the on-voltage can be suppressed low.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional perspective view showing the structure of the main part of a planar type SI thyristor which is an embodiment of the present invention, and FIG. 2 is a cross-sectional view schematically showing it.

The SI thyristor shown in the figure has a buried gate structure similar to that shown in FIG. 5, that is, a base layer 1 made of an n ^{− type} semiconductor layer is buried with a gate 2 made of ap ^{+ type} semiconductor layer, and It has a structure in which a cathode 3 made of an n ^{+ type} semiconductor layer is formed on the top. According to this structure, a plurality of p ⁺ buried gates are formed between the adjacent p ⁺ regions appearing in FIG. 2 in the gate 2 as shown in FIG.
In the meantime, channel 10 is created. Further, the gate electrode 5 is formed on the gate 2 through the contact recess 4 and the cathode electrode 6 is formed on the cathode 3.

On the other hand, on the opposite side of the base layer 1, an anode short is formed via a buffer layer 11 made of an n-type semiconductor layer having a higher impurity concentration (for example, about 1 × 10 ¹⁴ to 10 ¹⁸ / cm ³ ) than the base layer 1. The structure is provided. This anode short structure is
Anode (anode region) 12 consisting of p ^{+ type} semiconductor layer and n ⁺
And the anode short region 13 made of a semiconductor layer with an anode short distance d of about 2 of the carrier diffusion length L.
They are alternately arranged on the anode electrode 9 so as to be twice or less (for example, d = 33 to 38 μm 2 L). If the carrier diffusion coefficient is D and the carrier lifetime is τ, the diffusion length L is It is represented by. Here, the depths of the anode 17 and the anode short region 18 are, for example, 15 μm and 3 μ, respectively.
In addition to setting m, the short-circuit rate is set to about 20 to 30% as in the conventional case. The thickness of the buffer layer 11 (the thickness from the upper surface of the buffer layer 11 to the upper end of the anode 12) t ₁ is set to, for example, about ₁₀ to 15 μm, and the thickness of the base layer 1 and the buffer layer 11 is added. t ₂ is, for example, 250μ
Set it thin to about m.

Next, the third step of manufacturing the SI thyristor having the above configuration
A description will be given with reference to FIGS. However, here
It is assumed that the above-described gate (buried gate) 2, the anode 12 and the anode short region 13 are formed so as to extend in a direction parallel to each other.

First, as shown in FIG. 3A, impurities such as phosphorus (P) are added from the lower surface of the n ⁻ substrate 20 such as Si having a thickness of about 250 μm.
By diffusing up to about 25 to 30 μm, an n region 21 to be a buffer layer is formed. Subsequently, impurities such as boron (B) are diffused from the upper and lower surfaces through a mask to form a p ⁺ region which will become a gate as shown in FIG. 3 (b).
22 and ap ⁺ region 23 to be an anode are simultaneously formed. At this time, for example, d = 33, so that the interval d between the adjacent p ⁺ regions 23 (that is, the anode short interval) d is approximately 2L (L is the carrier diffusion length) or less.
The thickness is about 38 μm and the depth is about 15 μm. Then, as shown in FIG. 3 (c), the p ⁺ region 22
On substrate 20, n ^{- -} n formed of a -Si like it is epitaxially grown, n ^{- -} the same n and substrate 20 to form a layer 24. Further, as shown in FIG. 3D, by diffusing impurities such as phosphorus (P) on the upper surface of the n ⁻ layer 24 uniformly and on the lower surface of the n region 21 through a mask, forming an n ⁺ region 26 serving as the cathode to become n ⁺ region 25 and the anode short regions. At this time, the n ⁺ region 26 is to be arranged alternately and p ⁺ region 23, and the depth of about 3 [mu] m, also n ⁺
The width ratio (short-circuit rate) of the region 26 and the p ⁺ region 23 is set to a predetermined value (for example, 20 to 30%).

Then, as shown in FIG. 3 (e), the n ⁺ region 25 and the n ⁻ layer are formed.
Becomes a gate by selectively etching 24
A contact recess 4 is formed on the peripheral region of the P ⁺ region 22. Subsequently, as shown in FIG. 3 (f), impurities such as boron (B) are further diffused in order to obtain ohmic contact with the surface portion of the p ⁺ region 22 exposed in the recess 4 (hatched portion). . Then, p ⁺ region 22, n ⁺ region 25, and p ⁺ region 24
As shown in FIG. 3 (g), a gate electrode 5, a cathode electrode 6, and an anode electrode 9 made of Al or the like are formed on the n ⁺ region 26 by vapor deposition or sputtering. N ⁻ substrate 20, p ⁺ region 22, n ⁺ region 25, n region thus obtained
21, p ⁺ regions 23, and n ⁺ regions 26 correspond to the base layer 1, gate 2, cathode 3, buffer layer 11, anode 12, and anode short region 13 shown in FIGS. 1 and 2, respectively. Finally, as shown in FIG. 3 (h), the surface of the electrodes 5 and 6 is covered with a passivation film 27 of SiO ₂ or the like, leaving the bonding pad regions.

Next, the main operation of the SI thyristor of the present embodiment, particularly the characteristic operation of the buffer layer 11 and the anode short structure, will be described below with reference to FIG.

In the SI thyristor of this example, when a reverse bias was applied between the gate and the anode, the base layer (n ⁻ layer)
A depletion layer spreads in 1 toward the anode side. However, since the buffer layer (n layer) 11 having a higher impurity concentration than the base layer 1 exists on the anode 12, the spread of the depletion layer hardly progresses after reaching the buffer layer 11. That is, the buffer layer 11 suppresses the expansion of the depletion layer. Therefore, the thickness of the base layer 1 can be made extremely thin in order to obtain the same withstand voltage (gate-anode breakdown voltage) as in the conventional case. Therefore, as described above, the thickness t ₂ obtained by adding the buffer layer 11 to the base layer 1 can be reduced. Can be thinned to about 250 μm (the thickness t of the conventional base layer 1 shown in FIG. 5 is as thick as 350 to 400 μm).

If the base layer 1 can be made thin in this way, the carrier transit time at turn-on and turn-off can be shortened, and thus the switching speed can be considerably increased. At the same time, in the on-state, the resistance of the base layer 1 becomes small, so that the on-voltage can be kept low.

Further, the turn-off time can be further shortened by the anode short structure of this embodiment. That is, the anode short region 13 that is the n ⁺ region has a lower potential for electrons than the anode 12 that is the p ⁺ region, and thus electrons are likely to accumulate. Moreover, the width (area) of the anode 12 is extremely narrowed by making the anode short distance d approximately twice or less than the electron diffusion length L. From these, at the time of turn-off, the drift velocity V _d from the cathode 3 side via the channel 10
Most of the electrons transferred in the anode (p ⁺ region) 12
The anode short-circuit region (n ⁺ region) 13 is reached at almost the same speed without reaching the above temperature, and the anode short-circuit region (n ⁺ region) 13 is quickly extracted from here. Note that some of the electrons that have moved from the cathode 3 side reach the vicinity of the center of the anode 12, but even with such electrons, by setting d2L, they reach the anode short region 18. The distance that must be traveled at the diffusion speed V _k is
It is a very small distance that is less than. In this way, the electrons do not stay on the front surface of the anode for a long time as in the conventional case, and most of the electrons are withdrawn without reaching the anode 12, so that the turn-off time is significantly shortened.

Also, in the above anode short structure, d2L was used,
By doing so, the short-circuit rate does not change, that is, since the total area of the anode 12 on the anode electrode 9 remains constant, the amount of holes injected from the anode side in the ON state is higher than that of the conventional one. There is no worry that it will decrease. For these reasons, the on-voltage does not increase due to the anode short structure according to the present embodiment, but rather the on-voltage can be lowered because the base layer can be thinned as described above.

Note that the present invention is not limited to SI thyristors, but GTO (Gate Turn
-Off Thyristor), IGBT (Instulated Gate Bipolar Tr
ansistor: product name), GATT (Gate Associated Turn-Off)
Thyristor (trade name), or general thyristors, etc., can be applied to various switching elements having an anode short structure. For example, a fourth example in which an anode short structure similar to that in the above embodiment is applied to a general GTO having an npnp structure
Shown in the figure. Specifically, the base (n ⁻ layer) 30, the gate (p
Layer) 31, cathode (n ⁺ region) 32, gate electrode 33, and cathode electrode 34 on the anode side of the GTO composed of the anode electrode 35 via the buffer layer (n layer) 36 and the anode (p ⁺ region) 37. And the anode short region (n ⁺ region) 38 d
The anode short structure is formed by alternately arranging so as to be 2L. Even in the GTO configured in this way, due to the same operation as described above, the normal operating withstand voltage can be easily obtained, and the switching speed can be remarkably increased without increasing the on-voltage.

Further, the anode short region is not limited to the n ⁺ region, but may be the n ⁻ or n region. The relationship between the depths (thicknesses) of the anode and the anode short region is also arbitrary, and the numerical values shown in the above embodiments are merely examples.
Also, the thickness of the buffer layer is only an example in the numerical values shown in the above embodiment.

Further, in the embodiment shown in FIG. 1, the forming direction of the anode 12 and the anode short region region 13 is set to be vertical to the forming method of the gate (buried gate) 2. However, as shown in FIG. You may form so that it may become parallel to each other. Also, in the manufacturing process, ion implantation or the like may be used instead of the impurity diffusion as described above.

Further, particularly in the SI thyristor, the anode region and the anode short region may be alternately arranged only at the position below the cathode region, and only the anode region may be uniformly arranged at the other positions. Furthermore, the anode short region may be provided only at a position below the channel between the gates. Considering that at the time of turn-off, electrons flow from the cathode side almost directly below through the channel, even with such a configuration, the action of extracting electrons remains unchanged.
On the other hand, since the effective area of the anode is further increased, the on-voltage can be suppressed to a low level, so that the effects more than those of the above-described embodiment can be expected.

It is needless to say that the present invention can be applied to a semiconductor switching element having both n and p channels.

〔The invention's effect〕

As described above, according to the present invention, by providing the buffer layer, it is possible to easily obtain a normal withstand voltage while keeping the base layer thin. Moreover, by making the base layer thin in this way, the turn-on and turn-off times can be shortened, the switching speed can be significantly increased, and the resistance of the base layer in the on-state can be reduced to keep the on-voltage low. You can Moreover, the turn-off time can be further shortened by setting d2L in the anode short structure, so that the on-voltage is not increased.

[Brief description of drawings]

FIG. 1 is a cross-sectional perspective view showing the structure of the main part of an embodiment of the present invention (in the case of SI thyristor), FIG. 2 is a schematic cross-sectional view showing the schematic structure of the same embodiment, and FIGS. h) is a manufacturing process diagram of the SI thyristor of the same embodiment, FIG. 4 is a schematic cross-sectional view showing a schematic configuration of another embodiment (in the case of GTO) of the present invention, and FIG. 5 is a schematic configuration of a conventional SI thyristor. It is a schematic cross-sectional view showing. 1 ... Base layer, 9 ... Anode electrode, 11 ... Buffer layer, 12 ... Anode (anode region), 13 ... Anode short region, 30 ... Base layer, 35 ... Anode electrode, 36 ... Buffer Layer, 37 ... Anode (anode area), 38 ... Anode short area.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Naoshige Tamamushi Kawauchi, Sendai City, Miyagi Prefecture (no address) Semiconductor Research Promotion Foundation (56) References JP-A-51-86982 (JP, A) JP-A-55 -146968 (JP, A) JP-A-54-149480 (JP, A) JP-A-50-147290 (JP, A) JP-B-62-19079 (JP, B2)

Claims (4)

[Claims] 1. An anode short circuit in which a p-type anode region and an n-type anode short region are alternately arranged below a base layer made of an n-type semiconductor layer having a low impurity concentration and above an anode electrode. In the semiconductor switching element having a structure, a buffer layer made of a semiconductor layer having the same n-type as the base layer and a higher impurity concentration than the base layer is provided between the base layer and the anode short structure. At the same time, the semiconductor switching element is characterized in that an anode short interval of the anode short structure is set to be approximately twice or less than a diffusion length of carriers in the base layer or the buffer layer. 2. The semiconductor switching element according to claim 1, wherein the thickness of the anode short region is thinner than the thickness of the anode region. 3. The semiconductor switching element according to claim 1, wherein the anode short structure is provided only below the cathode region, and only the anode region is provided except below the cathode region. 4. The semiconductor switching device according to claim 3, wherein the anode short region is provided below the cathode region and only below a channel formed between the gates.