JPH0795757B2 - Phase-locked carrier recovery circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention mainly relates to QPSK (Qu Qu for high-speed data communication, which is used in ground microwave communication devices and ground stations for satellite communication.
adrature Phase Shift Keying) The present invention relates to a phase recovery circuit (Phase Locked Loop: abbreviated as PLL) widely used in carrier recovery circuits of modulation / demodulation devices and various synchronization devices.

(Prior Art) FIG. 3 shows the basics of a conventional phase locked loop (PLL). 1
Is a voltage controlled oscillator (hereinafter referred to as VCO), 14 is a loop filter, and 12 is a phase comparator.

One of the typical applications of the PLL is a carrier recovery circuit of a QPSK demodulator, and its basic diagram is shown in FIG. Reference numerals 15 and 16 are quadruplers. 3 and 4 are frequency conversion mixers, 2'is a π / 2 phase shifter, and 5'and 6'are low-pass filters (LPF). LPF
The outputs 5'and 6'are output to the data reproducing circuit.

The quadrupler 15 regenerates the carrier at the quadruple frequency. The other operation is the same as the normal PLL.

(Problems to be Solved by the Invention) The biggest drawback of the conventional PLL is that the pull-in characteristic is not very good. Especially for the input signal like QPSK demodulator
When the SN ratio is low, the equivalent noise bandwidth (B _L ) of the PLL must be sufficiently narrowed compared to the data rate in order to improve the SN ratio of the reproduced carrier, which causes a poor pull-in characteristic. It becomes a very big problem.

Also, since the SN ratio of the reproduction carrier deteriorates by 6 dB by quadruple multiplication, BPF is usually inserted at the input end of the intermediate frequency signal, but the fluctuation of the tuning frequency becomes a big problem.

The object of the present invention is to solve the above-mentioned drawbacks of the prior art, and to perform a necessary band limitation, and to input a signal to the PLL, and a phase discrimination circuit (PLL) that surely pulls in the synchronization by the frequency discrimination function. Is to be realized.

(Means for Solving Problems) The present invention has the following configuration in order to achieve the above object. That is, the phase-locked carrier recovery circuit of the present invention includes a voltage-controlled oscillator; a first mixer for frequency-converting a signal from the voltage-controlled oscillator and an input intermediate frequency signal; and an output signal of the voltage-controlled oscillator. A first phase shifter for shifting its phase by π / 2 radians; a second mixer for converting the frequency by receiving the output signal of the phase shifter and the input intermediate frequency signal; A first low pass filter for band limiting the output signal; a second low pass filter for band limiting the output signal of the second mixer; a first low pass filter A first modulator that modulates a signal from the voltage controlled oscillator with an output signal of the wave filter; and a first modulator that modulates the signal from the first phase shifter with an output signal of a second low pass filter Two
A combiner for combining the output signal of the first modulator and the output signal of the second modulator; the phase of the signal from the combiner and the voltage controlled oscillator or the first phase shift A phase comparator for comparing the phase of the signal from the phase shifter; a second phase shifter for shifting the phase of the input intermediate frequency signal by π / 2 radians; and an output signal of the phase shifter and the combiner A frequency discriminator that performs frequency discrimination by receiving the signal of the signal; and an adder that receives the output signal of the frequency discriminator and the output signal of the phase comparator and adds them; a band for the signal from the adder And a low-pass filter for limiting and outputting to the voltage-controlled oscillator as a frequency control voltage. FIG. 1 is a block diagram showing the configuration of the phase-locked carrier recovery circuit of the present invention. 1 is a VCO, and its output signal V is now
_o a _{(t) V o (t)} = cosΘ and _L (t). 2 is a first π / 2 phase shifter, 3 is a first mixer (also called a cos mixer because a VCO cos signal is input), 4 is a second mixer (a VCO output signal is π / 2 Since a sine signal delayed by radians is input, it is also called a sin mixer. 5 is a first low-pass filter (also called cosLPF because it follows LPF: cos mixer), 6 is a second low-pass filter. Wave modulator (also called sinLPF), 7 is the first modulator (MOD, cosLPF, so cosMO
Also called D), 8 is a second modulator (also called sinMOD), 9 is a combiner (hybrid), 10 is a second π / 2 phase shifter, 11 is a frequency discriminator (Frequency Discriminator: F).
D), 12 is a phase comparator (PC), 13 is an adder, and 14 is a low-pass filter (LPF).

(Operation) The operation of the phase-locked carrier recovery circuit of the present invention will be described below with reference to FIG.

Now, assuming that the input intermediate frequency signal 101 is V _i (t), V _i (t) = cos θ _i (t) (1), the VCO output signal 102 is V _o (t), and V _o (t) = cos θ _L (t) ) ... (2), the output V _CM of the cos mixer 3 and the output V _SM of the sin mixer 4 are as follows.

V _CM (t) = cos θ _i (t) · cos θ _L (t) = cos θ _e (t) (3) V _SM (t) = cos θ _i (t) · sin θ _L (t) = −sin θ _e ( t) (4) where Θ _e (t) = Θ _i (t) −Θ _L (t) Θ _i (t) = ω _i t + θ _i , Θ _L (t) = ω _L t + θ _L ω _i are input The angular velocity of the signal 101, θ _i represents the initial phase of the input signal 101, ω _L represents the angular velocity of the VCO output 102, and θ _L represents the initial phase of the VCO output 102.

Next, the outputs of the mixers represented by equations (3) and (4) are respectively fed to the first LPF (cosLPF) 5 and the second LPF.
When passing through PF (sinLPF6), output V of cosLPF5
The output V _SLPF (t) of _CLPF (t) and sinLPF6 is given by the following equation.

V _CLPF (t) = A (t) cos (Θ _e (t) −θ _d ) ...
(6) V _SLPF (t) = − A (t) sin (Θ _e (t) −θ _d ) ...
(7) where A (t) indicates the amplitude and A (t) ≧ 0 θ _d is the phase delay generated by cosLPF5 and sinLPF6.

Now for example as cosLPF5 and sinLPF6 Using LPF of comprising properties when it comes to its phase retarded theta _d is ^{_{θ d = -tan -1 ω e t}} ...... (9) where ω _e = ω _i -ω _L.

The output signal V _CLPF (t) of _cosLPF5 is then applied to the first modulator (cosMOD) 7 and the output signal V sinPFF6 of V
_SLPF (t) is added to the second modulator (sinMOD) 8 and co
The output signal of sMOD7 and the output of sinMOD8 are combined by the combiner 10.

When the output of the combiner 10 is V _HYB (t), V _HYB (t) is expressed by the following equation. That is, V _HYB (t) = A (t) cos (Θ _i (t) −θ _d ) ... (1
0). From the above equations (9) and (10), the first π / 2 phase shifter 2, cos mixer 3, sin mixer 4, cosLPF5, sinLPF6, cosMOD
It can be seen that the circuit composed of 7, sinMOD8 and the combiner 9 constitutes a band pass filter (BPF) having a center frequency of ω _L and having the same frequency characteristics as cosLPF5 and sinLPF6.
When the frequency ω _L corresponding to the local oscillation frequency is changed, the center frequency easily changes, so tracking BPF (Tracking BPF)
As excellent.

The output of the combiner 9 thus obtained is added to the phase comparator 12 and the frequency discriminator 11.

The phase comparator 12 outputs the signal sin θ from the first π / 2 phase shifter 2.
_{Since L} is added, phase comparison with the output signal of the combiner 9 is performed. The output V _PC of the phase comparator 12 is expressed by the following equation.

V _PC = A (t) cos (Θ _i −θ _d ) · sin θ _L = −A (t) sin (Θ _e −θ _d ) (11) As can be seen from the equation (11), the phase comparator 12 The output detects the phase difference between the input intermediate frequency signal 101 and the VCO output signal 102. On the other hand, in the frequency discriminator 11, in addition to the signal from the synthesizer 9, a signal obtained by delaying the input intermediate frequency signal 101 by π / 2 radians by the second π / 2 phase shifter (represented by sin Θ _i ) Has been added. Therefore, the output V _FD of the frequency discriminator 11 is expressed by the following equation.

_{V FD = A (t) cos} (Θ i -θ d) · sinΘ i = A (t) sinθ d ...... (12) Further, by substituting equation (9) in the above equation of theta _d, It turns out that the frequency discrimination function is performed.

As described above, the phase locked loop circuit according to the present invention performs not only the phase comparison but also the frequency discrimination function at the time of non-synchronization, so that the reliable lock-in can be performed.

Further, as can be seen from the equation (13), ω _e = 0 → θ _d = 0 (14) in the synchronous state, and the phase difference θ _e is accurately detected by the equation (11).

An application of the PLL according to the present invention to a carrier recovery circuit for a QPSK demodulator is shown in FIG. The operation is exactly the same as that described above except that the multiplication is performed four times to reproduce the carrier wave and the phase comparison is performed using the frequency signal four times higher.

As described above, the phase-locked carrier recovery circuit of the present invention performs the frequency pull-in operation by the frequency discrimination function in the non-synchronous manner, so that the reliable synchronous pull-in is possible. It is solved and can be applied to a wide range of purposes. Also, as shown in Fig. 2, QPSK
In the application to a demodulator, the output of a tracking BPF (Tracking BPF) that can limit the band to the Nyquist band is input to the carrier recovery circuit, so that the deterioration of the SN ratio due to quadruple multiplication can be suppressed.

Furthermore, since the BPF is realized by using two LPFs in the phase locked loop of the present invention, the design of the filter is facilitated, and the problem of fluctuation of the tuning frequency as in the normal BPF is eliminated.

On the other hand, regarding the effect of noise on the frequency discrimination function,
Since one input to the frequency discriminator 11 is the output signal of the follow-up type BPF, the deterioration of the characteristics due to the thermal noise of the input is small even under the low SN condition. In addition, the speed of frequency discrimination operation is
It is as fast as the frequency discrimination operation by BPF, and can be used for demodulators that require extremely fast pull-in to perform burst operation like TDMA communication systems.

(Effects of the Invention) As described above, the phase-locked carrier recovery circuit of the present invention has a frequency discrimination function, and when it is not synchronized, since the frequency pull-in operation is performed by the frequency discrimination function, reliable synchronization pull-in is possible. There is an advantage that the problem of pulling in of the phase locked loop is solved and it can be applied to a wide range of purposes.

In addition, in the application to the multi-phase PSK demodulator, the output of the tracking BPF (Tracking BPF) that can limit the band to the Nyquist band is used as the input to the carrier recovery circuit, so the deterioration of the SN ratio due to frequency multiplication is suppressed. There is an advantage that can be done.

Furthermore, in the phase locked loop circuit of the present invention, since BPF is realized by using two LPFs, there is an advantage that the design of the filter is easy and there is no fluctuation of the tuning frequency as in the normal BPF.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a phase-locked carrier recovery circuit of the present invention, FIG. 2 is a block diagram showing a configuration when the circuit of the present invention is applied to a QPSK signal demodulation circuit, and FIG. FIG. 4 is a block diagram showing the configuration of the circuit, and FIG.
It is a block diagram showing a configuration of a carrier recovery circuit for QPSK demodulation. 1 ... Voltage controlled oscillator (VCO), 2 ... First π / 2 phase shifter, 2 '... π / 2 phase shifter, 3 ... First mixer (cos mixer), 4 ... 2 mixers (sin mixer), 5, 5 '...
1st low pass filter (cosLPF), 6,6 '... 2nd low pass filter (sinLPF), 7 ... 1st modulator (cosMO)
D), 8 ... second modulator (sinMOD), 9 ... combiner, 1
0 …… Second π / 2 phase shifter, 11 …… Frequency discriminator (FD), 1
2 ... Phase comparator (PC), 13 ... Adder, 14 ... Low pass filter, 15, 16 ... Quadrupler.

Claims (1)

[Claims] 1. A voltage controlled oscillator; first for converting a frequency by receiving a signal from the voltage controlled oscillator and an input intermediate frequency signal
A first phase shifter that receives the output signal of the voltage controlled oscillator and shifts its phase by π / 2 radians;
A second mixer for converting the frequency of the output signal of the phase shifter and the input intermediate frequency signal; a first low-pass filter for band limiting the output signal of the first mixer; A second low pass filter for band limiting the output signal of the second mixer; a first modulation for modulating the signal from the voltage controlled oscillator with the output signal of the first low pass filter Second;
A second modulator that modulates the signal from the first phase shifter with the output signal of the low-pass filter of the above; and an output signal of the first modulator and an output signal of the second modulator. A phase comparator for comparing the phase of the signal from the combiner with the phase of the signal from the voltage controlled oscillator or the first phase shifter; and the phase of the input intermediate frequency signal by π / A second phase shifter that shifts the phase by 2 radians; a frequency discriminator that performs frequency discrimination by receiving an output signal of the phase shifter and a signal from the synthesizer; an output signal of the frequency discriminator and the phase An adder that receives the output signals of the comparators and adds them; a low-pass filter that performs band limitation on the signals from the adder and outputs the frequency-controlled voltage to the voltage-controlled oscillator; A phase-locked carrier recovery circuit, comprising: