JPH0797118B2 - Voltage detection circuit - Google Patents
Voltage detection circuitInfo
- Publication number
- JPH0797118B2 JPH0797118B2 JP61100158A JP10015886A JPH0797118B2 JP H0797118 B2 JPH0797118 B2 JP H0797118B2 JP 61100158 A JP61100158 A JP 61100158A JP 10015886 A JP10015886 A JP 10015886A JP H0797118 B2 JPH0797118 B2 JP H0797118B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- gate
- type
- power supply
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 description 11
- 208000011380 COVID-19–associated multisystem inflammatory syndrome in children Diseases 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005070 sampling Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 101001005165 Bos taurus Lens fiber membrane intrinsic protein Proteins 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
Landscapes
- Measurement Of Current Or Voltage (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電圧検出回路に関し、特に半導体をゲート電
極として用いるMIS型半導体集積回路に関するものであ
る。The present invention relates to a voltage detection circuit, and more particularly to a MIS type semiconductor integrated circuit using a semiconductor as a gate electrode.
従来、半導体集積回路に内蔵された電圧検出回路は、第
2図に示す回路等が用いられてきた。ここでMP21,MP22
は等しい電流能力、スレツシヨルド電圧をもつP型MIS
トランジスタ、MN21,MN22は等しい電流能力をもち、各
々スレツシヨルド電圧、VTN1,VTN2をもつN型MISトラン
ジスタ、21は、N型MISトランジスタを用いた分圧抵
抗、22は、コンパレータ、VDDは電源、VSSは電源で
ある。ここでVref2は、基準電圧で、 Vref2=VDD−(VTN1−VTN2) となる電圧であり、Vcmp2は Vcmp2=1/n・VDD となる電圧である。コンパレータにより、Vcmp2がVref2
より高レベルか低レベルかを判別する。Conventionally, the circuit shown in FIG. 2 and the like have been used as a voltage detection circuit built in a semiconductor integrated circuit. Where MP21, MP22
Is a P-type MIS with equal current capability and threshold voltage
Transistors, MN21 and MN22, have the same current capacity, N-type MIS transistors having threshold voltages V TN1 and V TN2 respectively, 21 is a voltage dividing resistor using N-type MIS transistors, 22 is a comparator, V DD is The power supply, V SS, is the power supply. Here, Vref2 is a reference voltage, which is a voltage at which Vref2 = V DD − (V TN1 −V TN2 ), and Vcmp2 is a voltage at which Vcmp2 = 1 / n · V DD . Vcmp2 becomes Vref2 by the comparator
Determine if it is higher or lower.
従来このような回路は、時計用集積回路の電池寿命検出
用として主に用いられていたため、電源電圧が、比較的
低く(3v以下)安定している。サンプリング動作をして
も、応答速度に問題はない、等の条件を満たしていたた
め、問題はなかつた。Conventionally, such a circuit has been mainly used for detecting the battery life of an integrated circuit for a timepiece, so that the power supply voltage is relatively low (3v or less) and stable. Even if the sampling operation was performed, there was no problem because the response speed had no problem.
ところが、モータドライブ回路等を含む、マイクロコン
ピユータ・システムのシステムリセツト信号等に用いる
場合、上記の条件は両者とも満たせない。例えば、電池
駆動のシステムにおいて、動作時はモータドライブ等に
より電源電圧変動が激しく、非動作時は、低消費電力が
要求される。又、電源電圧は、モータ駆動の為、比較的
高い(3〜6v程度)電圧値に設定されている。システム
の暴走をさける為サンプリング動作が出来ず、広い電源
電圧範囲(2〜6v程度)の中で、従来回路を用いた場
合、消費電流がほぼ電圧の2乗に比例しているため、低
消費電力となり得ない。又、集積回路チツプの面積を小
さくする為用いているN型MISトランジスタ分圧抵抗
も、その電流値を小さくすると、応答速度が遅くなる。
さらに、リニアな特性でないため、設計もむずかしい。
又、製造バラツキにより分圧値も異なつてくる。However, when used for a system reset signal of a micro computer system including a motor drive circuit or the like, neither of the above conditions can be satisfied. For example, in a battery-powered system, a power supply voltage fluctuates drastically due to a motor drive or the like during operation, and low power consumption is required during non-operation. Further, the power supply voltage is set to a relatively high voltage value (about 3 to 6v) because the motor is driven. Sampling operation cannot be performed to avoid system runaway, and current consumption is almost proportional to the square of the voltage when using a conventional circuit in a wide power supply voltage range (about 2 to 6v). It cannot be electricity. Further, the response speed of the N-type MIS transistor voltage dividing resistor used to reduce the area of the integrated circuit chip becomes slow when the current value is reduced.
Furthermore, the design is difficult because it has no linear characteristics.
Further, the partial pressure value also varies due to manufacturing variations.
本発明はかかる問題点を解決するためのものでその目的
とするところは、広い電源電圧範囲にわたり、低消費電
力であり、サンプリング動作することなく高速に動作
し、集積回路内専有面積が小さく、製造容易で、製造バ
ラツキに強く、温度依存性の小さい電圧検出回路を提供
するものである。The present invention is for solving such a problem, and an object thereof is to have a wide power supply voltage range, low power consumption, operate at high speed without sampling operation, and have a small occupied area in an integrated circuit. It is intended to provide a voltage detection circuit which is easy to manufacture, is resistant to manufacturing variations, and has small temperature dependence.
本発明の電圧検出回路は、 カレントミラー回路を用いた基準電圧源と、該基準電圧
源の出力である基準電圧を入力とするコンパレータとを
備えた電圧検出回路において、 前記基準電圧源は、第1の電源端子と第2の電源端子と
の間に直列に接続された第2導電型のゲートを有する第
2導電型のデプレッションタイプの第1のトランジスタ
及び第1導電型のゲートを有する第1の導電型の第2の
トランジスタと、前記第1の電源端子と前記第2の電源
端子との間に直列に接続された第1導電型のゲートを有
する第2導電型の第3のトランジスタ及び第1導電型の
ゲートを有する第1導電型の第4のトランジスタとを備
え、 前記第1のトランジスタのゲート及びソース端子が前記
第1の電源端子に接続され、前記第2及び前記第4のト
ランジスタのゲート端子が前記第1及び前記第2トラン
ジスタのドレイン端子に接続され、前記第3のトランジ
スタのソース端子が前記第1の電源端子に接続され、か
つゲート端子が前記第3及び第4のトランジスタのドレ
イン端子に接続され、前記第3及び前記第4のトランジ
スタの前記ドレイン端子の接続点から前記基準電圧を出
力し、 前記コンパレータは、第2導電型のゲートを有する第2
導電型の第5のトランジスタと第1導電型のゲートを有
する第2導電型の第6のトランジスタとからなる差動入
力回路と、第2導電型の第7のトランジスタからなる電
流源とを含む差動増幅回路で構成され、 該電流源は前記第1のトランジスタのドレイン電流に基
づいた電流を前記第5及び第6のトランジスタのソース
端子に供給し、前記基準電圧が前記第5のトランジスタ
のゲート端子に入力されてなることを特徴とする。The voltage detection circuit of the present invention is a voltage detection circuit comprising a reference voltage source using a current mirror circuit and a comparator having a reference voltage as an output of the reference voltage source as an input, wherein the reference voltage source is A first transistor of a second conductivity type depletion type having a second conductivity type gate connected in series between a first power supply terminal and a second power supply terminal, and a first transistor having a first conductivity type gate And a second transistor of the second conductivity type having a second transistor of the conductivity type and a gate of the first conductivity type connected in series between the first power supply terminal and the second power supply terminal, and A fourth transistor of a first conductivity type having a gate of a first conductivity type, a gate and a source terminal of the first transistor are connected to the first power supply terminal, and the second and fourth transistors are connected. Transis Has a gate terminal connected to the drain terminals of the first and second transistors, a source terminal of the third transistor connected to the first power supply terminal, and a gate terminal of the third and fourth transistors. Is connected to the drain terminal of the third and fourth transistors, and outputs the reference voltage from a connection point of the drain terminals of the third and fourth transistors, and the comparator has a second conductivity type gate having a second conductivity type gate.
A differential input circuit including a conductive type fifth transistor and a second conductive type sixth transistor having a first conductive type gate; and a current source including a second conductive type seventh transistor The current source supplies a current based on the drain current of the first transistor to the source terminals of the fifth and sixth transistors, and the reference voltage of the fifth transistor is a differential amplifier circuit. It is characterized by being input to the gate terminal.
以下、本発明について実施例に基づき詳細に説明する。 Hereinafter, the present invention will be described in detail based on examples.
第1図は、本発明の電圧検出回路の一実施例である。11
は基準電圧発生回路、12はコンパレータである。以下こ
とわりのない限り、ゲート電極はポリシリコン、ゲート
電極タイプはN型とする。基準電圧発生回路は、P型ゲ
ートP型MISトランジスタMP1と、MP1とほぼ等しい電流
特性を有するP型MISトランジスタ(以下PMISと称す)M
P2、電流特性の同一なN型MISトランジスタ(以下NMIS
と称す)ペアMN1,MN2とからなる。MP1とMP2とのスレツ
シヨルド電圧差は、ゲート電極タイプの違いにより、そ
の仕事関数差となり、ゲート電極がポリシリコンのた
め、約1.1vとなる。たとえばMP2のスレツシヨルド電圧
を−0.5vとすると、同一製造条件のもとではMP1のスレ
ツシヨルド電圧は0.6vとなり、デプレシヨン型MISトラ
ンジスタとなる。そのため第1図に示す回路構成が可能
となり、出力電圧Vrefは、各々のスレツシヨルド電圧に
関係なく、 VrefVDD−1.1〔v〕 となる。Vrefの温度依存性も実測で、ppmオーダーとな
り非常に小さい。さらに消費電流は、回路構成により、
MP1により決まり、電源電圧にほとんど依存しない。
又、製造上も、PMISのソース・ドレイン領域を形成する
P型不純物イオン打込み工程をそのまま利用できるた
め、容易である。FIG. 1 shows an embodiment of the voltage detection circuit of the present invention. 11
Is a reference voltage generating circuit, and 12 is a comparator. Unless otherwise specified, the gate electrode is polysilicon and the gate electrode type is N type. The reference voltage generating circuit includes a P-type gate P-type MIS transistor MP1 and a P-type MIS transistor (hereinafter referred to as PMIS) M having a current characteristic almost equal to that of MP1.
P2, N-type MIS transistor with the same current characteristics (hereinafter NMIS
Called) pair MN1 and MN2. The threshold voltage difference between MP1 and MP2 is the work function difference due to the difference in the gate electrode type, and is about 1.1v because the gate electrode is polysilicon. For example, assuming that the threshold voltage of MP2 is −0.5v, the threshold voltage of MP1 is 0.6v under the same manufacturing conditions, and a depletion type MIS transistor is obtained. Therefore, the circuit configuration shown in FIG. 1 is possible, and the output voltage Vref becomes VrefV DD -1.1 [v] regardless of the threshold voltage. The measured temperature dependence of Vref is also in the ppm order, which is extremely small. Furthermore, the current consumption depends on the circuit configuration.
Determined by MP1 and almost independent of power supply voltage.
Further, in manufacturing, the P-type impurity ion implantation process for forming the source / drain regions of the PMIS can be used as it is, which is easy.
コンパレータは、電流源として動作するPMIS、MP4、差
動トランジスタを構成するMP5,MP6及び、MN5,MN6とから
成る。ここで、MN5,MN6は、同一の電流特性を有するNMI
S、MP6は、−1.6v程度のスレツシヨルド電圧を有するPM
IS、MP5は、MP6のゲートタイプをP型とした、MP6と電
流能力の等しいP型MISトランジスタである。ここでも
基準電圧発生回路と同様の原理に基づき、コンパレータ
のオフセツト電圧は、ゲート電極の仕事関数差による約
1.1vとなる。オフセツト電圧の温度依存性も非常に小さ
い。さらに消費電流は回路構成上、MP1により決まり、
電源電圧にほとんど依存しない。又製造上もP型ゲート
は、基準電圧発生回路と同様に容易であり、さらに−1.
6v程度のスレツシヨルド電圧は、P型不純物をチヤネル
ドープし、スレツシヨルド電圧をvに近づける、通常の
PMIS製造工程をマスクすることにより容易に得られる。The comparator is composed of PMIS, MP4 which operates as a current source, MP5, MP6 and MN5, MN6 which constitute differential transistors. Here, MN5 and MN6 are NMIs having the same current characteristics.
S and MP6 are PMs with a threshold voltage of about -1.6v
IS and MP5 are P-type MIS transistors having the same current capability as MP6, with the gate type of MP6 being P-type. Again, based on the same principle as the reference voltage generation circuit, the offset voltage of the comparator is about the difference due to the work function difference of the gate electrode.
It becomes 1.1v. The temperature dependence of the offset voltage is also very small. Furthermore, the current consumption is determined by MP1 due to the circuit configuration,
Almost independent of power supply voltage. Also in manufacturing, the P-type gate is as easy as the reference voltage generating circuit, and -1.
The threshold voltage of about 6v is channel-doped with P-type impurities to bring the threshold voltage close to v.
It is easily obtained by masking the PMIS manufacturing process.
このように本実施例では、回路動作電流が、デプレシヨ
ンMISトランジスタMP1によつて決まるため、広い電源電
圧範囲にわたり低消費電力であり、従来回路に比べ、素
子数及び集積回路内専有面積が小さく、製造も特殊な工
程を必要とせず、物理的な仕事関数で決まる電位差を検
出するため製造バラツキに強く、温度依存性も小さく、
応答速度も、コンパレータの応答速度のみで決まるため
高速に出来、設計も容易な、約2.2vの電圧検出回路が提
供できる。As described above, in this embodiment, since the circuit operating current is determined by the depletion MIS transistor MP1, the power consumption is low over a wide power supply voltage range, and the number of elements and the area occupied in the integrated circuit are small as compared with the conventional circuit, Manufacturing does not require a special process, and because it detects the potential difference determined by the physical work function, it is resistant to manufacturing variations and has low temperature dependence.
Since the response speed is determined only by the response speed of the comparator, it is possible to provide a high-speed and easy-to-design voltage detection circuit of about 2.2v.
また、本実施例ではP型ポリシリコンゲートとN型ポリ
シリコンゲートの仕事関数差を用いたがもちろん、異種
金属間、金属−半導体間、異種半導体間等、各種の仕事
関数差を利用出来ることはいうまでもない。さらに本実
施例の回路図は、電源電圧の検出回路であるが、もちろ
ん、他の電位の検出にも用いることが出来る。Further, in the present embodiment, the work function difference between the P-type polysilicon gate and the N-type polysilicon gate is used, but it is of course possible to use various work function differences such as between different metals, between metal and semiconductor, between different semiconductors. Needless to say. Further, although the circuit diagram of this embodiment shows a power supply voltage detection circuit, it can be used for detection of other potentials, of course.
さらに基準電圧源を直列に2段用いることにより約3.3v
の電圧検出が可能であり、イントリンシツク型ゲートを
用いたり、チヤネルドープにより、検出電圧の微調整が
可能である。Furthermore, by using two stages of reference voltage source in series, about 3.3v
The voltage can be detected, and the detection voltage can be finely adjusted by using an intrinsic type gate or by channel doping.
又本実施例では、VDD電位基準の回路構成について述べ
たが、PMISとNMISを逆転した回路構成によりVSS電位基
準の回路構成、あるいは、他の電位を基準とすることも
できる。Although the circuit configuration based on the V DD potential is described in the present embodiment, the circuit configuration based on the V SS potential may be used by using the circuit configuration in which PMIS and NMIS are reversed, or another potential may be used as the reference.
以上述べたように本発明では、広い電源電圧範囲にわた
り低消費電力であり、集積回路内専有面積が小さく、製
造も容易であり、製造バラツキにほとんど影響をうけ
ず、温度依存性も小さく、応答速度も速く、設計も容易
な、電圧検出回路を提供できる。As described above, according to the present invention, the power consumption is low over a wide power supply voltage range, the area occupied by the integrated circuit is small, the manufacturing is easy, the manufacturing variations are hardly affected, the temperature dependence is small, and the response is small. It is possible to provide a voltage detection circuit that is fast and easy to design.
第1図は、本発明の電圧検出回路一実施例図、 第2図は、従来回路例図、 11は基準電圧発生回路 12はコンパレータ MP1〜6はPMIS,MN1〜6はNMIS FIG. 1 is a diagram showing an embodiment of a voltage detecting circuit of the present invention, FIG. 2 is a diagram showing an example of a conventional circuit, 11 is a reference voltage generating circuit 12, 12 are comparators MP1 to 6 are PMIS, and MN1 to 6 are NMIS.
Claims (1)
と、該基準電圧源の出力である基準電圧を入力とするコ
ンパレータとを備えた電圧検出回路において、 前記基準電圧源は、第1の電源端子と第2の電源端子と
の間に直列に接続された第2導電型のゲートを有する第
2導電型のデプレッションタイプの第1のトランジスタ
及び第1導電型のゲートを有する第1の導電型の第2の
トランジスタと、前記第1の電源端子と前記第2の電源
端子との間に直列に接続された第1導電型のゲートを有
する第2導電型の第3のトランジスタ及び第1導電型の
ゲートを有する第1導電型の第4のトランジスタとを備
え、 前記第1のトランジスタのゲート及びソース端子が前記
第1の電源端子に接続され、前記第2及び前記第4のト
ランジスタのゲート端子が前記第1及び前記第2のトラ
ンジスタのドレイン端子に接続され、前記第3のトラン
ジスタのソース端子が前記第1の電源端子に接続され、
かつゲート端子が前記第3及び第4のトランジスタのド
レイン端子に接続され、前記第3及び前記第4のトラン
ジスタの前記ドレイン端子の接続点から前記基準電圧を
出力し、 前記コンパレータは、第2導電型のゲートを有する第2
導電型の第5のトランジスタと第1導電型のゲートを有
する第2導電型の第6のトランジスタとからなる差動入
力回路と、第2導電型の第7のトランジスタからなる電
流源とを含む差動増幅回路で構成され、 該電流源は前記第1のトランジスタのドレイン電流に基
づいた電流を前記第5及び第6のトランジスタのソース
端子に供給し、前記基準電圧が前記第5のトランジスタ
のゲート端子に入力されてなることを特徴とする電圧検
出回路。1. A voltage detection circuit comprising a reference voltage source using a current mirror circuit and a comparator having a reference voltage as an output of the reference voltage source as an input, wherein the reference voltage source is a first power supply. A second conductivity type depletion type first transistor having a second conductivity type gate connected in series between a terminal and a second power supply terminal, and a first conductivity type having a first conductivity type gate Second transistor, a second transistor of the second conductivity type having a gate of the first conductivity type connected in series between the first power supply terminal and the second power supply terminal, and a first conductivity type A fourth transistor of a first conductivity type having a gate of a second type, the gate and source terminals of the first transistor being connected to the first power supply terminal, and the gates of the second and fourth transistors end There is connected to the first and a drain terminal of the second transistor, a source terminal of said third transistor being connected to said first power supply terminal,
The gate terminal is connected to the drain terminals of the third and fourth transistors, the reference voltage is output from the connection point of the drain terminals of the third and fourth transistors, and the comparator is a second conductive element. Second with a gate of the mold
A differential input circuit including a conductive type fifth transistor and a second conductive type sixth transistor having a first conductive type gate; and a current source including a second conductive type seventh transistor The current source supplies a current based on the drain current of the first transistor to the source terminals of the fifth and sixth transistors, and the reference voltage of the fifth transistor is a differential amplifier circuit. A voltage detection circuit characterized by being inputted to a gate terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61100158A JPH0797118B2 (en) | 1986-04-30 | 1986-04-30 | Voltage detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61100158A JPH0797118B2 (en) | 1986-04-30 | 1986-04-30 | Voltage detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62257068A JPS62257068A (en) | 1987-11-09 |
| JPH0797118B2 true JPH0797118B2 (en) | 1995-10-18 |
Family
ID=14266507
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61100158A Expired - Lifetime JPH0797118B2 (en) | 1986-04-30 | 1986-04-30 | Voltage detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0797118B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5010514B2 (en) * | 2008-01-24 | 2012-08-29 | 株式会社リコー | Voltage detection circuit |
| CN117471152B (en) * | 2023-12-27 | 2024-03-08 | 苏州贝克微电子股份有限公司 | Low-power-consumption voltage detection circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5415782A (en) * | 1977-06-17 | 1979-02-05 | Seiko Epson Corp | Voltage detecting circuit |
| JPS56141566A (en) * | 1980-04-04 | 1981-11-05 | Seiko Instr & Electronics Ltd | Voltage detecting circuit |
-
1986
- 1986-04-30 JP JP61100158A patent/JPH0797118B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62257068A (en) | 1987-11-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |