JPH0797309B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a calculation method of a comparison logical operation instruction in a data processing device, and more particularly, a data transfer width between a storage unit and a storage control unit is equal to that of the storage control unit. The present invention relates to a comparison logical operation device in a data processing device having a data transfer width larger than that of a data processing device.

[Background of the Invention]

The comparison logical operation instruction in the data processing device is an instruction that determines whether the relationship between the first operand and the second operand is equal, whether the first operand is large or small, and shows the result of this determination as a condition code. The judgment is generally processed by using the subtraction function of the arithmetic unit. For this reason, the processing speed of the comparison logic operation instruction in the data processing device having a configuration in which the arithmetic width of the arithmetic unit is smaller than the data width processed by the storage control unit is determined by the arithmetic width of the arithmetic unit. On the other hand, in the data processing device having the above-described configuration, the speed can be increased by providing the storage control unit with the subtraction circuit and processing the comparison logical operation instruction by the storage control unit. However, the storage control unit divides into bit units in order to speed up the transfer logical operation instruction (collects bit 0 of each byte into one configuration, and similarly configures each of bit 1 to bit 7 into one configuration). In general, it is an implementation in which 1 bit or several bits are collectively divided). This transfer logical operation instruction is an instruction for transferring the data of the second operand to the position of the first operand, and it requires a shift function in byte units. For this reason, it is convenient to implement division in bit units. The subtraction circuit is provided in the storage control unit divided into such bit units to determine the magnitude relation between the two operands in the comparison logical operation instruction in order to increase the number of signal pins for the carry signal between each bit. It was difficult to implement. Note that, for example, JP-A-58-182772 can be cited as one related to speeding up of transfer logical operation instructions.

[Object of the Invention]

It is an object of the present invention to provide a data processing device that processes a comparison logical operation instruction at high speed.

[Outline of Invention]

A feature of the present invention is that the storage control unit detects a mismatch between two operands, and transfers only the data necessary for setting the relationship between the two operands as a condition code after detecting a mismatch or detecting the end of comparison to the arithmetic unit. The purpose of this is to speed up the comparison logic operation instruction by determining the transferred data by the arithmetic unit and setting the condition code.

Example of Invention

An embodiment of the present invention will be described with reference to FIG. FIG. 1 is composed of a storage unit (MS) 1, a storage control unit (SCU) 2, an arithmetic unit (ALU) 3, and an execution control unit (ESU) 4, and is provided between the storage unit 1 and the storage control unit 2. This is an example of a data processing device having a data transfer width of 8 bytes and a data transfer width between the storage control unit 2 and the arithmetic unit 3 of 4 bytes. The storage control unit 2 stores the AND gate 25, a data register A (DRA) 20 having a length of 8 bytes, a data register B (DRB) 21, and a second operand data which hold the first operand data and the second operand data, respectively. Matching circuit (AL) 22 that shifts to the start position of the operand, comparison circuit (COMP) 23, selection circuit (SEL) that selects 4 bytes out of 8 bytes of data register A20 or data register B21
Consists of 24.

In the following, according to the microprogram flow of FIG.
The operation of the figure will be described.

In FIG. 2, in step 200, fetch activation for reading the second operand data from the storage unit MS1 is performed. The second operand data read from MS1 is output as read data at the byte position of the valid operand by the AND gate 25 in the storage control unit 2 through the data signal line 100 having a width of 8 bytes, and "0" is output at the byte position of the invalid operand. "Is output and held in the data register DRB21. The distinction between valid and invalid operands in the 8 bytes is indicated by the 8-bit signal line 104 on a byte-by-byte basis, and is created by the operand length update circuit 40 in the execution control unit 4, and the first and second operands are used. Created every time the operand fetch is started. The second operand data held in DRB21 goes up to the matching circuit AL22, is shifted to the start position of the first operand, and is input into the comparison circuit COMP23. In step 201, the first operand data is M
The fetch operation for reading from S1 is performed, and the first operand data read from MS1 is invalid through the data signal line 100 by the AND gate 25 in SCU2 and the signal line 104. "0" is output to the byte position of the operand and the data register DR
It is held in A20 and directly input to COMP23. The two operands input to COMP 23 are compared, and the microprograms of steps 200 and 201 are repeatedly executed until the comparison process is completed. The end of the comparison process is when the mismatch between the two operands is detected or the operand lengths are compared. The former detects a mismatch at COMP23, outputs a 1-bit signal line 102, and sends it to the execution control unit 4. The latter is an operand length updating circuit 40 in the execution control unit 4.
At the same time, the signal line 104 indicating the valid and invalid operands is output, the end of comparison of the operand lengths is also determined, and the end of comparison is output to the signal line 105. These mismatch signal line 102 and operand length comparison end signal line 105 are passed through the OR gate 41 in the execution control unit 4 to form a test matrix.
Entered in 42 and tested. This test result is step 20
It is reflected in the test condition 1 "TEST = END", and when the test is not established (END), step 200 is executed and the test is established (EN
In the case of D), the loop of step 200 and step 201 is exited and step 202 is executed. The signal line 103 is an output signal of the comparison circuit 23, which indicates whether a mismatch is detected in the first 4 bytes or the latter 4 bytes of the comparison result of 8 bytes. Step
At 202, the first 8 bytes of the first operand data held in the data register A20 is selected by the signal line 103 and the selection circuit 24 from the first 4 bytes or the second 4 bytes,
Transferred to the operation unit 3 through the 4-byte width data signal line 101, and the 4-byte length data register (LX30) in the operation unit 3
Set to. In step 203, the final 8 bytes of the second operand data held in the data register B21 is set in the data register 31 (LY) of 4 bytes in the arithmetic unit 3 as data of 4 bytes as in step 202. Along with the first set on the LX30 in step 202
The operand is subtracted from the 4-byte width arithmetic unit 32, the result of the subtraction is judged by the condition code setting circuit 33, the magnitude relation is set to the condition code, and the arithmetic operation ends. On the other hand, in the test result in step 201, if the test is established because the comparison of the operand lengths is completed, the data register A20 and the data register B21 hold equal operands,
It is obvious that the first half 4 bytes of both operands are transferred to the arithmetic unit 3 and the result of the arithmetic operation is set with a condition code indicating "both operands are equal". As described above, since the one of the four bytes in the first half and the latter half that has detected a mismatch is sent to the arithmetic unit, the magnitude comparison result can be obtained earlier than sending all eight bytes.

FIG. 3 is a configuration diagram in the case where the storage control unit SCU2 is mounted separately in bit units. In FIG. 3, the LSI module 300
Is a configuration when bit 0 of each byte is collected into one LSI module. With the same configuration, the LSI module 301 is an LSI module in which bit 1 is collected.
It consists of eight LSI modules from module 300 to LSI module 307. The non-match signal of the two operand data is output from each LSI module bit by bit by eight signal lines from signal line 310 to signal line 317. These eight signal lines are collected in the LSI module 308 and OR gate 51 Through 1
The bit mismatch signal line 102 is omitted. Further, eight signal lines from the signal line 320 to the signal line 327 are signal lines indicating whether a mismatch is detected in the first 4 bits or the latter 4 bits in the 8-bit data in each LSI module. ,
These eight signal lines are also collected in the LSI module 308 like the eight signal lines 310 to 317, and are connected to one through the OR gate 50.
The bit signal line 103 is output. The signal lines 103 are respectively input from the LSI module 300 to the LSI module 307, and the selection circuit S
Used as EL24 selection signal.

FIG. 4 is a comparison circuit C in the LSI module 30 shown in FIG.
It is a detailed view of OMP23. When the two input data of the COMP 23 are a _{0 to} a ₇ and b _{0 to} b ₇ , respectively, the exclusive ORs of the two data are taken by the exclusive OR gates 60 to 67 for each bit. The outputs of the exclusive OR gates 60 to 63 from bit 0 to bit 3 are output as a signal line 320 through the OR gate 70, and the outputs of the exclusive OR gates 64 to 67 from bit 4 to bit 7 and DR The output of gate 70 is OR gate 71
Is output as a signal line 310. That is, the signal line 320 is a mismatch signal in the first 4 bits of the 8-bit data, and the signal line 310 is a mismatch signal of all the 8-bit data.

As described above, since the storage control unit only compares two operands, the hardware is simple and the number of signal pins is small, and the comparison processing can be performed at high speed.

〔The invention's effect〕

According to the present invention, the storage control unit only compares the two operands for coincidence and non-coincidence. For the magnitude relation, only the necessary data is transferred to the arithmetic unit and the arithmetic unit judges the operands every cycle. The time to transfer to the arithmetic unit can be saved, and the comparison logic operation can be processed at high speed without increasing the number of signal pins with the simple hardware that can be processed with the data width in the storage control unit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
An example of a microprogram flow of a variable length comparison logical operation in the configuration example of FIG. 3, FIG. 3 is an example of the configuration when the storage control unit is divided into bit units, and FIG. 4 is a detail of the comparison circuit in FIG. It is a figure. 1 ... storage unit, 2 ... storage control unit, 30 ... arithmetic unit, 4 ... execution control unit, 20, 21, 30, 31 ... data register, 22 ... matching circuit, 23 ... comparison circuit, 24 …… Selection circuit, 32 …… Calculator, 33
...... Condition code setting circuit, 40 …… Comparison end circuit, 43 …… Test matrix

Claims (1)

[Claims] 1. A storage unit, a storage control unit for reading an operand from the storage unit, and an arithmetic unit for processing an operand read from the storage unit by the storage control unit. A data processing device having a data transfer width with the control unit larger than a data transfer width with the storage control unit and the arithmetic unit, wherein the storage control unit stores the first and second operands read from the storage unit. First and second data registers for storing, and the first and second operands stored in the first and second data registers in units of data transfer width between the storage control unit and the arithmetic unit And a selector for selecting the mismatched portion of the first and second operands and sending it to the arithmetic unit when the comparator detects a mismatch, and the arithmetic unit sends Enemy The data processing apparatus characterized by having an arithmetic unit for performing size determination of the unmatched portion of said first and second operand.