JPH0797329B2 - Information processing system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system, and more particularly to a failure processing method for an information processing system having an arithmetic processor serially connected to one or a plurality of ports as a constituent element. .

[Conventional technology]

Conventionally, the failure processing method of each processor in a large multiprocessor system has been considered for the processors connected in parallel to the system control device.
For example, when a failure occurs in the arithmetic processor, it is usual to perform a logout process by the diagnostic processor that receives a failure report from the arithmetic processor and a degradation process of the arithmetic processor by the system control processor.

With the advent of supercomputers in recent years, the idea of pursuing only arithmetic processing performance has emerged, and a system in which the number of arithmetic processors is much larger than that of conventional large-scale general-purpose machines has been considered. In such a system, connecting all arithmetic processors to the system controller causes a significant increase in the data path and is physically difficult to realize, so the arithmetic processors are connected in series to several system controller ports. The method is adopted. For this reason, a high-order / low-order relationship naturally arises in each arithmetic processor, and when a failure occurs in a certain arithmetic processor, the arithmetic processor subordinate to the arithmetic processor is also affected and becomes unusable. Therefore, if the conventional failure processing method is used, it is necessary to execute the failure processing of the lower-order arithmetic processors after the failure processing of the failed arithmetic processor.

[Problems to be Solved by the Invention]

The conventional fault processing method described above is intended for an information processing system in which a plurality of arithmetic processors are connected in parallel to a system controller, and when the control processor receives a fault report communication, only the faulty arithmetic processor is disabled. It was graded.

When the conventional fault processing method is applied to the information processing system having the configuration shown in the claims, when the control processor receives the fault report communication, it degrades only the faulty arithmetic processor and lowers the arithmetic processor. The arithmetic processor group (away from the system control unit) is not degraded. As a result, the higher-order arithmetic processors are degraded, and the lower-order arithmetic processors whose operation cannot be guaranteed fail one after another, and each time the failure processing is performed by the above-mentioned process, the respective processors are degraded. However, there is a drawback in that the overhead of fault handling becomes large.

[Means for Solving the Problems]

An information processing system of the present invention is an information processing system including a system control device, a main storage device connected to the system control device, a system control processor, a diagnostic processor, and a plurality of arithmetic processors, The processor is connected in series to the system control device, and further has a fault detection notification circuit that reports a fault to the diagnostic processor independently of each other, and the diagnostic processor is a connection state between the plurality of arithmetic processors. And a connection held by the connection configuration circuit so that when a notification of a fault is received from the plurality of arithmetic processors, the arithmetic processors connected to a lower level of the arithmetic processor that has notified the fault are disconnected at once. An operation that is connected to a lower level of the operation processor that updates the status and notifies the failure And a failure processing control circuit for controlling the disorder from processor so as not to report to the system control processor.

[Action]

The system control processor, which has been notified that a failure has occurred in the arithmetic processor, refers to and updates the connection configuration table, and controls the batch processing of the required arithmetic processors in a batch. It is possible to eliminate the failure processing overhead that occurs when the lower-order arithmetic processors are individually degraded.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the information processing system of the present invention.

The information processing system according to the present embodiment includes a system controller 1
A main memory 2 connected to it, a system control processor 3, a diagnostic processor 4, arithmetic processors 10, 11, 12 connected in series, arithmetic processors 20, 21 connected in series, and signals Line 100,101,102,110,111,112,120,1
It consists of 21 and.

Each of the system control processor 3, the diagnostic processor 4, and the arithmetic processors 10, 11, 12, 20, 21 can access the main storage device 2 via the system control device 1 and communicate with each other (hereinafter, P processor). Communication). The system control device 1 includes a system control processor 3, a diagnostic processor 4, and an arithmetic processor 1.
It is possible to control access to the main storage device 2 from 0, 11, 12, 20, and 21 and P communication performed between the processors. The main memory 2 has an operating system program,
User program and arithmetic processor 10,11,12,20,21
A connection configuration table 40 that provides the connection configuration information is stored. The connection configuration table 40 is created at the initial startup of the information processing system, and the arithmetic processors 10, 11, 12, 2
Connection configuration information indicating whether or not 0, 21 is connected to the system control unit 3 and whether the configuration is valid or invalid, and whether or not there is a connection between the arithmetic processors 10, 11, 12, 20, 21 connected in series and the configuration is valid. / Store connection configuration information indicating invalidity. The system control processor 3 controls the information processing system, executes an operating system program and a user program stored in the main storage device 2, and allocates tasks to the arithmetic processors 10, 11, 12, 20, 21. Also,
The system control processor 3 has a fault processing control circuit 43. When the fault processing control circuit 43 is informed of the faulty arithmetic processor by P communication from the diagnostic processor 4, the content of the connection configuration table 40 is read out and the connection configuration table is read. The configuration of the faulty arithmetic processor stored in 40 and all arithmetic processors connected and configured under the faulty arithmetic processor is invalidated, and the connection configuration table 40 is updated. The arithmetic processors 10, 11, 12, 20, 21 are processors that specialize in high-speed arithmetic such as vector arithmetic, and fault detection notification circuits 30, 31, 32, 3
It has 3,34 respectively. Fault detection notification circuit 30, 31, 3
The reference numerals 2, 33, and 34 detect the faults in the arithmetic processors 10, 11, 12, 20, and 21, respectively, and notify the diagnostic processor 4 using the signal lines 210, 211, 212, 220, and 221 respectively. Diagnostic processor 4
Is a connection configuration circuit 42 having a copy of the connection configuration table 40
And a failure detection notification circuit 30, 31, 32, 33, 34, a failure operation processor stored in the connection configuration circuit 42 and all operation processors connected and configured under the failure operation processor. And a fault processing control circuit 50 for informing the system control processor 3 of the highest arithmetic processor in which a fault has occurred by P communication via the system control device 1 using the signal lines 102 and 101 to the system control processor 3. There is. Further, the diagnostic processor 4 refers to the connection configuration circuit 42, which is a copy of the connection configuration table 40, when a fault is propagated between the arithmetic processors connected in series and the faults are simultaneously reported from a plurality of arithmetic processors. Then, the highest-ranking arithmetic processor is determined, and failure reports from other arithmetic processors are not reported to the system control processor 3. The contents of the connection configuration circuit 42 are the same as those of the diagnostic processor 4.
Updated by Therefore, the overhead of failure processing can be reduced.

Next, a connection configuration table that stores connection configuration information
40 and its updating method will be described in detail.

The following table is a table showing the connection configuration table 40.

The connection configuration information for one arithmetic processor is stored in one word (2 bytes), and the connection configuration information for each arithmetic processor 10, 20, 11, 21, 12 is stored in words 0, 1, 2, 3, 4 respectively. It
V indicates whether or not the arithmetic processor is configured, and is "1" when it is configured and "0" when it is degraded. S indicates whether or not the arithmetic processor is connected to the system control device 1, and is “1” when connected and “0” when not connected. The UAP # indicates the number of the arithmetic processor above the arithmetic processor. VL indicates whether or not an arithmetic processor is connected to the lower order of the arithmetic processor, and is "1" when connected and "0" when not connected.
LAP # is the number of the arithmetic processor connected to the lower order of the arithmetic processor.

Numbers of arithmetic processors 10, 11, 12, 20, 21 are 0, 2, 4,
1, 3 and all arithmetic processors are configured. Since the arithmetic processor 10 is configured, V =
1, and since it is connected to the system controller 1, S =
1. There is no upper processor, so UAP # is Do
n't Care, and arithmetic processor 11 with number 2 in the lower order
Are connected, VL = 1 and LAP # = 2. Further, since the arithmetic processor 12 is configured, VL = 1, and since it is not connected to the system control device 1, S = 0,
Further, since the arithmetic processor 11 having the number 2 is connected to the upper level, UAP # 2 is used, and since the arithmetic processor is not connected to the lower level, VL = 0 and LAP # are Don't Care. Description of connection configuration information of other arithmetic processors is omitted. The V bit is updated to "0" by the system control processor 3 when the arithmetic processor is degraded.

With the above configuration, when a failure occurs in an arbitrary arithmetic processor, it is reported to the diagnostic processor 4, and the diagnostic processor 4 notifies the system control processor 3 that a failure has occurred in the arithmetic processor. The system control processor 3 refers to the connection configuration table 40, knows the arithmetic processor and the arithmetic processors that are subordinate to the arithmetic processor, and can collectively perform the necessary degradation of the arithmetic processors.

For example, when a failure occurs in the arithmetic processor 11 in the configuration shown in the connection configuration table 40, the failure processing control circuit 43 of the system control processor 3 is configured so that the arithmetic processor 12 having the number 4 is connected to the lower order from the connection configuration table 40. Then, the arithmetic processors 11 and 12 are collectively degraded, and the V bits of the words 2 and 4 of the connection configuration table 40 are set to 0.

〔The invention's effect〕

As described above, in the present invention, the system control processor notified of the occurrence of a failure in the arithmetic processor is
By referring to and updating the connection configuration table and controlling the necessary degrading processing of all the processors at once, the failure that occurs when the failing processor and its subordinate processors are individually degraded This has the effect of eliminating the processing overhead.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the information processing system of the present invention. 1 ... System control device, 2 ... Main memory device, 3 ... System control device, 4 ... Diagnostic processor, 10,11,12,20,21 ... Arithmetic processor, 30,31,32,33,34 ...... Fault detection notification circuit, 40 ...... Connection configuration table, 42 ...... Connection configuration circuit, 43,50 …… Fault processing control circuit, 100,101,102,103,110,111,112,120,121,210,211,212,22
0,221 …… Signal line.

Claims (1)

[Claims] 1. A system control device, a main memory device connected to the system control device, a system control processor,
In an information processing system including a diagnostic processor and a plurality of arithmetic processors, the plurality of arithmetic processors are connected in series to the system control device, and each independently reports a fault to the diagnostic processor. The diagnostic processor has a circuit and notifies the failure when a notification of a failure is received from a connection configuration circuit that holds a connection state between the plurality of operation processors and the failure detection notification circuit of the plurality of operation processors. The connection state held by the connection configuration circuit is updated so that the operation processors connected to the lower order of the operation processor are collectively disconnected, and the failure from the operation processor connected to the lower order of the operation processor that has notified the failure is reported. The fault processing control circuit that controls not to report to the system control processor The information processing system which is characterized in that.