JPH0797330B2 - Diagnostic circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diagnostic circuit for diagnosing normality / abnormality of a program or hardware in a system operating under the control of a CPU (central processing unit), and more specifically, to a predetermined circuit. The present invention relates to a fail-safe diagnostic circuit in which an alternating output is obtained as long as an operation is performed, and the alternating output is cut off when an abnormality occurs.

2. Description of the Related Art In a conventional CPU control system, when diagnosing and monitoring whether or not the operation of each part is normal, in order to diagnose whether the data handled by the CPU is normal or abnormal, a (data) diagnostic circuit is used. Is used. By the way, this data diagnostic circuit compares the data by one character each time the central processing unit reads the data from the memory or the like and writes the data, and the comparison is sequentially performed for each bit. As such a circuit, for example, a circuit has been proposed in which a pendulum circuit using a bidirectional shift register is used to check data at high speed.

Problems to be Solved by the Invention In addition to the diagnosis of the data itself as described above, monitoring the control of the entire system contributes to further improvement of the reliability of the system. An object of the present invention is to provide a (system) diagnostic circuit capable of diagnosing the control of the system from such a viewpoint.

Means for Solving the Problems In order to achieve the above object, in the present invention, a diagnostic circuit includes an input terminal (D), an output terminal (Q), and a clock terminal (C
K) equipped with a certain number of flip flops (FF1, FF2, FF
3, FF4) and an initial value setting means (INI), and the initial value setting means (INI) provides a predetermined logical value group in which at least one flipflop is different from other flipflops at the time of system startup. FF1, FF2, FF3, FF
4) is stored in each flip-flop (FF
1, FF2, FF3, FF4) each sequentially input the output terminal (Q) to the input terminal (D) of the flip-flop of the next stage to form a loop, and each flip-flop (FF1, FF2, FF4)
3, FF4) clock terminals (CK) are configured so that different output terminals of the CPU parallel data output terminal group are individually connected. The location is set and determined uniquely for each installation position, and is output from the CPU based on the fact that the diagnostic results of each part of the system in the CPU are normal.
1, FF2, FF3, FF4) control data for moving only the flip flops corresponding to the set position are sequentially input to each clock terminal (CK), and are sequentially input only during normal operation. Based on one set of the control data group, the arrangement of the logical values stored by each flip-flop (FF1, FF2, FF3, FF4) set by the initial value setting means (INI) is sequentially transferred only in normal operation. Cycle at a fixed cycle, and any flip-flop (FF1, FF2, FF3,
In FF4), the alternating output obtained during normal operation is used as the diagnostic output associated with normal system operation.

The operation initial value setting means (INI) stores a logical value group different from other flip flops in a predetermined flip flop, and each flip flop (FF1, FF2, FF3, FF) connected in a loop.
Two kinds of logical values are adjacent to 4).

In the subsequent control program, by sending a predetermined output to the parallel data output terminal of the CPU, the arrangement of the different logic values adjacent to each other can be set to each flip-flop (FF1, FF2, FF3, FF).
By controlling 4) to be sequentially transferred and circulated, an alternating output can be obtained as an output of an arbitrary flip-flop, so that a defect in the control program can be detected by the disappearance of the alternating output. Independent of the control program, the alternating output disappears even in the case of a failure of each part constituting the device of the present invention, so that it has a fail-safe characteristic.

Examples Hereinafter, the present invention will be described based on examples with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a diagnostic circuit for diagnosing an appropriate CPU control system according to the present invention.

The diagnostic circuit of the embodiment is composed of one latch circuit (L), four flip-flops (FF1, FF2, FF3, FF4) and a frequency dividing circuit (FD). Each flip (FF
1, FF2, FF3, FF4) are input terminal (D) and output terminal (Q)
And a clock terminal (CK), a set terminal (S) and a reset terminal (R).

The input and output of each flip-flop are connected in series in a multistage manner. That is, for example, the output terminal (Q) of the flip-flop (FF1) is connected to the input terminal (D) of the flip-flop (FF2) of the next stage. The output terminal (Q) of the flip-flop (FF4) at the final stage is sequentially input to the input terminal (D) and the frequency divider (F
D) and the first stage flip-flop (F
It is input so as to be fed back to the input terminal (D) of F1) and makes a loop to form a loop.

Each flip-flop (FF1, FF2, FF3, FF4) stores the content input to the input terminal (D) when the clock signal is input to the clock terminal (CK) and inputs it from the output terminal (Q). , So-called clock operation, each clock terminal (CK) of each flip-flop (FF1, FF2, FF3, FF4) is connected to the CPU via a latch circuit (L).
Different output terminals of the parallel data output terminal group are connected to each other and can be driven independently. Therefore, each flip-flop (FF
1, FF2, FF3, FF4) can operate in any combination.

Each flip-flop (FF1, FF2, FF3, FF4) also has a set terminal (S) and a reset terminal (R), and if there is an input to these terminals (S, R), it is forcibly supported. Output. In the embodiment circuit, initial value setting means (INI) is connected to both terminals.

The initial value setting means (INI) stores a predetermined logical value (described later) in each flip-flop only when the system is started. In the illustrated example, the flip-flop (FF1) is stored.
Reset terminal (R) and the remaining flip-flop (FF2, FF
The set terminal (S) of (3, FF4) is always connected (pulled up) to the power supply and the logical value "1"("H") is input, and the set terminal (S) of the flip-flop (FF1) and the remaining flip-flop. The same negative logic signal (RST) is input to the reset terminal (R) of (FF2, FF3, FF4) at system startup,
The held logical values of each flip-flop (FF1, FF2, FF3, FF4) are forcibly set to "1", "0", "0", "0" in order. The initial value input by the initial value setting means must be different from at least one flipflop in order to conform to the gist of the present invention. In other words, it is necessary that they are not all the same logical value.

(CPU) is a central processing unit such as a microprocessor, which can input 4-bit data signals (D1, D2, D3, D4) to the latch circuit (L), and accordingly, depending on the contents of 4 bits. 4 flip-flops (FF1, FF2, FF3, FF4) can be independently driven by individually controlling four clock signals (CK). As described above, the diagnostic circuit of the present invention is configured so that the flip-flop circuits connected in series in a loop form can be individually clocked according to the output from the CPU. With such a configuration,
As will be described later, the intended purpose of system diagnosis can be achieved together with the output of a predetermined data signal from the CPU.

Hereinafter, a CPU for appropriately using the diagnostic circuit of the present invention
The operation of the embodiment circuit will be described in detail together with the control on the side.

In order to operate the diagnostic circuit of the present invention, all the flip-flops connected in a loop are not all the same, in other words, the logical values discontinuous with respect to the connection order are kept in the loop while maintaining the order. CPU to cycle in order
The system control of the CPU is performed so that the process of outputting the data output from the side for each bit corresponding to the clock signal of each flip-flop is repeatedly included at a fixed cycle, and the output of any flip-flop among each flip-flop is used as the diagnostic output. If this diagnostic output is an alternating output, it is assumed that the control is operating normally and a constant output (no alternating output)
The system is diagnosed by detecting the occurrence of abnormalities.

That is, an example of system control will be described by taking the diagnostic circuit of the above-described embodiment as an example.On the CPU side, the diagnostic circuit described above is controlled in a predetermined order during a control process such as control of each part of the system and diagnosis of each part constituting the system. The process of driving with is included.
In the following example, for example, the above-mentioned diagnostic circuit controls not only the system diagnosis but also each part by controlling the driving so as to be driven in a constant cycle only when the diagnosis result of each part is normal, corresponding to the diagnosis result of each part. An example will be described in which the alternating output is cut off and an abnormal output is obtained even when the individual diagnosis result of is abnormal.

For such a diagnosis, in the embodiment circuit, for example, a clock signal corresponding to the data signal (D1 to D4) from the central processing circuit (CPU) is supplied from the latch circuit (L) to each of the flip-flops (FF1 to FF4). It is input to the clock signal terminal (CK) of. The clock signal output from the latch circuit (L) is a clock pulse only for a predetermined flip-flop in accordance with the test order of the memory and the timer as described above and corresponding to the test result (partial diagnosis result). If the test result is normal and the program operates normally, for example, the truth value “1” set in the flip-flop (FF1) is set to the flip-flop ( FF2), and after the next test, the truth value "1" set in the flip-flop (FF2) based on the data signal (clock signal for a predetermined flip-flop) from the CPU corresponding to the test order and the test result is It is designed to move to the flip-flop (FF3) of the stage. That is, the flip-flop is programmed in advance so as to sequentially shift "1" to the flip-flop of the next stage based on a predetermined clock signal output from the CUP via the latch circuit (L) which is a signal reflecting various test results. Has been converted. As described above, according to the present invention, the clock terminal of the flip-flop is set at a plurality of points during the diagnosis and other control processes of each part along with the progress of the program, and is uniquely determined according to each set position. Based on the result being normal, the CPU outputs the control data for the transfer operation of only the flip-flop corresponding to the set position among the flip-flops (FF1, FF2, FF3, FF4) at each clock terminal (CK). The flip-flops (FF1, FF2, FF3, FF4) set by the initial value setting means (INI) are stored on the basis of a series of a set of the control data that are sequentially input only during normal operation and are repeatedly input only during normal operation. Only when the logical values are arranged normally, the logical values are sequentially transferred in order and are circulated in a constant cycle. Therefore, if there is an abnormality in the partial diagnosis or if there is an abnormality in the operation of the program, "1" is not transferred (set) to the specified flip-flop, or "1" is set to the entire flip-flop and the alternation is performed. The output will be cut off.

Next, an example of the operation of this diagnostic circuit will be described with reference to FIGS. 2 and 3.

FIG. 2 shows the case where the flip-flop (FF1) has the truth value "1". In step 1, (FF
To erase the unnecessary "1" in 4), so to speak, set the truth value "0,0,0,1" in the latch circuit (L), and then set the truth value "0,0,0" in the latch circuit (L). The CPU outputs the data to set "0".

By this series of operations, if "1" that should originally be in (FF1) should be left in (FF4), it will be erased,
Eventually, the "1" in all flip flops disappears, and the alternating output stops.

Next, in step 2, the correct "1" of the flip-flop (FF1) is moved to the next flip-flop (FF2).
That is, for example, when the test result of the memory test is normal, the truth value "1" is shifted from (FF1) to (FF2). For this operation, the CPU outputs the truth value “1,1,” to the latch circuit (L) by outputting the data.
By setting 0,0 "and applying it to the predetermined flip-flops (FF1) and (FF2) as a clock pulse, subsequently setting the truth value" 0,0,0,0 "in the latch circuit (L). Is performed and the truth value “1” is set in (FF2), while (FF2)
1) is “0”. That is, "1" of (FF1) is shifted to (FF2).

By the above steps 1 and 2, one-time processing, that is, one flip-flop processing corresponding to one diagnostic result is completed.

Such an operation is performed in order for each flip-flop. That is, in the operation of (FF2), since "1" which should be in (FF2) is erased when it is in the previous stage (FF1), the truth value "1" is set in the latch circuit (L) as shown in FIG. 1,
After setting 0,0,0 ", the truth value" 0,0,0,0 "is set (FF1) and the invalid" 1 "is erased (step 1). ) To the truth value “0,1,1,0”
After setting, set the truth value “0,0,0,0” (FF2)
Shift "1" to (FF3).

Do the same for (FF3) and (FF4).

A series of operations from (FF1) to (FF4) completes diagnosis for one cycle. That is, for example, a total of four test results of the memory, the timer, the input unit and the output unit are diagnosed in this series of cycles. Therefore, if each of the above tests is normal, an alternating output is obtained from (FF4), and if it is abnormal, for example, the truth value “1” is set to the entire flip-flop (FF1, FF2, FF3, FF4). Or all are "0"
As a result, the alternating output is cut off, and the diagnosis of various tests is eventually judged by whether the alternating output is obtained or stopped.

In the embodiment described above, only four flip flops are shown. However, when the number of items to be checked is increased, a corresponding number of flip flops may be circulated and connected. That is, when five items to be checked are RAM (RAM), ROM (ROM), timer, input part data, and output part data, the number of flip-flops corresponding to the number of check items is five.
It suffices to connect them in series.

Effects of the Invention As described above, the diagnostic circuit of the control system using the CPU of the present invention has the input terminal (D) and the output terminal (Q).
And a predetermined number of flip-flops (FF1, FF2, FF3, FF4) equipped with a clock terminal (CK), sequentially input the output terminal (Q) to the input terminal (D) of the next flip-flop to make a loop. The flip-flops (FF1, FF2, FF3, FF4) are connected to different output terminals of the parallel data output terminal group of the CPU so that the above-mentioned predetermined signals are input to the clock terminals (CK) of each flip-flop. Further, the initial value setting means (INI) sets a predetermined logical value group in which at least one flip-flop is different from other flip-flops at the time of system startup, to each flip-flop (FF1, FF).
2, FF3, FF4), so that the output of any flip-flop can be diagnosed by performing system control by the CPU using an arbitrary program including a predetermined diagnostic program as described above. It can be used as an output, and in addition to various diagnostic results, the operation of the system control itself can be diagnosed, and the output is fail-safe, so that the reliability of the system can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a diagnostic circuit of the present invention, and FIG. 2 is a truth value for giving a latch circuit a clock pulse required when the first flip-flop has a truth value "1". 3 and FIG. 3 are views showing a list of data contents to be set in the latch circuit, which is necessary when the truth value is "1" for each flip-flop. (FF1, FF2, FF3, FF4): flip-flop, (INI): initial value setting means, (CPU): microprocessor, (CK): clock terminal, (D): input terminal, (Q): output terminal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuo Saito 1-13-8 Kamikizaki, Urawa-shi, Saitama Nihon Signal Co., Ltd. Yono factory (56) Reference JP-A-56-17444 (JP, A)

Claims (1)

[Claims] 1. A diagnostic circuit for a control system using a CPU, comprising an input terminal (D), an output terminal (Q) and a clock terminal (C).
K) equipped with a certain number of flip flops (FF1, FF2, FF
3, FF4) and an initial value setting means (INI), and the initial value setting means (INI) sets a predetermined logical value group in which at least one flipflop is different from other flipflops at the system startup. FF1,
FF2, FF3, FF4), and each flip-flop (FF1, FF2, FF3, FF4) has its output terminal (Q) as the input terminal (D) of the next flip-flop.
To form a loop, and the clock terminals (CK) of each flip-flop (FF1, FF2, FF3, FF4) are individually connected to different output terminals of the CPU parallel data output terminal group. Outputs from the CPU based on the fact that the diagnosis result of each part of the system in the CPU is normal because it is set at multiple points during the diagnosis of each part and other control processes as the program progresses and is uniquely determined according to each set position. Each flip-flop (FF1, FF
2, FF3, FF4) Control data for moving only the flip flop corresponding to the set position is sequentially input to each of the clock terminals (CK), and is sequentially repeated only during normal operation. Based on the control data group of, the arrangement of the logical values stored by each flip-flop (FF1, FF2, FF3, FF4) set by the initial value setting means (INI) is sequentially transferred in a fixed order only during normal operation and is constant. A diagnostic circuit for the CPU control system that circulates in cycles and uses the alternating output obtained only during normal operation with any flip-flop (FF1, FF2, FF3, FF4) as the diagnostic output associated with the system during normal operation.