JPH0797620B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a function arranged on a gate basic cell used in an internal region in a CMOS master slice type integrated circuit or a standard cell type integrated circuit. Regarding blocks.

[Conventional technology]

As an example of a conventional functional block of this type, a layout of a CMOS inverter circuit using two basic gate cells is shown in FIG. In FIG. 2, one gate basic cell 1
V _{DD in the} X direction in the P channel transistor region 2.
A power supply line 3 passes through and a polysilicon gate 4 is provided in the Y direction to have a source region 5 and a drain region 6. An N-channel transistor region 12 is passed through an X direction GND power supply line 13 and a Y direction polysilicon gate 14 is provided. It has 15 and a drain region 16.

Further, in FIG. 2, X indicates a contact, and O indicates a through hole for connecting the one-layer aluminum and the two-layer aluminum. As shown in the figure, a CMOS inverter circuit is constructed by connecting predetermined contacts using aluminum wirings 7 and 8. A contact 21 is generally defined as its output terminal. Wiring from here is usually done automatically using a CAD system, usually in close proximity to contact 21 and through hole.
22. From there, draw the wiring 23 in the Y direction by the second layer aluminum wiring, then place the through hole 24 and wire 25 in the X direction.
Is connected to the input terminals of the plurality of functional blocks in the next stage while using the first layer aluminum wiring, the second layer aluminum wiring, the through hole and the contact in this way.

[Problems to be solved by the invention]

In the above-mentioned conventional functional block, since the channel grid is defined so that automatic wiring can be performed, the wiring width of the aluminum wiring is uniquely determined, and it can be freely thinned,
I can't make it thick. Therefore, for example, the switching frequency of the above-mentioned CMOS inverter circuit becomes high, and the current (I) flowing in the signal line is proportional to the switching frequency,
Further, it cannot cope with an increase in proportion to the load capacitance (C) attached to the signal line. Further, the ON resistance (R) of the inverter circuit also changes the current flowing in the signal line.
In such a state, when the load capacity is large (specifically, the number of fan-outs (F / O) is large and the aluminum wiring length is long), and when operated at high speed, the signal line naturally flows. Since the current value becomes large and electromigration may occur in the aluminum wiring, there is a drawback that the load capacitance and the switching operation frequency are limited.

[Means for solving problems]

In the semiconductor integrated circuit of the present invention, a plurality of gate basic cells are arranged on a semiconductor chip, a wiring region defining a wiring channel is provided between the gate basic cells, and the arranged gate basic cells are arranged in the wiring channel. In a semiconductor integrated circuit that constitutes a logic circuit by connecting along a line, a functional block composed of a plurality of gate basic cells each having an output terminal The output terminal of each of the plurality of gate basic cells has a functional block connected between the output terminals, and metal wirings are led to the outside of the functional block. The plurality of derived metal wirings correspond to each other. It is connected to an input terminal of another functional block that operates.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 is a layout diagram of functional blocks according to an embodiment of the present invention. Portions common to those in FIG. 2 are indicated by the same number signals.
The difference from the conventional example of FIG. 2 is that the layout pattern is changed so that a plurality of equivalent output terminals can be secured, and the equivalent output terminals 31A and 31B are directly connected by aluminum wiring 30. is there.

By doing so, the contacts 31A and 31B can be used as equivalent output terminals depending on the operating frequency and the load capacitance. For example, when there is a large load capacity, a through hole 32A is placed in a grid near the output terminal 31A, a first layer aluminum wiring is connected between 31A and 32A, and a second layer aluminum wiring 33A is wired in the Y direction from the through hole 32A. Also, through hole 34A
In, the first layer wiring 35A is wired and connected to the input terminal of the other functional block, and the terminal 31B is also connected to the input terminal of the other functional block in the same manner. By thus dividing the load capacitance, the current density of the wiring from each output terminal can be reduced.

〔The invention's effect〕

As described above, according to the present invention, since the functional block has a plurality of equivalent output terminals connected by the metal wiring, when the functional block operates at high speed or the load capacity is large, the equivalent output terminals are used to output the output signal. By separating the lines, it is possible to prevent the current from concentrating extremely on one signal line, and to prevent the occurrence of electromigration to the aluminum wiring without increasing the wiring width of the signal line. There is.

[Brief description of drawings]

FIG. 1 is a layout diagram of functional blocks of a semiconductor integrated circuit of the present invention, and FIG. 2 is a layout diagram of conventional functional blocks.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/8238 27/092 27/118 H01L 21/82 M 21/88 Z

Claims (1)

[Claims] 1. A plurality of gate basic cells are arranged on a semiconductor chip, a wiring region defining a wiring channel is provided between the gate basic cells, and the arranged gate basic cells are arranged along the wiring channel grid. By connecting
In a semiconductor integrated circuit that constitutes a logic circuit, a functional block composed of a plurality of gate basic cells each having an output terminal, in which metal wiring is connected between the output terminals of the plurality of gate basic cells. A metal wiring is provided to the outside of the functional block from each of the output terminals of the plurality of gate basic cells, and the plurality of derived metal wirings are input terminals of other corresponding functional blocks. A semiconductor integrated circuit characterized by being connected to.