JPH0797626B2 - MIS type semiconductor memory device - Google Patents

Description

The present invention relates to an MIS type semiconductor memory device in which a memory cell is composed of one MIS type transistor and one capacitance, and more particularly to a semiconductor in which the memory cell is miniaturized. Regarding a storage device.

[Conventional technology]

Conventionally, a memory cell having a structure shown in FIG. 4 is known as a memory cell composed of one MIS type transistor and one capacitor formed in the groove.

In this example, a field oxide film is formed on the P-type semiconductor substrate 20.
21 is formed to define an element active region, a gate oxide film 22 and a groove are formed in this element active region, a capacitance insulating film 23 is formed inside this groove, and a capacitance section electrode 24 is formed to increase the capacitance. I am configuring. Also, in the device active region, a gate insulating film of a transistor and a gate electrode to be a word line are formed.
25 is formed, and then the source / drain 26 of the MIS transistor is formed to form a MIS type transistor. Then, an interlayer insulating film 27 is formed, and a bit line 28 in contact with the source 26 is formed on the insulating film 27 to form a memory cell.

[Problems to be solved by the invention]

In the conventional MIS type semiconductor memory device described above, the semiconductor substrate 2
It is necessary to perform patterning on the capacitor portion electrode 24 made of polycrystalline silicon or the like, the gate electrode 25 as the word line of the memory cell, and the wiring of the bit line 28 of the memory cell on the 0. Therefore, when these wirings are present on the surface of the semiconductor substrate, a region for forming the capacitor electrode 24 and the gate electrode 25 is particularly required, and an occupied area corresponding to this region is required. For this reason, when the memory cells are reduced in size for the purpose of high integration of the memory cells, it becomes difficult to secure the occupied area of these, and it becomes difficult to configure a high-capacity storage device.

It is an object of the present invention to provide an MIS type semiconductor memory device that enables miniaturization of memory cells and can configure a high capacity memory device.

[Means for solving problems]

The MIS type semiconductor memory device of the present invention includes a first semiconductor layer of opposite conductivity type formed on a semiconductor substrate of one conductivity type, and a semiconductor substrate of the same conductivity type as the semiconductor substrate formed on the first semiconductor layer. A second semiconductor layer and a third semiconductor layer formed on the second semiconductor layer and having an impurity concentration lower than that of the second semiconductor layer, and a MIS transistor is formed on the surface of the third semiconductor layer. On the other hand, a groove reaching the first semiconductor layer from the surface thereof is formed, and a capacitance portion is formed by the insulating film formed on the inner surface of the groove, the conductive member filled in the groove, and the third semiconductor layer. In addition, the conductive member is electrically connected to the first semiconductor layer on the bottom surface of the groove, and the first semiconductor layer is used as the common electrode of the capacitor section.

The gate electrode of the MIS transistor may be embedded in the upper groove of the capacitor electrode.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a vertical sectional view of the first embodiment of the present invention. First
In the figure, on the P-type semiconductor substrate 1, an N-type impurity diffusion layer 2,
A high-concentration P-type impurity diffusion layer 3 and a P-type impurity diffusion layer (epitaxial layer) 4 are sequentially formed, and then a field oxide film 5 defines an element active region. Then, a gate oxide film 6 and a groove are formed in the element active region, a capacitor insulating film 8 is formed on the side surface thereof, and a capacitor portion electrode 7 connected to the N-type impurity diffusion layer 2 on the bottom surface is formed. There is. The capacitor electrode 7 is not projected on the surface of the semiconductor substrate. Further, the N-type impurity diffusion layer 2 is connected to the capacitance portion extraction electrode 9 through another capacitance portion electrode 7A provided in another portion of the element active region. Further, a MIS type field effect transistor including a gate electrode 10 as a word line and an N type source / drain 11 is formed at a position adjacent to the capacitor electrode 7. Further, an interlayer insulating film 12 is formed on these and a bit line 13 is formed.

Next, a method for manufacturing the structure of FIG. 1 will be described with reference to FIGS.
The process will be described later with reference to the cross-sectional view shown in FIG.

First, as shown in FIG. 2 (a), the P-type semiconductor substrate 1 is doped with impurities such as phosphorus at about 1 × 10 ¹⁵ / cm ² by an ion implantation method, and then heat-treated at 1100 ° C. to 1200 ° C. The N-type impurity diffusion layer 2 having a depth of about 3 to 4 μm from the semiconductor surface is formed. Further, 5 × 10 ¹⁵ to 1 × 10 5 P type impurities such as boron are formed on the N type diffusion layer 2 by an ion implantation method.
Implantation of about ¹⁶ / cm ² and 0.5μ of high concentration P-type impurity diffusion layer 3
It is formed with a depth of about m.

Next, as shown in FIG. 2B, a P-type epitaxial layer 4 having a specific resistance of about 4 Ω · cm is formed on the high-concentration P-type impurity diffusion layer 3 with a thickness of about 4 to 5 μm.

Then, as shown in FIG. 2C, a field oxide film 5 of 6000 to 8000Å is formed in the element isolation region by using a selective oxidation method, and a gate oxide film 6 of 500 to 1000Å is formed in the active element region. Form. Then, a groove reaching the N-type impurity diffusion layer 2 is formed to a depth of about 5 to 6 μm in a part of the active element region and another region adjacent to the element active region, and the groove inner surface is subjected to an oxidation treatment. A capacitance insulating film 8 is formed in a region including the.

Next, as shown in FIG. 2 (d), polycrystalline silicon 7a is deposited on the capacitive insulating film 8 with a film thickness of 1/4 or less of the minimum groove size, and the polycrystalline silicon on the bottom surface of the groove is formed by reactive ion etching. The silicon 7a and the capacitor insulating film 8 are removed in a state where the polycrystalline silicon attached to the side wall of the groove is left as it is.

Next, as shown in FIG. 2 (e), the inside of the groove is completely filled with polycrystalline silicon or the like to form the capacitor electrode 7.

Thereafter, as shown in FIG. 1, the gate electrode 10 to be the word line of the memory cell, the interlayer insulating film 12, the source / drain 11 of the transistor, and the bit line 13 are formed to form the memory cell.

According to this embodiment, the capacitor part electrode 7 is electrically connected to the N-type impurity diffusion layer 2 at the bottom surface 7 ', and is electrically connected to the capacitor part electrode of another memory cell through the diffusion layer 2. Further, the N-type impurity diffusion layer 2 is electrically connected to another capacitance part electrode 7A formed at another location, and is drawn out to the outside via the capacitance part extraction electrode 9 provided on the capacitance part electrode 7A. Therefore, the polycrystalline silicon forming the capacitor electrode 7 does not exist on the substrate, the occupied area of this portion can be reduced, and the occupied area of the memory cell can be reduced to achieve miniaturization.

FIG. 3 is a sectional view of the second embodiment of the present invention. In this embodiment, the upper surface of the capacitor electrode 7 of the first embodiment is recessed,
After forming an insulating film, here is the gate electrode of the transistor
The MIS transistor is formed by forming 10A and using the insulating film formed on the side wall of the capacitor portion as the gate insulating film. In this embodiment, it is not necessary to form the gate electrode on the substrate as in the first embodiment, and there is an advantage that the area occupied by one memory cell can be further reduced.

〔The invention's effect〕

As described above, according to the present invention, the capacitance portion forming the memory cell of the MIS type semiconductor memory layer is formed by the insulating film formed on the inner surface of the groove reaching the semiconductor layer of the opposite conductivity type from the surface and the conductivity filled in the groove. Since the conductive member is electrically connected to the semiconductor layer of the opposite conductivity type at the bottom surface of the groove, the capacity layer electrode, and further, the wiring layer existing on the upper part of the substrate such as the gate electrode is reduced, and the memory cell There is an effect that the device can be miniaturized and the storage capacity can be increased.

Further, in the present invention, in the capacitor part, the capacitor part electrode connected to the MIS transistor serves as the outer wall of the groove in the third semiconductor layer, and thus is formed of the conductive member in the groove connected to the first semiconductor layer. By setting the potential of the counter electrode higher than that of the capacitor electrode, the surface inversion layer can be formed to accumulate charges. Further, since there is a second semiconductor layer having a relatively high impurity concentration between the capacitor electrode and the first semiconductor layer connected to the counter electrode, both electrodes are provided with the second semiconductor layer. Separated by semiconductor layers.

[Brief description of drawings]

FIG. 1 is a sectional view of the first embodiment of the present invention, and FIG. 2 (a).
2 (e) is a sectional view showing the manufacturing method of the first embodiment in the order of steps, FIG. 3 is a sectional view of the second embodiment, and FIG. 4 is a sectional view of a conventional example. 1 ... P-type semiconductor substrate, 2 ... N-type impurity diffusion layer, 3 ...
... High-concentration P-type impurity diffusion layer, 4 ... P-type impurity diffusion layer (epitaxial layer), 5 ... Field oxide film, 6 ...
... Gate oxide film, 7,7A ... Capacitance part electrode, 8 ... Capacitance insulating film, 9 ... Capacitance part extraction electrode, 10,10A ... Gate electrode (word line), 11 ... Source / drain, 12 ... … Interlayer insulation film, 13 …… bit line, 20 …… P-type semiconductor substrate, 21 ……
Field oxide film, 22 ... Gate oxide film, 23 ... Capacitance insulating film, 24 ... Capacitance part electrode, 25 ... Gate electrode, 26 ... Source / drain, 27 ... Interlayer insulating film, 28 ... Bit line .

Claims (1)

[Claims] 1. A MIS type semiconductor memory device comprising a memory cell composed of a MIS transistor and one capacitance section, wherein a first semiconductor layer of opposite conductivity type is formed on a semiconductor substrate of one conductivity type, and A second semiconductor layer formed on the first semiconductor layer and having the same conductivity type as the semiconductor substrate; and a third semiconductor layer formed on the second semiconductor layer and having an impurity concentration lower than that of the second semiconductor layer. Forming a groove reaching the first semiconductor layer from the surface of the third semiconductor layer and forming a MIS transistor on the surface of the third semiconductor layer. A capacitive portion is formed by the film and a conductive member filled in the groove and the third semiconductor layer, and the conductive member is electrically connected to the first semiconductor layer at the bottom surface of the groove, and the first semiconductor layer is formed. Is a common electrode of the capacitance section, That the MIS-type semiconductor memory device.