JPH0797704B2 - Method for manufacturing multilayer printed wiring board - Google Patents
Method for manufacturing multilayer printed wiring boardInfo
- Publication number
- JPH0797704B2 JPH0797704B2 JP29275389A JP29275389A JPH0797704B2 JP H0797704 B2 JPH0797704 B2 JP H0797704B2 JP 29275389 A JP29275389 A JP 29275389A JP 29275389 A JP29275389 A JP 29275389A JP H0797704 B2 JPH0797704 B2 JP H0797704B2
- Authority
- JP
- Japan
- Prior art keywords
- via hole
- multilayer
- hole
- manufacturing
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000000034 method Methods 0.000 title claims description 14
- 229920006015 heat resistant resin Polymers 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 4
- 229920001187 thermosetting polymer Polymers 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 238000007639 printing Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 238000005553 drilling Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229930185605 Bisphenol Natural products 0.000 description 1
- 230000004308 accommodation Effects 0.000 description 1
- WNROFYMDJYEPJX-UHFFFAOYSA-K aluminium hydroxide Chemical compound [OH-].[OH-].[OH-].[Al+3] WNROFYMDJYEPJX-UHFFFAOYSA-K 0.000 description 1
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical compound C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層印刷配線板の製造方法に関し、特に高密度
実装のためにヴィアホールの一部の導体層を分割し、複
数のヴィアホールを同一格子上に有する多層印刷配線板
の製造方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a multilayer printed wiring board, and in particular, for the purpose of high-density mounting, a part of a conductor layer of a via hole is divided to form a plurality of via holes. The present invention relates to a method for manufacturing a multilayer printed wiring board having the same grid.
LSI,IC等の高集積化,電子機器の高性能化と経済性向上
のために多層印刷配線板(以下、多層板と称す)の高密
度化が進展している。High density integration of multilayer printed wiring boards (hereinafter referred to as “multilayer boards”) is progressing in order to achieve high integration of LSIs and ICs, high performance of electronic devices and improvement of economic efficiency.
多層板の高密度化に対して、主に、2つの対応が図られ
ている。第1に導体層数の増加、すなわち、高多層化で
あり、第2の対応が基本格子間への多配線化である。し
かしながら、第1の対応では、層間の導体層を接続する
ヴィアホールの増加になり、第2の対応の多配線化は、
配線収容性を著しく制限する。そのため、ヴィアホール
径の小径化,配線導体の細線化等で対応しているが、い
ずれも多層板の製造性を阻害している。Two main measures are taken to increase the density of multilayer boards. The first is the increase in the number of conductor layers, that is, the increase in the number of layers, and the second is the increase in the number of wirings between the basic lattices. However, in the first measure, the number of via holes connecting the conductor layers between layers is increased, and in the second measure, the increase in the number of wiring is
Wiring capacity is severely limited. Therefore, the reduction of the via hole diameter and the thinning of the wiring conductor have been dealt with, but these all hinder the manufacturability of the multilayer board.
この問題を解決する方法として、ヴェリッドヴィアホー
ル,サーフェス(ブラインド)ヴィアホールを有する多
層板が考案されている。As a method for solving this problem, a multilayer board having a viad via hole and a surface (blind) via hole has been devised.
以下に、代表的な製造方法を第3図(A)〜(E)を例
にとり説明する。Hereinafter, a typical manufacturing method will be described with reference to FIGS. 3A to 3E as an example.
第3図(A)に示すように、まず、積層板にドリル加
工,パネルめっきを行ない、サーフェスヴィアホール13
aとなるべくヴィアホールを形成し、次に、フォト印刷
法によって、片面のみに内層回路パターン14aを形成
し、サーフェスヴィア内層板15を作製する。As shown in FIG. 3 (A), first, the laminated plate is subjected to drilling and panel plating, and then the surface via hole 13
A via hole is formed as much as possible, and then an inner layer circuit pattern 14a is formed only on one surface by a photo printing method to produce a surface via inner layer plate 15.
又、同じく、第3図(B)に示すように、積層板にドリ
ル加工,パネルめっきを行ない、ヴェリッドヴィアホー
ル16となるべくヴィアホールを形成し、次にフォト印刷
法によって両面に内層回路パターン14b,14cを形成し、
ヴェリッドヴィア内層板17を作製する。Similarly, as shown in FIG. 3 (B), drilling and panel plating are performed on the laminated plate to form via holes as much as the verid via holes 16, and then the inner layer circuit pattern is formed on both sides by photo printing. Forming 14b and 14c,
The Velidvia inner layer board 17 is produced.
次に、第3図(C)に示すように、先の2種の内層板15
a,15b,17をプリプレグ6a,6bを介挿されてセットする。Next, as shown in FIG. 3 (C), the two inner layer plates 15 described above are used.
The a, 15b and 17 are set by inserting the prepregs 6a and 6b.
次に、第3図(D)に示すように、加熱,加圧工程を経
て、各内層板15a,15b,17がプリプレグ層9a,9bによって
一体化した多層成型基板10を得る。Next, as shown in FIG. 3 (D), a multilayer molded substrate 10 in which the respective inner layer plates 15a, 15b, 17 are integrated by the prepreg layers 9a, 9b is obtained through the heating and pressing steps.
次に、第3図(E)に示すように、多層成型基板10の所
定の箇所に貫通孔を穿孔しパネルめっき層18a,18b,18c
を施し、貫通ヴィアホール11を形成し、フォト印刷加工
を行なう事により、サーフェスヴィアホール13a,13bヴ
ェリッドヴィアホール16を有する従来の製造方法による
多層板12を得ていた。Next, as shown in FIG. 3 (E), through holes are drilled in predetermined positions of the multilayer molded substrate 10 to form the panel plating layers 18a, 18b, 18c.
Then, the through via hole 11 is formed, and photo-printing processing is performed to obtain the multilayer board 12 having the surface via holes 13a and 13b and the buried via hole 16 by the conventional manufacturing method.
又、サーフェスヴィアホールには、通常の銅張多層板を
形成し、外層面から半貫通孔をN/Cドリラー,レーザー
加工等によって穿設し、その後、通常のパネルめっき,
フォト印刷加工を施して、半貫通穴により、外層と外層
直下の内層を接続させる事により、サーフェスヴィアホ
ールを得る製造方法も知られている(図示略)。In addition, a normal copper clad multilayer board is formed in the surface via hole, and a semi-through hole is drilled from the outer surface by N / C drilling, laser processing, etc., and then normal panel plating,
There is also known a manufacturing method (not shown) in which a surface via hole is obtained by performing a photo printing process and connecting an outer layer and an inner layer immediately below the outer layer with a semi-through hole.
上述した従来の多層板の製造方法には、以下のような欠
点がある。The above-described conventional method for manufacturing a multilayer board has the following drawbacks.
まず、サーフェスヴィアホール,ヴェリッドヴィアホー
ル内に充填される樹脂は、プリプレグに含まれる樹脂の
みに依存している。従って、内層板の厚みはプリプレグ
層と同一の厚み程度しか得られず、この種の内層板の厚
みは、最大でも0.3〜0.4mm位であり多層化する事は、ほ
ぼ不可能であった。First, the resin filled in the surface via hole and the buried via hole depends only on the resin contained in the prepreg. Therefore, the thickness of the inner layer plate is only about the same as that of the prepreg layer, and the thickness of this type of inner layer plate is about 0.3 to 0.4 mm at the maximum, and it is almost impossible to form a multilayer.
従って、通常10層板を超える多層板で同一格子上にヴィ
アホールを構成する場合は、両面構成での内層板に於い
て、サーフェスヴィアホール及びヴェリッドヴィアホー
ルを、又は、貫通スルーホールを形成し、ヴィアホール
として使用するという、大別して2種類の方法しかな
く、特に、後者の貫通ヴィアホールは、一格子点上に一
ホールしか配置できず、高多層化する程配線収容性が不
利になるヴィアホールネック問題を生じていた。Therefore, when constructing via holes on the same lattice with multilayer plates that normally exceed 10 layer plates, surface via holes and verid via holes or through through holes are formed on the inner layer plate with double-sided structure. However, there are roughly two types of methods of using it as a via hole. In particular, in the latter through via hole, only one hole can be arranged on one grid point, and the higher the number of layers, the more disadvantageous the wiring accommodation becomes. Was causing a via hole neck problem.
本発明の目的は、配線収容性が良く、高密度配線が可能
な多層板の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a multilayer board which has good wiring accommodability and enables high-density wiring.
本発明の多層印刷配線板の製造方法は、両面又は多層構
成からなる積層板にスルーホール加工,外層回路形成を
施した後、ペースト状耐熱性樹脂を前記積層板の表裏両
全面に塗布し、併わせて、前記スルーホール内にも充填
させた後熱硬化させ、中間積層体を形成する工程と、少
なくとも2組の該中間積層体をプリプレグを介挿させて
加熱加圧成型する工程とを含んで多層化成型される。The method for producing a multilayer printed wiring board according to the present invention is a through-hole process for a laminated board having a double-sided or multi-layered structure, an outer layer circuit is formed, and a paste-like heat resistant resin is applied to the entire front and back surfaces of the laminated board. At the same time, a step of forming an intermediate laminated body by filling the inside of the through hole and then thermosetting it, and a step of inserting at least two sets of the intermediate laminated body by heat and pressure molding. It is molded in multiple layers including.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(A)〜(E)は本発明の第1の実施例の製造方
法を説明する工程順に示した縦断面図である。1 (A) to 1 (E) are vertical cross-sectional views showing the manufacturing process of the first embodiment of the present invention in the order of steps.
第1の実施例は、第1図(A)に示すように、予め、任
意の内層導体1a,1bを有する積層成型した積層板2(今
回は4層板にて試作した)の任意の箇所にスルーホール
加工を施し、将来分割されたヴィアホールとなるべく分
割ヴィアホール3を形成する。In the first embodiment, as shown in FIG. 1 (A), an arbitrary portion of a laminated plate 2 (trial-produced as a 4-layer plate this time) which is previously laminated and has arbitrary inner layer conductors 1a and 1b is used. Through-hole processing is performed to form the divided via holes 3 as much as possible divided via holes in the future.
次に、第1図(B)に示すように、ビスフェノール型エ
ポキシ樹脂に水酸化アルミニウム20〜50%配合させたペ
ースト状の耐熱性樹脂4aをロールコーターにより分割ヴ
ィアホール3に充填すると同時に、併わせて積層板2の
表裏にも耐熱性樹脂4aを塗布する。その後、温度150℃,
90分間ベーキング処理を行ない熱硬化させ、中間積層板
5aを形成する。Next, as shown in FIG. 1 (B), a paste-type heat-resistant resin 4a in which bisphenol type epoxy resin is mixed with aluminum hydroxide in an amount of 20 to 50% is filled in the divided via holes 3 by a roll coater, and at the same time, At the same time, the heat-resistant resin 4a is also applied to the front and back of the laminated plate 2. After that, the temperature is 150 ℃,
90 minutes baking process, heat curing, intermediate laminate
Form 5a.
次に、第1図(C)に示すように、2組の中間積層板5
a,5bを準備し、プリプレグ6a,6bを介挿させ、最外層に
厚み18μmの銅箔7a,7bを配置する。尚、一方の中間積
層板5bの表面にはパターン8を配置させた。Next, as shown in FIG. 1 (C), two sets of intermediate laminated plates 5
a, 5b are prepared, prepregs 6a, 6b are inserted, and copper foils 7a, 7b having a thickness of 18 μm are arranged on the outermost layer. The pattern 8 was arranged on the surface of one of the intermediate laminated plates 5b.
次に、第1図(D)に示すように、加熱加圧成型工程を
経て中間積層板5a,5bがプリプレグ層9a,9b,9cによって
一体化された多層成型基板10を得る。Next, as shown in FIG. 1 (D), a multilayer molded substrate 10 in which the intermediate laminated plates 5a, 5b are integrated by the prepreg layers 9a, 9b, 9c is obtained through a heating and pressure molding process.
次に、第1図(E)に示すように、先の多層成型基板10
のパターン8と電気的接続が可能な所定の箇所に従来法
によるスルーホール加工,フォト印刷加工を施して、貫
通ブィアホール11を形成する事により、第1の実施例に
よる多層板12を得る。Next, as shown in FIG. 1 (E), the above-mentioned multilayer molded substrate 10
By applying through-hole processing and photo-printing processing according to the conventional method to the predetermined portions that can be electrically connected to the pattern 8 to form the through via holes 11, the multilayer board 12 according to the first embodiment is obtained.
第2図(A)〜(D)は本発明の第2の実施例の製造方
法を説明する工程順に示した縦断面図である。2 (A) to 2 (D) are longitudinal sectional views showing the manufacturing method of the second embodiment of the present invention in the order of steps.
第2の実施例は、まず、第2図(A)に示すように、第
1の実施例と同一の製造方法により、中間積層板5aを形
成する。In the second embodiment, first, as shown in FIG. 2A, the intermediate laminated plate 5a is formed by the same manufacturing method as that of the first embodiment.
次に、第2図(B)に示すように、第1の実施例と同様
に、2組の中間積層板5a,5bをプリプレグ6a,6b,6cを介
挿させて、銅箔7a,7bを最外層に配置する。Next, as shown in FIG. 2 (B), as in the first embodiment, two sets of the intermediate laminated plates 5a, 5b are inserted through the prepregs 6a, 6b, 6c to form the copper foils 7a, 7b. Is placed on the outermost layer.
次に、第2図(C)に示すように、加熱加圧成型工程を
経てプリプレグ層9a,9b,9cで一体化した多層成型基板10
を得る。Next, as shown in FIG. 2 (C), a multilayer molded substrate 10 integrated with prepreg layers 9a, 9b, 9c through a heating and pressure molding process.
To get
次に、第1図(D)に示すように、第1の実施例と同様
の工法で貫通ヴィアホール11を形成すると同時に、最外
層側から、パターン8a,8bと電気的接続が可能となる深
さまでN/Cドリラーで半貫通孔を形成し、パネルめっ
き,フォト印刷加工を施して、サーフェスヴィアホール
13a,13bを形成し、多層板12を得る。Next, as shown in FIG. 1 (D), the through via hole 11 is formed by the same method as that of the first embodiment, and at the same time, the patterns 8a and 8b can be electrically connected from the outermost layer side. A semi-through hole is formed to the depth with an N / C driller, panel plating and photo printing are applied, and a surface via hole is formed.
13a and 13b are formed to obtain the multilayer plate 12.
この実施例においては、従来方法によるサーフェスヴィ
アホールの加工方法との組み合わせにより、分割ヴィア
ホールと外層パターンとの配線チャンネルを効率的に、
且つ、数多くとれるので、より高密度化が図れる利点が
ある。In this embodiment, a wiring channel between the divided via hole and the outer layer pattern can be efficiently provided by combining with the conventional method of processing the surface via hole.
Moreover, since a large number can be obtained, there is an advantage that a higher density can be achieved.
以上説明したように本発明は、同一格子上の貫通スルー
ホールを分割することにより、以下に列挙する効果があ
る。As described above, the present invention has the effects listed below by dividing the through-holes on the same lattice.
(1) 貫通スルーホールをヴィアホールとして使用す
る際、同一格子点上に分割されたヴィアホールとして配
置でき、配線収容性が向上し高密度配線が可能となる。(1) When the through-holes are used as via holes, they can be arranged as divided via holes on the same lattice point, the wiring accommodability is improved, and high-density wiring is possible.
(2) 板厚の厚い高多層板を任意に複数枚一括成型す
る事が可能となり、特に、両面に表面実装部品が大量に
搭載される場合には、同一層面の配線はサーフェスヴィ
アホールとの組み合わせで分割されたヴィアホール配線
を施し、表裏間の配線は貫通スルーホール型のヴィアホ
ールで配線を施す事により、飛躍的に配線収容性を向上
させる事が可能である。(2) It is possible to mold multiple high-thickness multi-layer boards with a large thickness, and especially when a large number of surface mount components are mounted on both sides, the wiring on the same layer surface should be connected to the surface via hole. It is possible to dramatically improve the wiring accommodating property by providing the via hole wiring divided by the combination and providing the wiring between the front and back sides by the through-hole type via hole.
第1図(A)〜(E)は本発明の第1の実施例の製造方
法を説明する工程順に示した縦断面図、第2図(A)〜
(D)は本発明の第2の実施例の製造方法を説明する工
程順に示した縦断面図、第3図(A)〜(E)は従来の
製造方法の一例を説明する工程順に示した縦断面図であ
る。 1a,1b,1c,1d……内層導体、2……積層板、3a,3b……分
割ヴィアホール、4a,4b……耐熱性樹脂、5a,5b……中間
積層板、6a,6b,6c……プリプレグ、7a,7b……銅箔、8a,
8b……パターン、9a,9b,9c……プリプレグ層、10……多
層成型基板、11……貫通ヴィアホール、12……多層板、
13a,13b……サーフェスヴィアホール、14a,14b,14c,14d
……内層回路パターン、15a,15b……サーフェスヴィア
内層板、16……ヴェリッドヴィアホール、17……ヴェリ
ッドヴィア内層板、18a,18b,18c……パネルめっき層。1 (A) to 1 (E) are longitudinal sectional views showing the manufacturing method of the first embodiment of the present invention in the order of steps, and FIGS. 2 (A) to 2 (E).
(D) is a longitudinal sectional view showing the manufacturing method of the second embodiment of the present invention in the order of steps, and FIGS. 3 (A) to (E) are shown in the order of steps explaining an example of the conventional manufacturing method. FIG. 1a, 1b, 1c, 1d …… Inner layer conductor, 2 …… Laminated plate, 3a, 3b …… Divided via holes, 4a, 4b …… Heat resistant resin, 5a, 5b …… Intermediate laminated plate, 6a, 6b, 6c …… Prepreg, 7a, 7b …… Copper foil, 8a,
8b ... Pattern, 9a, 9b, 9c ... Prepreg layer, 10 ... Multilayer molded substrate, 11 ... Through via hole, 12 ... Multilayer board,
13a, 13b …… Surface via hole, 14a, 14b, 14c, 14d
...... Inner layer circuit pattern, 15a, 15b …… Surface via inner layer board, 16 …… Velid via hole, 17 …… Velid via inner layer board, 18a, 18b, 18c …… Panel plating layer.
Claims (1)
ホール加工,外層回路形成を施した後、ペースト状耐熱
性樹脂を前記積層板の表裏両全面に塗布し、併わせて、
前記スルーホール内にも充填させた後熱硬化させ、中間
積層体を形成する工程と、少なくとも2組の該中間積層
体をプリプレグを介挿させて加熱加圧成型する工程とを
含んで多層化成型することを特徴とする多層印刷配線板
の製造方法。1. A laminated plate having a double-sided or multi-layered structure is subjected to through-hole processing and outer layer circuit formation, and then a paste-like heat-resistant resin is applied to the entire front and back surfaces of the laminated plate, and both are combined.
A multilayer structure including a step of filling the inside of the through hole and then thermosetting to form an intermediate laminated body, and a step of inserting at least two sets of the intermediate laminated body through a prepreg and heating and pressurizing the intermediate laminated body. A method for manufacturing a multilayer printed wiring board, which comprises molding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29275389A JPH0797704B2 (en) | 1989-11-09 | 1989-11-09 | Method for manufacturing multilayer printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29275389A JPH0797704B2 (en) | 1989-11-09 | 1989-11-09 | Method for manufacturing multilayer printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03152996A JPH03152996A (en) | 1991-06-28 |
| JPH0797704B2 true JPH0797704B2 (en) | 1995-10-18 |
Family
ID=17785893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29275389A Expired - Fee Related JPH0797704B2 (en) | 1989-11-09 | 1989-11-09 | Method for manufacturing multilayer printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0797704B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0669660A (en) * | 1992-03-26 | 1994-03-11 | Nec Corp | Printed wiring board and its manufacture |
| JP2003204157A (en) * | 2001-12-28 | 2003-07-18 | Toshiba Corp | Multilayer printed wiring board, electronic device mounted with multilayer printed wiring board, and method of manufacturing multilayer printed wiring board |
| JP5430002B2 (en) * | 2010-08-31 | 2014-02-26 | 京セラSlcテクノロジー株式会社 | Wiring board and manufacturing method thereof |
-
1989
- 1989-11-09 JP JP29275389A patent/JPH0797704B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03152996A (en) | 1991-06-28 |
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