JPH0797743B2 - Majority logic circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a majority logic circuit that corrects a transmission error by determining a majority of data in which the same contents are continuously transmitted.

[Prior Art] In a system for transmitting data using radio such as a car telephone, bit errors occur continuously due to fading and static electricity phenomena. As one of the methods of correcting this bit error, there is a method of continuously transmitting the data of the same content an odd number of times and reproducing the received data by obtaining a majority decision of the data transmitted on the receiving side. In order to realize this error correction method, a means for requesting a majority decision from the receiver is required. Generally, this means is conventionally performed by software.

In this software processing, the sent data is temporarily stored in the memory, after all the data is received, the majority decision processing is performed to check the corresponding bit and judge which of "0" and "1" is more. Was being done. Since data is sent continuously, there is a problem in that this majority processing must be executed at all times and the load on the CPU increases.

If the majority decision means is made into a circuit, the above problem can be solved. This majority logic circuit is well known. But,
When a majority decision is made on the data sent continuously, it is necessary to store all the data for which a majority decision should be taken, which causes a problem of an increase in the memory circuit.

Japanese Unexamined Patent Publication No. 61-66409 is disclosed as a conventional technique for solving the above problem. This is AND gate, OR gate and m
This is a circuit configuration in which n sets of combination circuits with shift registers in stages are used to obtain a majority decision of continuous transmission data up to 2n-1 times continuous transmission.

[Problems to be Solved by the Invention] As described above, the majority processing by software processing has a problem that the processing time is long and the load on the CPU is large. In addition, there is a problem in that the number of shift registers is large and the circuit scale is increased in making the circuit. Also in the above-mentioned conventional technique, n sets of shift registers are required for 2n-1 continuous data.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a majority logic circuit in which the number of shift registers required is reduced and which can be easily integrated into an IC.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention, as shown in FIG. 1A, provides an m-bit serial data transmitted continuously (2n−1) times (n ≧ 2). In a majority logic circuit for taking a majority decision of data, a shift register of m stages having a k-bit configuration, 1-bit data corresponding to the serial data is sequentially added to k-bit output data of the shift register, and the addition result is An adding means for inputting to the shift register, a detecting means for detecting that the k-bit output data of the shift register coincides with a predetermined value s, and an adding operation of the adding means according to a coincidence detection signal of the coincidence detecting means. comprising a prohibiting means for prohibiting, and initialization means for initializing all (s-n) of m k-bit data of the shift register, wherein k satisfies 2 ^k -1 ≧ n Those were Unishi.

The 1-bit data that the adding means adds to the k-bit output data of the shift register may be the serial data itself or its inverted data.

The adding means permits, for example, a preset counter that sets an input value according to a setting request signal and increments the set value by a counting clock, and an increment operation of the counter by a value of 1-bit data corresponding to the serial data. Alternatively, it may be constituted by a control means for prohibiting and a timing generating means for outputting the setting request signal and the counting clock in synchronization with the transmission timing of the 1-bit data.

The initialization can be easily performed by resetting the shift register when the initial data is 0, for example. When the initial data is not 0, the initial data can be forcibly shifted and input to the shift register.

In the present specification, the term “addition” is understood in a broad sense and includes subtraction.

[Operation] In the above-mentioned configuration, the adding means functions to count the number of "1" or "0" for each of the same-order bits of the transmitted continuous transmission data. The counting result up to each time is stored in the m-stage shift register instead of the counting result up to the previous time. Since this counting result is further shifted by m stages in the shift register and set again as the initial value of the adding means, it is possible to cumulatively count bit data that arrives every m bits. At the start of data transmission, the shift register is initialized to sn by the initialization means. Further, when the count value reaches s by the function of the detecting means and the prohibiting means, the addition, that is, the counting operation is prohibited, so that the number of "1" or "0" of 2n-1 consecutively transmitted data is n or more. In this case, the count value is kept as s. Therefore, majority logic can be obtained by receiving all the data and checking whether the value stored in the shift register is s.

Thus, since the majority logic is obtained from the count value stored in the shift register, up to 2 × (2 ^k −1) −1 = 2 ^{k + 1} −3 continuous transmission using the k-bit m stage shift register. You can get the majority logic of the data.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG. 1B.

<First Embodiment> The first embodiment shown in FIG. 1B is for obtaining a majority logic of 40-bit data which is continuously transmitted five times.

In FIG. 1, a data signal a and a clock signal b are signals from a data demodulation circuit not shown in FIG. This data demodulation circuit is a circuit for reproducing the NRZ data signal a and the clock signal b from the received signal. Here, it is assumed that the data signal a changes at the fall of the clock signal b. The reset signal r is given in synchronization with the continuous transmission start timing of the data a, which is also output from the data demodulation circuit. The circuit 1 is a 40-bit shift register for 2 bits, and the shift operation is performed at the rising edge of the clock signal b. A reset signal r is input to the reset terminal of the shift register 1, and the contents of the shift register 1 are all initialized to "0" by the signal r at the start of transmission of the data a. The circuit 2 is an addition circuit corresponding to the addition means, and the signals g1 and g2
And the signal c is added to the shift register 1, and the resulting signals e1 and e2 are output to the shift register 1. The signals e1, e2 and g1, g2 are 2
It is a decimal number and takes values from 0 to 3 (decimal). Circuit 3
Is an AND gate corresponding to the detecting means, and outputs a detection signal h when the output value of the shift register 1 is 3.
The circuit 4 is an AND gate corresponding to a prohibition means, and forcibly sets the signal b to the adder circuit 2 to "0" to prohibit the addition operation of the adder circuit 2 when the detection signal h becomes "1". Is. The circuit 5 is an inverter.

Hereinafter, the operation of this embodiment will be described in detail with reference to FIG. FIG. 2 is an operation timing chart showing an example of the operation of this embodiment. The data a changes in synchronization with the falling edge of the data clock b, and the signals g1 and g2 also change in synchronization with the rising edge of the data clock b because the shift register 1 operates at the rising edge of the data clock b. Further, in synchronization with this, the signals e1 and e2 are stored in the shift register 1. As shown in FIG. 2, the values of the signals g1 and g2 are 0 to
In the case of 2, the data a becomes the data c as it is, so that the values of the signals e1 and e2 are
It is the added value of g2 and the data a. When the values of the signals g1 and g2 become 3, the output signal h of the AND gate 3 which is the detecting means becomes "1". In response to this, the signal c is forcibly set to "0" by the AND gate 4 which is a prohibition means. Therefore, when the values of the signals g1 and g2 are 3, the values of the output signals e1 and e2 of the adder circuit are 3 regardless of the value of the data a, that is,
This is the same as the prohibition of the adding operation of the adding circuit 2.

Table 1 is a table showing the relationship between the input data and the output data of the adder circuit 2. As you can see from this table, adder circuit 2
Adds the data a to the addition result (input) output from the shift register 1 up to that point. When the addition result becomes 3, the addition operation is stopped and the value is held in the shift register 1. That is, in the embodiment shown in FIG. 1B, the number of “1” s of the transferred data is counted for each corresponding bit, and when there are three or more “1” s, 3 is stored in the shift register 1. It will be. The basic operation of this embodiment has been described above.

Next, it will be shown that the majority logic is obtained by this embodiment.

First, it is assumed that the reset signal r is input prior to data transmission and the contents of the shift register 1 are all initialized to "0". When the data transmission is started, both the data a and the clock signal b are output from the data demodulation circuit. Since the content of the shift register 1 is "0", the first 40-bit data, that is, the first data of the first continuous transmission is added to "0" by the adder circuit 2. This addition result is sent to the shift register 1 in synchronization with the clock signal, and as a result, 1
The data of the second time is stored as it is in the shift register 1. From the second consecutive transmission data, that is, from the 41st bit, since the length of the shift register 1 is 40 stages, it is added to the addition result of the first consecutive transmission. Thereafter, similarly, data of every 40 bits is added until the end of the fifth continuous transmission data, and the result is stored in the shift register 1. When the addition result stored in the shift register 1 becomes 3, the addition operation is prohibited, so that the addition result becomes 3 regardless of the value of the data a. Therefore, after inputting all 5 consecutive transmission data, check the contents of the shift register 1, and if the value is 3, "1" has appeared three or more times, so the received data is "1", otherwise If so, it can be judged as "0", and the majority logic will be obtained. In the present embodiment, the output signal h of the AND gate 3 is the majority output, and by inputting the clock signal to the shift register 1 after receiving all the continuous transmission data, the majority logic can be obtained from the signal h.

As described above, according to the present embodiment, since the addition result may be stored in binary numbers from 0 to 3, two bits worth (two sets) are stored.
It is possible to obtain the majority decision logic of 5 consecutively transmitted data by using the 40-stage shift register, and it is possible to reduce one shift register set (40 stages) as compared with the conventional case.

In the above embodiment, the reset function of the shift register was used for the initialization of the shift register, but the initialization can be performed by fixing the input of the adder circuit during the initialization of the shift register.

<Second Embodiment> A second embodiment of the present invention employing such an initialization method will be described below with reference to FIG. In FIG. 3,
The same circuits as those in FIG. 1B are designated by the same reference numerals. The difference between the embodiment of FIG. 3 and the embodiment of FIG. 1B is that the shift register 1
It is in the initialization method of. In FIG. 3, circuits 6, 7, and 8 are shown.
Reference numerals 9 and 9 are circuits corresponding to initialization means for initializing the shift register 1. Circuit 6 is a NAND gate, circuit 7,
Reference numeral 8 is an AND gate, and circuit 9 is an initialization signal generation circuit that outputs a signal j that becomes "0" only during the first data transmission period based on the data transmission start signal i and the clock signal b.

Hereinafter, an operation example of the second embodiment shown in FIG. 3 will be described with reference to FIGS. 4 and 5. FIG. 4 shows a general data format of transmitted continuous transmission data. The continuous transmission data is the bit synchronization data (hereinafter abbreviated as BS signal) for establishing the leading bit synchronization, the word synchronization data (hereinafter abbreviated as WS signal) for establishing the data word synchronization, and then the same content. Transmission data is sent 5 times. The operation will be described below on the assumption that data is continuously transmitted with this data format as one unit. FIG. 5 is a diagram showing an example of operation timing of the second embodiment shown in FIG. The subscripts n and n + 1 in the figure indicate the data transmission order. For example, D4n indicates the nth transmission data and the fourth consecutive transmission data.

In FIG. 5, when the BS signal and the WS signal are received, the data demodulation circuit outputs the word synchronization signal i. This signal i
Is received as a data transmission start timing signal, the initialization signal circuit 9 sets the initialization signal j to "0" only during the first data transmission period. As a result, the outputs of the AND gates 7 and 8 also become "0". In this state, the data signal a is AND
Since it is added with 0 through the gate 4 in the adder circuit, the output of the adder circuit 2 becomes the value of the data a. In the first embodiment, the initialization is performed by setting the contents of the shift register 1 to 0, but in the present embodiment, the initialization is performed by fixing the input of the adder circuit 2 to 0 as described above.
When the first continuous transmission data is completed, the initialization signal j becomes "1". As a result, after the second consecutive transmission data, the same operation as in the first embodiment shown in FIG. 1B is performed, and after the termination of the consecutive transmission data, the majority logic is obtained from the output signal h.

As described above, also in the present embodiment, as in the case of the first embodiment, since it is sufficient to store the addition result from 0 to 3 in binary number, it is necessary to use a 40-stage shift register of 2 bits (2 sets) to obtain 5 bits. It is possible to obtain the majority logic of the continuous transmission data, and it is possible to reduce one shift register set (40 stages) from the conventional one.

<Third Embodiment> In the embodiments described so far, the majority logic output is obtained from the AND gate 3, but the majority logic output can be obtained by decoding the output of the adder circuit 2.

FIG. 6 shows a third embodiment of the present invention. 6, the same circuits as those in FIG. 4 are designated by the same reference numerals. circuit
An AND gate 10 decodes whether the output value of the adder circuit 2 is 3 and outputs a majority logic.

The operation of the third embodiment will be described below with reference to FIGS. 6 and 7. FIG. 7 is a timing chart showing an example of the operation. When the BS signal and the WS signal indicating the start of the continuous transmission data are received, the synchronization signal i is transmitted from the data demodulation circuit. In response to this, the initialization signal generation circuit 9 outputs the initialization signal j during the period of the first continuous transmission data. This makes AND
The outputs of the gates 7, 8 and 9 become "0", and the shift register 1 is initialized. This is the same operation as the second embodiment shown in FIG. Since the initialization signal j becomes "1" after the second continuous transmission data, addition of the data values is performed as in the first and second embodiments. The present embodiment is different from the previous embodiments when the fifth consecutive transmission data is input. At the time when the fourth continuous transmission data is completed, the addition result up to that point is stored in the shift register 1. When the fifth consecutive transmission data is input, the addition result of the fifth consecutive transmission data is obtained at the output of the adding circuit 2. By decoding this output value with the AND gate 13, the majority logic output can be obtained as the output signal q at the same time as the fifth consecutive transmission data is input.

As described above, according to this embodiment, there is an effect that the majority logic output can be obtained at the same time when the final continuous transmission data is received. Needless to say, there is an effect that the number of shift registers can be reduced as in the above-described embodiments.

<Fourth Embodiment> In the third embodiment, the AND gates 7 and 8 are inserted immediately before the adder circuit 2 to initialize the shift register 1. This initialization is performed with a value 0 and a signal a. The AND gates 7 and 8 may be inserted immediately after the output of the shift register 1 as long as the addition operation can be obtained. FIG. 8 shows a fourth embodiment of the present invention which employs such an initialization structure. In this embodiment, while the signal j is "0", the input signals f1 and f2 of the adding circuit 2 are
Becomes 0, and the shift register 1 is initialized as in the embodiment shown in FIG. At this time, NAND gate
Since the input of 3a also becomes "0", the data a is not prohibited by the AND gate 4. Therefore, the present embodiment has an effect that the AND gate 6 can be reduced as compared with the embodiment shown in FIG.

<Fifth Embodiment> In the embodiments described above, the reset function of the shift register 1 is used as the shift register initialization method, or
The input value of the adder circuit 2, that is, the output value of the shift register 1
This is equivalently done by setting it to 0 by the AND gate. These initializations were performed by setting the contents of the shift register 1 to 0, but the majority logic can be obtained by determining whether the number of "1" s or "0" s exceeds the majority of the number of continuous transmissions. Therefore, even if the contents of the shift register are set to other than 0, the present invention can be applied.

The fifth embodiment of the present invention employing such an initialization method will be described below with reference to FIG. The embodiment shown in FIG. 9 is a majority logic circuit which can obtain the majority logic of 29 consecutive transmission data from 3 consecutive transmissions. In FIG. 9, the circuit 1a is a 4-bit shift register. This number of stages corresponds to the length of the continuous transmission data, and here it is set to 40 as in the previous embodiments. Circuit 2a is 1 for 4-bit data
It is an adder circuit for adding bits and corresponds to an adding means. The circuit 3b is an AND gate corresponding to a detecting means for detecting that the output value of the shift register 1a is 15. The circuit 4 is an AND gate corresponding to prohibiting means, and the circuit 10a is an AND gate that determines whether the output value of the adder circuit 2a is 15 and outputs a majority logic. The circuit 11 is a latch circuit for storing 4-bit data, and the circuit 12 is a switching circuit for switching the input of the adder circuit 2a according to the initialization signal j. When the initialization signal j is "0", the output of the latch 12 is the addition circuit. It is configured to be input to 2a. The circuit 9 is an initialization signal generating circuit, which is the same circuit as that shown in FIG.

The operation of the fifth embodiment will be described below. The addition of the data value of the continuous transmission data a by the addition circuit 2a is the same as in the previous embodiments. In this embodiment, the initial value s of the shift register 1a is set in the latch 14 in advance. When the continuous transmission data is started, the word synchronization signal i is input. Accordingly, the initialization signal generation circuit 9 sets the initialization signal j to "0" during the first continuous transmission data period. This allows the switching circuit
12 is switched and the output of the latch 11 is input to the adding circuit 2a. Further, the initialization signal j is also input to the NAND gate 3b, and the signal h is fixed at "1". As a result, while the initialization signal j is "0", the output of the adder circuit 2a becomes a value obtained by adding the set value s of the latch 11 and the value of the data a. Since the initialization signal j becomes "1" after the second continuous transmission data, the result of adding the output value of the shift register 1a and the value of the data a becomes the output of the adding circuit 2a. The output value of the shift register 1a is
When it reaches 15, the NAND gate 3b detects this and outputs the signal g as "0".
To As a result, the output signal c of the AND gate 4 is "0".
The addition operation is prohibited and the output value of the addition circuit 2a becomes 15. As described above, in the present embodiment, the counting operation is stopped at 15 when the number of "1" s in the continuous transmission data starts counting from the value s set in the latch 11 as an initial value. For example, the latch
When 0 is set in 11, the counting operation is performed from 0 to 15, so that the number of "1" s of the data a can be counted up to 15. Therefore, it is possible to obtain the majority decision logic of the 29 consecutive transmission data in which 15 is the majority.

Table 2 shows the relationship between the value set in the latch 11 and the number of continuous transmissions for which the majority logic is obtained. It is shown that by changing the set value from 0 to 13, it is possible to obtain the majority logic of the data from 3 consecutive transmissions to 29 consecutive transmissions. For example, since the number of "1" s of the data a having the set value of the latch 11 as 12 is counted up to 13, 14, 15 and 3, the majority logic of 5 consecutively transmitted data can be obtained as in the previous embodiments. You can

As described above, according to the present embodiment, 40 bits having a 4-bit structure are used.
The majority shift logic of 29 consecutive transmission data can be obtained by using the stage shift register, and the circuit scale of the shift register can be significantly reduced. Further, the present embodiment has an effect that the majority logic of 29 consecutive transmission data from 3 consecutive transmission can be obtained only by changing the value set in the latch circuit 11.

In the fifth embodiment shown in FIG. 9, the initial value of the shift register 2a is changed to set the number of continuous transmissions for which the majority logic is obtained.
Since it is only necessary to change the number to be counted, it can be easily inferred that the present invention can be applied even if the detection value of the detection means can be set.

<Sixth Embodiment> In the embodiments described so far, the adding circuit is used as the adding means, but the present invention can be applied by using a counter.

FIG. 10 shows the configuration of the sixth embodiment of the present invention using a counter as the addition means. This embodiment is configured by replacing the adder circuit 2 in the first embodiment shown in FIG. 1B with a counter, and the same components as those in FIG. 1B are designated by the same reference numerals. In FIG. 10, the circuit 1 is a 2-bit 40-stage shift register. The circuit 2b is a preset type counter having a function of internally setting the output signals g1 and g2 of the shift register 1 when the preset terminal (signal n) becomes Low level. The circuit 2b is internally set at the rising timing of the signal c. The set value is counted up.
The circuit 20 is a timing generation circuit that receives a data clock b and a timing clock k having a frequency four times as high as that of the data clock b, and outputs a signal m serving as a count clock of the counter 2b and a preset signal n.

Prior to the description of the operation of the sixth embodiment shown in FIG. 10, first, a configuration example and operation of the timing generation circuit 20 will be explained.
This will be described with reference to FIG. 13 and FIG.

FIG. 12 is a configuration diagram showing a configuration example of the timing generation circuit 20. The circuits 22 and 23 are D-type flip-flops (hereinafter referred to as D-FF).
Circuit 24 is a NOR gate, circuit 25 is an AND gate, and circuit 21 is an inverter. The operation of the circuit shown in FIG. 12 will be described below with reference to the timing chart of FIG. As described above, the timing clock k is the data clock b
Is a clock signal having a quadruple frequency synchronized with. Here, it is assumed that the data clock b changes at the rise of the timing clock k. First, a signal k1 obtained by delaying the data clock b until the falling timing of the timing clock k is obtained by the D-FF22. Next, the signal k1 is sent by D-FF23.
Is further delayed by one clock of the timing clock k to obtain its negated signal k2. From the NOR gate 24, the logical sum signal m of the signals k1 and k2 obtained from D-FF22 and D-FF23 is obtained.
The AND signal n is obtained from the NAND gate 25 and output. By these operations, the signal m and the signal n are output from the timing generation circuit 20 at the timing shown in FIG.

In the embodiment shown in FIG. 10, the signal m is used as the count clock signal of the counter 2b and the signal n is used as the preset signal of the counter 2b. According to the timing shown in FIG. 11, the data a changes at t1 and at t2. The counter 2b counts up, the shift register 1 performs the shift operation at t3, and the preset operation of the counter 2b is performed at t4.

Next, the operation of the entire sixth embodiment shown in FIG. 10 will be described with reference to FIG. In this embodiment, the shift register 1
The operation of the AND gate 3 is the same as the operation of the first embodiment shown in FIG. 1B, the shift register 1 stores the count output of the counter 2b, and the AND gate 3 outputs the output value of the shift register 1 of 3. Detect that there is. At the start of the continuous transmission data, the contents of the shift register 1 are initialized to 0 by the reset signal r. When the output of the AND gate 3 is "0" and the value of the data input a is "1", the signal m passes through the AND gate 4 and is supplied to the counter 2b as the count clock signal to perform the counting operation. AND if the value of data input a is "0"
The signal m is blocked by the gate 4a and the counting operation is not performed. That is, like the adder circuit 2 of the first embodiment, the counter 2b counts the number of "1" of the data input a. When the counting operation progresses and the count value reaches 3, the AND gate 3 detects this and sets the output to "1". This allows
The AND gate 4a is closed and the count clock signal c of the counter 2b is prohibited. That is, the AND gate 4a prohibits the counting operation of the counter 2b. As a result, also in the present embodiment, as in the first embodiment, when the number of data "1" is 3 or more, the count value stored in the shift register 1 is held as 3. By detecting this value with the AND gate 3, the majority logic can be obtained.

As described above, also in the present embodiment using the counter circuit as the adding means, the majority logic of 5 consecutively transmitted data can be obtained by the shift register of 2 rows and 40 stages, and the effect that the number of shift registers can be reduced is obtained. To be Further, in the present embodiment, an example in which the counting means of the first embodiment is replaced with a counter is shown, but the counter circuit can be applied to the adding means also in the second, third, fourth and fifth embodiments. Can be easily analogized.

In the above examples, the number of "1" s in the data was counted,
Logically "1" or "0" can be changed with one inverter circuit. Therefore, it is obvious that the present invention can be applied to the case of counting (adding) the number of "0" s. Further, it is obvious that the present invention can be applied to data other than 40 bits by changing the number of stages of the shift register. Further, the number of "1" or "0" may be changed to be subtracted from the initial value.

[Effects of the Invention] As described above, according to the present invention, the majority decision logic up to (2 ^{k + 1} -3) continuous transmission data can be obtained by using k sets of shift registers. This has the effect of being able to significantly reduce the circuit scale.

[Brief description of drawings]

FIG. 1A is a block diagram showing the configuration of the present invention, FIG. 1B is a configuration diagram of the first embodiment of the present invention, FIG. 2 is a timing diagram showing an operation example of the first embodiment, and FIG. 3 is the present invention. 2 is a configuration diagram of a second embodiment, FIG. 4 is a data configuration diagram showing an example of transmitted continuous transmission data, FIG. 5 is a timing diagram showing an operation example of the second embodiment, and FIG. 6 is the present invention. 7 is a block diagram of the third embodiment of FIG.
FIG. 8 is a timing diagram showing an operation example of the third embodiment, FIG. 8 is a configuration diagram of the fourth embodiment of the present invention, FIG. 9 is a configuration diagram of the fifth embodiment of the present invention, and FIG. 6 is a block diagram of a sixth embodiment of FIG.
FIG. 11 is a timing chart showing an operation example of the sixth embodiment,
11 is a circuit diagram showing a configuration example of the timing generation circuit 20 shown in FIG. 11, and FIG. 13 is a timing diagram showing an operation example of the circuit shown in FIG. 1,1a …… Shift register, 2,2a …… Adding circuit, 2b …… Counter, 3,4,4a, 7,8 …… AND gate, 3a, 3b …… NAND gate, 9 …… Initialization signal generation circuit.

Claims (8)

[Claims] 1. m that is sent continuously (2n-1) times (n ≧ 2)
In a majority logic circuit of bit serial data, a shift register having a k-bit configuration and m stages, and 1-bit data corresponding to the serial data are sequentially added to the k-bit output data of the shift register, and obtained by addition. Addition means for inputting a k-bit addition result to the shift register, detection means for detecting whether or not the k-bit output data of the shift register matches a predetermined value s, and the coincidence detection means Prohibiting means for prohibiting the adding operation of the adding means in accordance with the detection signal; initialization means for initializing all m pieces of k-bit data of the shift register to (s−n); and (2n−1) th time After the end of the continuous transmission, it is detected whether or not each of the m pieces of k-bit output data output from the shift register coincides with the above s, and the respective detection results are detected. And means for outputting the determined logical result, said k satisfies 2 ^k -1 ≧ n, the S is s = 2 ^k -1
And the addition means inputs the k-bit output data of the shift register to the shift register as the addition result when the addition operation is prohibited, and adds the second (2n−
1) The m number of k-bit output data output from the shift register after the completion of the first consecutive transmission is the sum of the adding means performed for each of the (2n−1) th consecutive m-bit serial data. A majority logic circuit which is the result of addition of m pieces by an addition operation. 2. The majority logic circuit according to claim 1, wherein the 1-bit data corresponding to the serial data is each bit of the serial data. 3. The majority logic circuit according to claim 1, wherein the 1-bit data corresponding to the serial data is each inverted bit of the serial data. 4. The addition means includes k of the shift register.
By presetting bit output data, performing an increment operation according to the value of 1-bit data corresponding to the serial data, and inputting the output to the shift register, the serial data is converted into the k-bit output data of the preset shift register. Has a counter for inputting the k-bit addition result obtained by adding 1-bit data corresponding to the above into the shift register, and the prohibiting means prohibits the increment operation of the counter according to the match detection signal. The majority logic circuit according to claim 1, wherein the adding operation of the adding means is prohibited. 5. An m sent continuously (2n-1) times (n ≧ 2)
In a majority logic circuit of bit serial data, a shift register having a k-bit configuration and m stages, and 1-bit data corresponding to the serial data are sequentially added to the k-bit output data of the shift register, and obtained by addition. Addition means for inputting a k-bit addition result to the shift register, detection means for detecting whether or not the k-bit output data of the shift register matches a predetermined value s, and the coincidence detection means Prohibiting means for prohibiting the adding operation of the adding means in accordance with the detection signal; initialization means for initializing all m pieces of k-bit data in the shift register to (s−n); and (2n−1) th time The addition of 1-bit data corresponding to serially transmitted m-bit serial data and k-bit output data output from the shift register Each of the m addition result by stage, detects whether matches in the s, the respective detection results and means for outputting as a majority logic result, the k satisfies 2 ^k -1 ≧ n, The S is s = 2 ^k −1
And the addition means inputs the k-bit output data of the shift register to the shift register as it is when the addition operation is prohibited. 6. The majority logic circuit according to claim 5, wherein the 1-bit data corresponding to the serial data is each bit of the serial data. 7. The majority logic circuit according to claim 5, wherein the 1-bit data corresponding to the serial data is each inverted bit of the serial data. 8. The addition means includes k of the shift register.
By presetting bit output data, performing an increment operation according to the value of 1-bit data corresponding to the serial data, and inputting the output to the shift register, the serial data is converted into the k-bit output data of the preset shift register. Has a counter for inputting the k-bit addition result obtained by adding 1-bit data corresponding to the above into the shift register, and the prohibiting means prohibits the increment operation of the counter according to the match detection signal. The majority logic circuit according to claim 5, wherein the adding operation of the adding means is prohibited.