JPH0797745B2 - Phase synchronization circuit - Google Patents

Description

The present invention relates to a phase locked loop circuit used in a wireless device.

[Conventional technology]

A conventional phase locked loop circuit, a so-called PLL circuit, has a basic configuration as shown in FIG. 4, a reference signal generator 1, a phase comparator (PD) 2, a low pass filter (LPF) 3, and a voltage. Controlled oscillator (hereinafter abbreviated as VCO) 4 and variable frequency divider 6
It consists of and. Then, uses a divided signal by the variable frequency divider 6 the fundamental wave f _o of VCO4 as a comparison signal of the phase comparator 2, the reference frequency of the reference signal generator 1 PLL system in a stable and Natsuta state is equal to f _r . Thus, if the frequency division number of the variable frequency divider 6 is M, and the fundamental wave f _o and the reference signal generator 1 of the reference frequency f _r of the _{VCO4, f o = M · f} r (1) becomes , frequency interval Delta] f of the output is equal to Δf = (M + 1) f r -Mf r = f r (2) and the reference frequency f _r. Therefore, in order to reduce the frequency interval of the output signal, it is necessary to lower the reference frequency f _r .

By the way, when using a PLL circuit for transmission in a radio,
4 or a method of modulating the voice (300 to 3 KHz) to the reference signal is generally adopted. When modulating with VCO4, the low-pass filter 3 does not attenuate the voice component, so the PLL
The natural frequency f _{n of the} circuit must be less than 300 Hz, but P
The LL pull-in time is inversely proportional to f _n , causing a pull-in delay. On the other hand, when modulation is performed with the reference signal, the low-pass filter 3 needs to pass a voice component, and the natural frequency f _n needs to be 3 KHz or higher, so that there is no problem of delay in pulling in. . However, the reference signal f
There is a problem that the SN ratio is deteriorated due to leakage of _r, the f _n f
_It must be _r or less, and it is impossible to realize a frequency interval of 3 KHz or less by the method of modulating the reference signal.

[Problems to be solved by the invention]

As described above, in the above-mentioned conventional phase locked loop circuit, it is necessary to lower the reference frequency of the phase comparator in order to reduce the frequency interval of its output, and the delay of the PLL pull-in and the output frequency depending on the modulation method. There was a problem of the interval limit.

The present invention has been made in order to solve the conventional problems, and an object thereof is to provide a phase locked loop capable of operating at a reference frequency which is an integral multiple of the output frequency interval.

[Means for solving problems]

In order to achieve the above-mentioned object, the present invention provides a reference signal generator, a phase comparator, a low-pass filter, a VCO, and a variable frequency divider in the phase-locked loop circuit, wherein the VC
Between the O and the variable frequency divider, a harmonic selection amplification circuit that attenuates the fundamental wave of the output of the VCO and amplifies an arbitrary harmonic is provided.

[Action]

Therefore, in the present invention, if the order of the harmonic selected by the harmonic selective amplification circuit is N, the comparison signal frequency of the phase comparator is And equal to the reference frequency f _r , these are Becomes Therefore, the output frequency interval Δf is Therefore, the frequency interval can be reduced with the same reference frequency f _r as compared with the conventional method (when N = 1).

〔Example〕

Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings.

FIG. 1 is a block diagram showing an embodiment of the phase locked loop circuit according to the present invention, in which the same parts as those in FIG. 4 are designated by the same reference numerals. Here, the reference signal generated from the reference signal generator 1 and the output of the variable frequency divider 6 are input as comparison signals to the phase comparator 2, and the phase comparator 2 compares the two signals in phase. Then, a voltage proportional to the phase difference is output to the low pass filter 3. The low-pass filter 3 removes the high frequency contained in the output voltage from the phase comparator 2 and applies the voltage to VCO4 as a control voltage. As a result, the VCO 4 oscillates an output having a frequency corresponding to the control voltage, the output is taken out as an output signal of this circuit, and at the same time, through the harmonic selective amplification circuit 5,
Only a certain harmonic component of the output of VCO4 is input to the variable frequency divider 6.

Next, the operation of the configuration of the above embodiment will be described. The output of the VCO 4, as shown in FIG. 2, the fundamental wave f in addition to the basic wave of an integral multiple of the harmonic 2f _o of _o, includes a · · · · Nf _o etc., the signal is harmonic When input to the selective amplification circuit 5,
The amplifier circuit 5, as shown in FIG. 3, only the selected amplified high-level signal Nf _o of any harmonic is inputted to the variable divider 6. At this time, normally, the variable frequency divider 6
Of the many frequency components included in the input signal, the maximum level frequency is used as the operating frequency. Therefore, the first
In the figure, if the order of the harmonics selectively amplified by the harmonic selective amplification circuit 5 is N, the operating input frequency of the variable frequency divider 6 is N × f _o . Further, if the frequency division number of the variable frequency divider 6 is M, the comparison signal frequency of the phase comparator 2 becomes N · f _o / M, which is equal to the reference frequency f _r when the PLL system is stable. , Is established. Thus, the frequency interval Δf of the case of the fundamental wave f _o as the output of the VCO4 is Becomes As a result, according to the present invention, it is possible to realize a request for the same frequency interval Δf at a frequency that is an integral multiple of the reference frequency f _r . Therefore, in response to the requirement for a frequency interval of 3 KHz or less, what could only be realized by the method of modulating VCO4 can be realized by the method of modulating the reference signal, and the frequency with a short PLL pull-in time can be realized. A synthesizer can be realized.

〔The invention's effect〕

As described above, the phase-locked loop circuit of the present invention includes a harmonic selection amplifier circuit in which the output of the VCO divided by the variable frequency divider is not the fundamental wave but a harmonic, and is provided between the VCO and the variable frequency divider. Since the reference frequency can be increased by providing the same frequency interval, the pull-in time can be shortened. As a result, there is an advantage that a phase locked loop having a small output frequency interval can be realized by the reference signal modulation method for modulating the reference signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a general spectrum of an output signal of the VCO of FIG. 1, and FIG. 3 is an input of the variable frequency divider in FIG. FIG. 4 is a block diagram showing a signal spectrum, and FIG. 4 is a block diagram showing a conventional example. 1 ... Reference signal generator, 2 ... Phase comparator (PD), 3 ...
… Low pass filter (LPF), 4 …… Voltage controlled oscillator (V
CO), 5 ... Harmonic selection amplifier circuit, 6 ... Variable frequency divider.

Claims (1)

[Claims] 1. An output frequency of a voltage controlled oscillator is frequency-divided by a variable frequency divider, and the phase of the frequency-divided output and the reference signal generator output is compared by a phase comparator, and the comparison result is passed through a low-pass filter. In the phase locked loop circuit for supplying the voltage controlled oscillator to the voltage controlled oscillator, between the voltage controlled oscillator and the variable frequency divider, a harmonic selective amplification that attenuates the fundamental wave of the output of the voltage controlled oscillator and amplifies any harmonic A phase synchronization circuit, wherein a circuit is provided, and the reference frequency generated by the reference signal generator is a value obtained by multiplying the order of the harmonics amplified by the harmonic selection amplification circuit by a frequency interval.