JPH0797771B2 - Clock control system - Google Patents

Description

The present invention relates to an information processing apparatus, a clock control system used for digital communication processing, and the like.

[Conventional technology]

Computer systems include a single processor system having one information processing device and a multiprocessor system having a plurality of information processing devices. The clock that determines the basic unit time of operation of these systems is the only clock for a multiprocessor system.

The clock is supplied to the system as described above by providing only a clock supplying device for the system or a clock from one device of a clock supplying device group provided one by one corresponding to each of the plurality of information processing devices. It is realized by providing a device for selecting.

Further, a certain clock supply device includes a plurality of oscillators that generate clocks of different frequencies and a selector that selects one of the clocks of different frequencies that are generated by the plurality of oscillators. Also, other kelock supply devices can generate clocks at different periods. For details of this device, refer to US Pat. No. 4,564,943.
These devices are used for early detection of a failure of the information processing device.

〔Problems to be solved〕

A failure of the clock supply device in a system having only one clock supply device causes a system outage and becomes more serious as the system size increases.

Further, a failure of a certain clock supply device in a system including a plurality of clock supply devices causes a system stop.
However, after that, the rate of system stoppage can be reduced by manually switching to another clock supply device. However, switching to the failed clock supply device is performed toward a specific clock supply device, and thus the operability becomes poor.

Moreover, when both the switching of the device and the switching among the plurality of oscillators included in the device are required, there is a drawback that the operation for that is complicated.

It is an object of the present invention to provide a clock control system which eliminates the above mentioned drawbacks.

[Means for Solving the Problems]

A clock control system of the present invention is a clock control system including a plurality of information processing devices and a clock supply device corresponding to each of the plurality of information processing devices, and each of the clock supply devices has a different frequency. A plurality of clock generating means and a clock selecting means for selecting one of the clocks from the plurality of clock generating means are provided, and each of the plurality of information processing devices clocks its own processing device among the clock supply devices. Device designating means for designating a device for supplying the clock, clock switching instructing means for instructing switching from the clock currently in use in the clock supplying device to another clock, and the clock switching instructing means in the information processing device. In response to an instruction from the clock switching instruction means in the other information processing device. With respect to the clock supply device corresponding to the information processing apparatus and a selection control means for selectively controlling one of the clocks from the plurality of clock generating means.

〔Example〕

Referring to FIG. 1, according to one embodiment of the present invention, a plurality of information processing devices 1 and 2 for performing a processing operation by a clock supplied from the outside, and a clock supply mode to these information processing devices 1 and 2 are changed. A plurality of clock supply devices 10 and 20 are provided. Each of the plurality of information processing devices 1 and 2 is a clock control unit that controls change of clock supply of the corresponding clock supply devices 10 and 20.
Have 11 and 12. These clock control units 11 and 21
Is a clock supply device 10 or 20, which is a clock supply source for the own device, and a designation signal is a clock supply device designation line 301.
And a clock supply device designation unit 102 for sending to 302
202, clock switching instruction signal to clock switching lines 303 and 3
The clock switching units 103 and 203, the clock supply unit switching units 102 and 202, and the clock supply unit switching instruction signals to the lines 305 and 307 based on the signals given from the clock switching units 103 and 203 via lines 301 to 304. Clock supply control units 101 and 201 for outputting and outputting a clock switching instruction signal to lines 306 and 308 are included.

Since the clock supply control units 101 and 201 have the same configuration, the clock supply control unit 101 will be described in detail below.

Referring to FIG. 2, the clock supply control unit 101 determines its own device based on the signal supplied from the clock supply device designating unit 102 via the line 301 and the signal supplied from the clock switching unit 103 via the line 303. A gate 1011 for controlling the switching of the system clock, and a clock of the other system based on the negative signal of the signal supplied from the clock supply device designation unit 202 via the line 302 and the signal supplied from the clock switching unit 203 via the line 304. Is provided with a gate 1012 for controlling the switching of the clocks and a gate 1013 for outputting the signals from the gates 1011 and 1012 to a line 306 as a clock switching instruction signal for the clock supplying device 10, and the signal supplied via the line 301 is supplied to the clock supplying device. It is output to the line 305 as a switching instruction signal.

The clock supply device 10 that inputs a signal from the clock supply control unit 101 via the lines 305 and 306 has the same configuration as the clock supply device 20. Therefore, the clock supply device 10 will be described in detail below.

Referring to FIG. 3, the clock supply device 10 includes a first oscillator 104 that generates a clock signal at a certain period, a second oscillator 105 that generates a clock signal at a period different from that of the first oscillator 104, and a clock supply. A selector 106 for selecting one of a clock signal from the first oscillator 104 and a clock signal from the second oscillator 105 in response to a clock switching instruction signal provided from the control unit 101 via a line 306, and Clock supply control unit 101
Selector 1 applied via line 309 in response to a clock supply device switching instruction signal applied via line 305 from
The selector 107 includes a selector 107 for selecting the output 06 and the clock signal provided from the other clock supply device 20 via the line 310 and outputting the clock signal to the line 311.

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIGS. 1 to 5.

First, the clock supply device designation operation will be described in detail.

Referring to FIG. 1 and FIG. 4, in the processing step 401, the clock supply device designation unit 102 of the information processing device 1
Specifies to use the clock of the clock supply device 10, and outputs a signal to that effect to the line 301. Processing step 402
Then, the clock supply device designation unit 202 of the information processing device 2 designates to use the clock of the clock supply device 10,
A signal to that effect is output to line 302.

Referring to FIG. 1, FIG. 2 and FIG. 4, in the processing step 403, the clock supply control unit 101 supplies the clock from the clock supply device 10 in response to the signal given via the line 301. To send an instruction signal to the line 305.

Referring to FIG. 1, FIG. 3 and FIG. 4, in the processing step 405, the selector 107 of the clock supply device 10 is processed.
Selects the output of the selector 6 in response to the signal from the line 305 and supplies it as a clock signal to the processing device 1 via the line 311.

Referring to FIG. 1, FIG. 2 and FIG. 4, in the processing step 404, the clock supply control unit 201 supplies the clock from the clock supply device 10 in response to the signal applied via the line 302. To send an instruction signal to the line 307.

Referring to FIG. 1, FIG. 3 and FIG. 4, in the processing step 406, the selector 107 of the clock supply device 20.
Responds to the signal from line 307 and supplies it to the processor 2 via line 312 and a clock selection provided by the clock supply unit 10 via line 309.

Next, the clock switching operation of the clock supply device 10 in response to an instruction from the clock switching unit 103 of the information processing device 1 will be described in detail.

Referring to FIGS. 1 and 4, in processing step 407, clock switching unit 103 of information processing device 1 issues a clock switching instruction signal and sends it to line 303.

Referring to FIG. 1, FIG. 2 and FIG. 4, in the processing step 408, the gate 1011 of the clock supply controller 101 is
In response to the signals on the lines 301 and 303, a clock switching valid signal of its own device is generated, transmitted through the gate 1013 and the line 306, and supplied as a clock switching instruction signal to the clock supply device.
Supply to 10.

Referring to FIGS. 1, 3 and 4, in process step 410 the selector 106 of the clock supply device 10 operates on the line 30.
In response to the switching instruction signal from 6, the selection is switched from the output of the first oscillator 104 to the output of the second oscillator 105, or from the output of the second oscillator 105 to the output of the first oscillator 104. The output of the selector 106 is transmitted to the second clock supply device 20 via the line 309 and is also supplied to the processing device 1 via the selector 107 and the line 311.

Referring to FIG. 1, FIG. 2 and FIG. 4, in processing step 409, the gate 1012 of the clock supply control unit 201 of the processing device 2 sends the clock switching instruction signal given via the line 303 via the line 301. It is invalidated by the negative logic of the given device designation signal. Therefore, the clock supply controller 20
1 does not give a clock switching instruction to the clock supply device 20.

In this state, since the clock is supplied from the clock supply device 10 to the processing devices 1 and 2, the clock cycle of the devices 1 and 2 is changed by the clock switching operation.

Further, the clock switching operation of the clock supply device 10 according to an instruction from the clock switching unit 203 of the information processing device 2 will be described in detail.

Referring to FIGS. 1 and 4, in processing step 411, the clock switching unit 203 of the information processing device 2 issues a clock switching instruction signal and sends it to the line 304.

Referring to FIG. 1, FIG. 2 and FIG. 4, in processing step 412, the gate 1012 of the clock control unit 101 of the processing apparatus 1 sends the clock switching instruction signal given via the line 304 via the line 302. It is enabled by the negative logic of the specified device designation signal. The validated signal is provided as a clock switching instruction signal to the clock supply device 10 via the gate 1013 and the line 306. Next, in processing step 414, the clock supply device 10 performs the same clock switching operation as in processing step 410.

In processing step 413, the gate 1011 of the clock control unit 201 of the processing device 2 invalidates the clock switching instruction signal given via the line 304 with the device designation signal given via the line 302. Therefore, the clock control unit 201 does not give the clock switching instruction signal to the clock supply device 20.

In this state, since the clock is supplied from the clock supply device 10 to the processing devices 1 and 2, both clock cycles of the devices 1 and 2 are changed by the clock switching operation.

According to the present invention described with reference to FIG. 4, when the clock is supplied from one clock supply device 10, any clock switching instruction from any of the information processing devices 1 and 2
Only the clock of the clock supply device 10 being supplied can be switched.

Next, it will be described in detail below that even when the information processing apparatus is supplied with the clock from the clock supplying apparatus on the opposite side, only the clock supplying apparatus on the opposite side which is being supplied can perform the clock switching.

First, a state in which the information processing device 1 receives a clock from the clock supply device 20 and the information processing device 2 receives a clock from the clock supply device 10 will be described.

Referring to FIG. 1 and FIG. 5, in the processing step 415, the clock supply device switching unit 102 of the information processing device 1 is executed.
Outputs a device designation signal to the line 301 so as to receive the clock of the clock supply device 20. Further, in processing step 416, the clock supply device switching unit 202 of the information processing device 2 outputs a device designation signal to the line 302 so as to receive the clock of the clock supply device 10.

Referring to FIG. 1, FIG. 2 and FIG. 5, in processing step 417, the clock control unit 101 of the information processing device 1 assigns the designation signal of the device 20 given via the line 301 to the device 20 on the line 305. It is supplied to the clock supply device 10 as an instruction signal. In the processing step 418, the information processing device 2
The clock controller 201 of the device 10 is provided via line 302
Is supplied to the clock supply device 20 on the line 307 as a designation instruction signal for the device 10.

Referring to FIG. 1, FIG. 3 and FIG. 5, in process step 419, the selector 107 of the clock supply device 10 is processed.
Selects the clock supplied from the clock supply device 20 via the line 310 and supplies it to the information processing device 1 via the line 311. Further, in processing step 420, the selector 107 of the clock supply device 20 selects the clock supplied from the clock supply device 10 via the line 309 and supplies it to the information processing device 2 via the line 312.

In this way, the information processing device 2 receives the clock from the clock supply device 10. Therefore, when the processing device 2 wants to change the clock cycle, it must issue a clock switching instruction to only the clock supply device 10. This operation will be described below.

Referring to FIGS. 1 and 5, in the processing step 421, the clock switching unit 203 outputs the clock switching instruction signal to the line 3.
Output to 04.

Referring to FIG. 1, FIG. 2 and FIG. 5, in the processing step 423, the gate 1011 of the clock supply controller 201 is
Disables the clock switch indication signal provided on line 304 by the device designation signal provided on line 302. Therefore, the clock supply control unit 201 does not give the clock switching instruction to the clock supply device 20 via the line 308.

In the process step 422, the gate 1012 of the clock supply control unit 101 outputs the clock switching instruction signal given via the line 304 and the other device system clock switching instruction signal by the negative logic of the device designation signal given via the line 302. To generate.
This signal is supplied to the clock supply device 10 via the gate 1013 and the line 306 as a clock switching instruction signal.

Referring to FIGS. 1, 3 and 5, in process step 424, the selector 106 of the clock supply device 10
The output of the first oscillator 104 changes from the output of the first oscillator 104 to the second oscillator 1 in response to the clock switching instruction signal provided via the line 306.
To the output of 05 and from the output of the second oscillator 105 to the first
The selection is switched to the output of the oscillator 104 of. Selector 1
The output of 06 is given to the information processing device 2 via the line 309, the clock supply device 20, and the line 312.

〔The invention's effect〕

In this way, when the information processing device 2 receives the clock from the clock supply device 10 which is not compatible, the clock of the clock supply device 10 being supplied can be switched to a different clock. For this reason, it is possible to operate the information processing system without depending on the clock supply form, and it is possible to improve the efficiency of system operation, and it is also possible to realize remote maintenance and simplification of operation.

That is, by making it possible to control the clock supply,
When the clock supply device is switched due to a failure of the oscillator of the clock supply device or the like, the clock supply state can be continued as it is, so that there is no need to reset the clock supply state. Further, it becomes unnecessary to switch the clock supply in consideration of the relationship between the clock supply device and the information processing device, and only the information processing device needs to be considered, so that the operation efficiency can be improved.

In addition, the clocks supplied by the two clock supply devices are not the same as in the embodiment of the present invention, but individual clocks are supplied, thereby providing a double clock supply form. Therefore, it is also an effective means in a clock margin test as a means for early detection of a failure during system maintenance.

[Brief description of drawings]

1 is a diagram showing an embodiment of the present invention; FIG. 2 is a diagram showing a detailed configuration of the clock supply control units 101 and 201 of FIG. 1; FIG. 3 is a diagram of the clock supply devices 10 and 20 of FIG. FIG. 4 is a diagram showing a detailed configuration; and FIGS. 4 and 5 are diagrams for explaining the operation of one embodiment of the present invention. In the figure, 1,2 ... Information processing device, 10, 20 ... Clock supply device, 11, 21 ... Clock supply control unit, 101, 201 ...
Clock supply control unit, 102,202 ... Clock supply device designation unit, 103, 203 ... Clock switching unit.

Claims (1)

[Claims] 1. A clock control system comprising a plurality of information processing devices and a clock supply device corresponding to each of the plurality of information processing devices, wherein each of the clock supply devices generates a plurality of clocks having different frequencies. Means and a clock selection means for selecting one of the clocks from the plurality of clock generation means, and each of the plurality of information processing devices supplies a clock to its own processing device among the clock supply devices. Device designating means for designating a device, clock switching instructing means for instructing switching from the currently used clock in the clock supply device to another clock, and instruction from the clock switching instructing means in the information processing device Alternatively, in response to an instruction from the clock switching instructing means in another information processing apparatus, the information processing apparatus is addressed. Clock control system characterized in that it comprises a selection control means for selectively controlling one of the clocks from the plurality of clock generation means to said clock supply apparatus.