JPH0797837B2 - Solid-state imaging device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention provides a signal processing circuit that suppresses noise of an output signal obtained by a solid-state image sensor to obtain a high-sensitivity television camera device. The present invention relates to a solid-state imaging device having the same.

[Technical background of the invention and its problems]

The solid-state image sensor such as CCD is smaller than the conventional image pickup tube,
It has the advantages of light weight and high reliability, and also has advantages in terms of characteristics such as no distortion of figures, afterimages, and image sticking. For this reason, it has recently been used for industrial TV cameras, home video cameras and the like. Furthermore, application to electronic cameras is also expected. In the application to these cameras, there is a strong demand for higher sensitivity because it is a device for seeing things. Higher sensitivity of solid-state imaging device is a method to improve photoelectric conversion sensitivity of the device itself and noise generated by the device itself.
There is a way to suppress. The former is determined by the structure of the device, and it is technically difficult to improve it significantly in the future. Therefore, the main factor that determines the sensitivity of the solid-state imaging device at present is noise generated from the device itself, and if this noise is suppressed, higher sensitivity can be achieved. The noise generated by the solid-state image sensor is greatly influenced by the noise generated from the output section of the element.

The cause of noise generation in the solid-state image sensor will be described with reference to FIGS. 6 and 7. FIG. 6 is a schematic diagram showing the output circuit section of the CCD image pickup device. For example, to the transfer electrodes ΦH ₁ and ΦH ₂ , the output gate electrode OG, the reset gate electrode RS, and the reset drain electrode RD formed on the P-type Si substrate 1, a predetermined pulse P ₁ , P ₂ , P _R or a DC voltage V is applied. _OG and V _RD are added to transfer the signal charge from left to right in the figure. A floating n provided between the output gate electrode OG and the reset gate electrode RS
The type diffusion layer 2 and the substrate 1 form a signal charge detecting diode. An on-chip source follower circuit 3 is provided so as to be connected to the diffusion layer 2. Source follower circuit 3
Is composed of a two-stage circuit using MOS FETs. Then, the drain electrode OD, the substrate electrode SS and the respective electrodes of the signal output terminal 4 which are common to the two stages are provided. A DC voltage V _OD is applied to the drain electrode OD. The signal charge is transferred under the transfer electrodes ΦH ₂ and ΦH ₁ , flows under the output gate electrode OG and flows into the diffusion layer 2, and changes its potential. The source follower circuit 3 receives this potential change and outputs a signal from the output terminal 4 to the outside. A reset pulse is applied to the reset gate electrode RS in a constant cycle to reset the potential of the diffusion layer 2 to the reset drain voltage V _RD . This output circuit section is well known to a designer who handles a solid-state image sensor as a floating diffusion type output circuit. FIG. 7 shows operation waveforms of each part of the output circuit of FIG. While the pulse of the transfer electrode ΦH ₁ is on, the pulse of the reset gate electrode RS is turned off-
On-off. The signal obtained from the output terminal 4 at this time is reset to the reset drain voltage V _RD during the period t _{R in which} the pulse of the reset electrode RS is on, and the reset electrode R in the next period.
When the S pulse is off and the transfer electrode ΦH ₁ pulse is on, the input gate capacitance Ci of the source follower circuit and the capacitance of the reset electrode RS
It becomes the potential determined by Cr. No signal is included in this period t _N. Then, next, during a period t _S in which the pulse of the reset electrode RS is off and the pulse of the transfer electrode ΦH ₁ is off, the signal charge is converted into a voltage and output.

By the way, in the output circuit having such a structure, the noise source is 2
There is one. One is thermal noise generated when the pulse of the reset electrode RS is on and remains in the diffusion layer 2 when the pulse of the reset electrode RS is turned off. Usually, this noise Qn can be expressed by the following equation. .

Here, k is the Boltzmann constant, T is the absolute temperature, and C is the capacitance of the diffusion layer. This noise is white noise that is distributed almost constant with respect to frequency, and is called reset noise. The other is 1 / f noise generated in the source follower circuit 3. The source follower circuit is composed of MOS FET. For this reason, 1 / f noise that MOS / FET has is generated. This noise increases as the frequency decreases, and is particularly noticeable on the reproduced image. These two noises are output with different values for each pixel as shown in the output signal waveform of FIG. Normally, the output signal of the CCD is averaged by using the LPF in order to remove the pulse jump of the reset electrode RS and to extend the signal period t _S. As a result, the above-mentioned two noise components remain in the obtained output signal as shown by the hatched portion in the figure. For this reason, the S / N (signal / noise ratio) of the output signal deteriorates, and there is a problem that the sensitivity of the CCD cannot be improved. In particular, 1 / f noise is a low-frequency component, which causes coarse noise on a reproduced image and is a very conspicuous cause.

One way to remove this noise and improve S / N is to correlate the output signal shown in Fig. 7 by clamping the t _N period to a constant DC voltage and then sampling the voltage of the signal period t _S. Sampling methods are well known. Also,
A method of performing the correlated double sampling after sampling the period of t _N once and expanding the period is disclosed in Japanese Patent Laid-Open No. 55-163693.
It is disclosed in the publication.

However, when the frequency of the clock pulse driving the CCD is as high as several MHz or more, the period of t _N becomes short and the time required for clamping cannot be taken,
There was a problem that S / N could not be improved. When the inventor shows concrete numerical values, the horizontal clock frequency is 7.16 MHz in a CCD having horizontal 400 pixels and vertical 500 pixels. In this case, one cycle of the signal, that is, one pixel cycle is 140 ns. To obtain reliable operation in this cycle, the on period t _R of the pulse of the reset gate electrode RS is 35 ns, the noise period t _N is 35 ns, and the signal period is
t _S becomes about 70ns. The noise period t _N is 35 ns, but within this period the period during which it becomes sufficiently stable is further narrowed down to about 15 ns. Therefore, it is necessary to clamp within this 15ns, but it is very difficult to operate the clamp circuit accurately within 15ns. Moreover, in this case, a narrow pulse with a pulse width of 15 ns or less is required, and this pulse mixes into the signal, which causes a problem of deteriorating S / N. Further, the correlated double sampling circuit does not operate correctly when high frequency noise is included in the t _N period in the CCD output signal, and rather has a problem of degrading the S / N from the state before clamping. Further, if the clamp pulse includes a pulse component within the signal band, there is a problem that the reproduced image is remarkably deteriorated by being mixed into the output signal as fixed noise. Further correlation 2
The signal band required to operate the double sampling reliably is more than 5 times the horizontal clock frequency. This value is 35MH
There was a problem that it was more than z, which was difficult in circuit fabrication.

As explained above, the clock frequency of the conventional CCD is several MHz.
When the above operation is performed, noise in the output circuit unit cannot be removed, and S / N is deteriorated, so that there is a problem that a high-sensitivity TV camera cannot be realized.

[Object of the Invention]

The present invention has been made in view of the above points, and effectively eliminates noise generated in the output circuit section of a solid-state image sensor, obtains a signal with extremely good S / N, and is a highly sensitive television camera device. It is an object of the present invention to provide a solid-state imaging device equipped with a signal processing circuit that can realize the above.

[Outline of Invention]

According to the present invention, the output signal of the solid-state image pickup device is divided into two periods within one pixel period, that is, the first signal of only noise having no signal component.
And the second period in which noise and signal components are included. Here, the first period and the second period are set to be substantially equal to each other. Then, one of the output signals divided into the first and second periods is passed through an inverting amplifier and the other is passed through an in-phase amplifier, and then the two output signals are alternately taken out by a gate circuit and reset in one pixel cycle. A circuit for suppressing noise by integrating with an integrating circuit is provided.

〔The invention's effect〕

By including the noise suppressing circuit of the present invention, the problems that have been encountered in the conventional noise improving circuit are significantly improved, and the following effects can be obtained.

Since the noise suppression circuit of the present invention does not require the high-speed clamp circuit used in the conventional circuit, noise can be reliably suppressed even when the CCD read frequency is as high as 10 MHz or higher.

Since the high frequency component, which has been a problem in the conventional circuit, returns to the low frequency side and is generated back, there is essentially no backlash noise, so that the noise suppressing effect of the present invention is large.

In the past, the frequency band of the CCD output signal had to be large for high-speed clamping and sample-holding, but the circuit of the present invention does not need to have a wide frequency band of the CCD output signal because the signal gate circuit is sufficient. The characteristic is that the signal of the pixel cycle can be transmitted. Therefore, noise can be suppressed easily and surely in terms of circuit design as compared with the conventional circuit.

As for S / N, the higher the S (signal component) and the smaller N (noise component), the higher the image quality. Therefore, when S is reduced in the noise suppression circuit itself, the amount of suppression of N cannot be improved as S / N unless a very large value is obtained. According to the present invention, noise is suppressed by integrating the inverting amplifier output and the in-phase amplifier output for each pixel period, and at the same time, the signal component period within one pixel period divided into ½ pixel periods is effectively obtained by this integration. Is expanding. Therefore, there is a feature that N can be significantly suppressed without a decrease in S.

As described above, according to the present invention, the reset noise and the 1 / f noise generated in the output circuit section of the solid-state imaging device can be surely suppressed, so that the device can be driven with a very small output voltage. . As a result, it is possible to realize a high-sensitivity television camera device with extremely good S / N.

Example of Invention

Examples of the present invention will be described below. FIG. 1 is a block diagram of an embodiment of the solid-state imaging device of the present invention, and FIG. 2 is a signal waveform diagram thereof. The CCD image pickup device 10 is driven by a drive circuit 11 with a predetermined pulse. The output signal of the image sensor 10 is input to the noise suppression circuit 12. The noise suppressing circuit 12 includes a inverting amplifier 13 and an in-phase amplifier 14 arranged in parallel, and a gate circuit 15 composed of _first and _second switches S ₁ and S ₂ connected to the outputs of these amplifiers, and switches S ₁ and S ₁ . ₂ , a gate pulse circuit 16 for on / off control, an integration circuit 17 for integrating the output signals obtained from the switches S ₁ and S ₂ and synthesized within one pixel period, and the integration circuit 17 is reset in one pixel cycle. It is composed of a reset pulse circuit 18 for controlling and an LPF 19 for averaging the output signal of the integrating circuit 17.

As shown in FIG. 2, the output signal of the CCD image pickup device 10 includes a first period t _F of only noise having no signal component, a second period t _{S of which} signal component and noise are included, and signal charge of CCD. The drive circuit 11 operates so as to have a reset period t _R for resetting in one pixel cycle. What is important here is that t _F = t _S. If t _F and t _S deviate from each other, it is necessary to adjust the gain of the inverting amplifier 13 or the common-mode amplifier 14 in FIG. Then, the switch S ₁ is applied with the gate pulse A which is on during the t _A period including a part of the t _F period and the t _R period. On the other hand, the switch S ₂ is applied with the gate pulse B which is on during the t _B period including the t _S period and a part of the t _R period. As a result, when the outputs of the switch S ₁ and the switch S ₂ are combined, the noise in the t _F period is inverted with respect to the input signal of the noise suppression circuit 12,
Noise during the t _S period can be in phase. Then, the signal components are obtained in the same phase. This means that the noise component has a repetition frequency twice that of the signal component. Then, this signal is integrated within one pixel period by the integrating circuit 17 and the reset pulse circuit 18 which controls this integrating circuit. As a result, the inversion noise and the in-phase noise, which are equal in amount within one pixel period, are canceled and only the signal component is extracted. At this time, the reset pulse component remains, so the LPF 19 is used to remove it and average the signal components. As a result, a signal component in which noise is significantly suppressed can be obtained. Here, since the gate pulses A and B have an opposite phase relationship, the mixed noises due to these pulses cancel each other out. Therefore, the S / N deterioration due to the mixing of the clamp pulse and the sample hold pulse, which was a problem in the conventional example, is not found in this example.

The same effect can be obtained by exchanging the gate pulses A and B in the embodiment of FIG. Also, the inverting amplifier 13 and the in-phase amplifier 14
It is the same even if is replaced. CC is important in this embodiment.
That is, the noise component is alternately inverted within one pixel period of the D output signal.

In this way, in this embodiment, noise can be reliably removed, so that a signal output with an extremely good S / N can be obtained.
As a result, a highly sensitive CCD TV camera can be realized.

Next, an embodiment of a concrete circuit configuration of the main part of the noise suppression circuit section of FIG. 1 will be described with reference to FIG. FIG. 3 shows a circuit system in which the inventor has conducted a design and an experiment and obtained a very preferable result as a method for carrying out the present invention. In this system, a double balanced differential circuit 30 is used in the portion composed of the inverting amplifier 13, the common-mode amplifier 14 and the gate circuit 15 composed of the switches S ₁ and S ₂ described in FIG. It uses an integrating circuit having a configuration.

Double balanced differential amplifier circuit 30 that inverts noise components alternately
Is a first differential amplifier circuit DA ₁ using transistors Q _A and Q _B as a differential pair and transistor Q _C as a constant current source, transistors Q _D and Q _E as a differential pair, and transistor Q _F Is constituted by two sets of differential circuits, that is, a second differential amplifier circuit DA ₂ having a constant current source. The bases of transistors Q _A and Q _{E and} the bases of transistors Q _B and Q _D are connected in common. The emitter of the constant current source composed of the transistors Q _C and Q _F is connected to the constant current circuit I. Then, a signal is input to the base of the current source transistor Q _{C, and} a predetermined DC voltage is input as a reference voltage from the resistor R30 to the base of the other current source transistor Q _F. The gate pulse B is input to the bases of the transistors Q _A and Q _E , and the gate pulse A is input to the bases of the transistors Q _B and Q _D. As a result, the added output waveform shown in FIG. 2 appears at the output terminal to which the collectors of the transistors Q _B and Q _E are commonly connected and the load resistor R ₃₁ is connected due to the effect of the differential circuit. Then, this output is integrated circuit 17
To enter.

The integrating circuit 17 is a transistor that constitutes the first integrating circuit.
Q _G , constant current circuit I _C , resistor R ₃₃ and integrating capacitor C ₃₀ ,
Transistor Q _H to reset this in 1 pixel cycle
And a resistor R ₃₄ and an integrating capacitor C ₃₁ that form a second integrating circuit, and a transistor Q ₁ and a resistor R ₃₅ that form an output stage emitter follower. In the first integrating circuit current obtained by the difference in the resistance R ₃₃ Accordingly determined current according to the constant current circuit I _C and the input signal is stored in the integrating capacitor C _30. This is the reset transistor Q _H
It is integrated over the period of ff. At this time, the noise of the input signal is 1
Since it is inverted half by half in the pixel period, it is canceled by integrating this. On the other hand, since the signal component is input with a unidirectional polarity, the integration amount is determined according to this amount. When the transistor Q _H is turned on by the reset pulse, the signal component stored in the capacitor C ₃₀ is discharged through the resistor R ₃₄ . At this time, if the time constants of the resistor R ₃₄ and the capacitor C ₃₁ are shorter than one pixel period and longer than the period when the reset pulse is on, the period of the signal component can be expanded. As a result, since the noise (N) can be suppressed and the signal component (S) can be increased, a large value can be obtained as S / N.

Thus, by using the circuit configuration of FIG. 3, the operation of alternately inverting the noise components within one pixel period is easily performed by the double balanced differential circuit. Further, in this circuit, the mixing of the gate pulse into the signal system is canceled by the effect of the differential circuit.

Next, a configuration example of an integrating circuit suitable for further exerting the effect of the embodiment of the present invention will be described. FIG. 4 is its block diagram, FIG.
The figure is an operation waveform diagram. The point of this embodiment is to surely increase the period of the signal component of the output of the integrating circuit described in FIG. The first integrator circuit is composed of a transistor Q ₁ , a resistor R ₄₁ and a capacitor C ₄₁ . The second integrating circuit is composed of a resistor R ₄₂ and a capacitor C ₄₂ . A first reset transistor Q ₂ is provided between these integrator circuits, and a second reset transistor Q ₃ is provided in parallel with the resistor R ₄₂ of the second integrator circuit. Transistor Q ₄ and resistor R _{43 form} an output stage emitter follower.

The operation of the integrating circuit will be described with reference to the waveform chart of FIG. A signal in which noise is alternately inverted within one pixel period is input to the base of the transistor Q ₁ . Then, the noise is canceled by the first integrating circuit, and only the signal component is extracted. At this time, the gate of the transistor Q ₂ is controlled by the reset pulse A, and when this pulse is off, the input signal and the constant current circuit I
The first integrator circuit performs an integrating operation by _C. Next, when the reset pulse A turns on, this integrated amount
Output to the drain side of Q ₂ . And transistor Q ₂
Is off in order to separate from the operation of the second integrating circuit below.
That is, if the signal component is output only during the period when the transistor Q ₂ is on, the signal period becomes shorter. Therefore, in order to extend this signal period, the second integration is performed using the time constant determined by the resistor R ₄₂ and the capacitor C ₄₂ . To do. As a result, the signal component is retained even when the transistor Q ₂ is turned off. Here, the integration time constant of the second integrating circuit (t ₁ or
t ₂ ) is one pixel period or more. And transistor Q ₃
Apply a reset pulse B to the gate of the transistor Q ₂
Make it off, on, off just before on. By doing so, the output signal becomes a signal component for almost the entire period within one pixel period, and the reset for each pixel can be surely performed. In addition,
Here, the transistor Q ₃ is connected to the power source side V _C to perform the second reset, but the same applies when the transistor Q ₃ is connected to the ground side.

As described above, in this embodiment, the double balanced differential circuit and the circuit that performs integration twice are used. As a result, noise can be suppressed reliably at high speed, and the expansion of the signal period can also be enabled, so that the high-frequency component flyback noise and noise caused by the jumping of the control pulse, which are seen in conventional noise suppression circuits, occur. do not do. As a result, the noise generated in the CCD output section included in the CCD output signal is a few electrons, which is 1/10 or less as compared with the conventional suppression circuit, which is an extremely large effect. The inventor has confirmed this by experiments.
This means that the sensitivity of the TV camera device using the CCD is 10 times higher than that using the conventional suppression circuit. This means that the practical range of CCD has been greatly expanded.

Although the embodiments of the present invention have been described above, the present invention can be variously modified and applied as listed below.

(A) Although the embodiments have been described for a black and white television camera, the present invention can be applied to a color television camera having a color filter provided on the CCD photosensitive surface. In this case, the noise suppression circuit of the present invention may be inserted before the color separation circuit. As a result, a highly sensitive color TV camera with less noise can be realized.

(B) In the description of the embodiment, the CCD image pickup device having the floating diffusion type signal charge detection unit which forms a pn diode with the semiconductor substrate has been described, but the signal charge detection of the floating gate structure using the MOS diode is described. Have a part
The same effect can be obtained by applying the present invention to a CCD image pickup device.

(C) The solid-state imaging device to which the present invention can be applied is not limited to the CCD, and the photosensitive pixel may have a MOS structure and the horizontal reading unit may have a CCD structure. Further, a laminated structure type CCD using a photoconductive film such as amorphous silicon in the photosensitive portion may be used. It may be a solid-state imaging device that has a signal charge storage unit between the vertical CCD and the horizontal CCD in order to increase the saturation signal current and operates to sweep out the signal charge of the vertical CCD register. The point common to these solid-state image pickup devices is that the signal charge detection unit is periodically reset.

(D) Although the above description has been made on the two-dimensional type solid-state imaging device, the same effect can be obtained by applying the present invention to the one-dimensional type solid-state imaging device.

(E) In the integrating circuit of FIGS. 3 and 4, the method of using the resistor and the capacitor for the first integration has been described, but the integrating circuit is not limited to this. Especially, if the constant current integration is performed, the effect of the present invention is further enhanced.

(F) Although the CCD output signal is immediately input to the noise suppression circuit in the description of FIG. 1, noise, hum, etc. mixed from the outside by first amplifying the CCD output signal and then inputting it to the noise suppression circuit The influence of can be reduced.
In this case, the band of the amplifier circuit needs to transmit a signal of one pixel period.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining its operation, FIG. 3 is a diagram for explaining a more concrete embodiment, and FIG. FIG. 5 is a block diagram of an embodiment of the present invention for more surely suppressing noise, FIG. 5 is a signal waveform diagram for explaining the operation thereof, and FIG. 6 is a CCD output section for explaining the cause of noise generation of CCD. FIG. 7 is a schematic diagram showing the operation waveform of each part for explaining the operation of FIG. 10 …… CCD image sensor, 11 …… Drive circuit, 12 …… Noise suppression circuit, 13 …… Inverting amplifier, 14 …… In-phase amplifier, 15 ……
Gate circuit, 16 ... Gate pulse circuit, 17 ... Integrator circuit, 18 ... Reset pulse circuit, 19 ... LPF, S ₁ …… First switch, S ₂ …… Second switch, DA ₁ , DA ₂ ...... Differential amplifier circuit, C ₃₀ , C ₄₁ …… First integration capacitor, C ₃₁ , C
₄₂ ... Second integration capacitor.

Claims (3)

[Claims] 1. A semiconductor substrate, a photosensitive pixel array, a signal charge transfer section for transferring signal charges photoelectrically converted in each photosensitive pixel,
A solid-state imaging device comprising a floating type charge detection unit for detecting the transferred signal charges, and a reset unit for resetting the potential of the charge detection unit to a predetermined potential for each cycle of the photosensitive pixel array. By driving the solid-state image sensor, one pixel period of the output signal is divided into a first period in which the image effective signal is not included and a second period in which the image effective signal is included in a period substantially equal to this period. Driving circuit for obtaining an output signal, a inverting amplifier and an in-phase amplifier juxtaposed to which the output signal of the solid-state imaging device is input, and gates for alternately taking out the outputs of these amplifiers in synchronization with the first and second periods. And a noise suppression circuit having an integrating circuit that is reset every pixel period and that synthesizes and integrates the output signals alternately extracted by the gate circuit. Solid-state imaging device. 2. The integrator circuit integrates the gate circuit output signal for each pixel period to cancel a noise component, and the output signal of the integrator circuit to integrate an effective signal period into a valid signal period. The solid-state imaging device according to claim 1, further comprising a second integrating circuit that expands. 3. The integrator circuit comprises a first integrator circuit and a second integrator circuit, the first integrator circuit is provided with a first reset circuit, and the second integrator circuit is provided with a second reset circuit. 2. The solid-state imaging device according to claim 1, wherein a circuit is provided, the time constant of the second integration circuit is set to 1 pixel cycle or more, and the reset cycle of the second reset circuit is set to 1 pixel cycle. apparatus.