JPH079919B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH079919B2 JPH079919B2 JP20940785A JP20940785A JPH079919B2 JP H079919 B2 JPH079919 B2 JP H079919B2 JP 20940785 A JP20940785 A JP 20940785A JP 20940785 A JP20940785 A JP 20940785A JP H079919 B2 JPH079919 B2 JP H079919B2
- Authority
- JP
- Japan
- Prior art keywords
- positive electrode
- electrode
- semiconductor device
- reinforcing plate
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D18/00—Thyristors
- H10D18/60—Gate-turn-off devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
Landscapes
- Die Bonding (AREA)
- Wire Bonding (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、大電力用として用いられる圧接構造方式の
半導体装置に関するものである。The present invention relates to a pressure contact structure type semiconductor device used for high power.
一般に、大電流を制御することの要求される大電力用の
半導体装置においては、大電流通電時の熱疲労等の問題
から電極取り出し方法としては、半田付やワイヤボンデ
ィング方式は用いられず、圧接構造方式が用いられる。In general, in a semiconductor device for high power required to control a large current, soldering or wire bonding method is not used as an electrode extraction method because of problems such as thermal fatigue during energization of a large current. A structural method is used.
第４図は圧接構造方式の従来のサイリスタの断面図で、
１はｎ形ベース層、２はｐ形ベース層、３はｎ形エミッ
タ層、４はｐ形エミッタ層、５は陽電極、６は陰電極、
７はゲート電極を示し、陽電極５は圧接時の機械的補強
の面から通常、モリブデン板やタングステン板等のシリ
コンと熱膨張率の近い金属で、半導体チップと接着層を
介して合金化が行われている。８は前記陰電極６に装着
されモリブデン板またはタングステン板等からなる電極
接続板、9,10はそれぞれパッケージに連結された陽電極
側および陰電極側の電極ブロックで、一般に矢印に示す
方向に圧接されている。また11はポリイミドワニス，シ
リコンゴム等の有機物質等からなる表面被覆材、J1，J2
はそれぞれ主耐圧を制御する接合である。FIG. 4 is a cross-sectional view of a conventional pressure contact thyristor.
1 is an n-type base layer, 2 is a p-type base layer, 3 is an n-type emitter layer, 4 is a p-type emitter layer, 5 is a positive electrode, 6 is a negative electrode,
Reference numeral 7 denotes a gate electrode, and the positive electrode 5 is usually a metal having a coefficient of thermal expansion close to that of silicon such as molybdenum plate or tungsten plate in terms of mechanical reinforcement at the time of pressure welding, and alloyed with a semiconductor chip through an adhesive layer. Has been done. Reference numeral 8 is an electrode connection plate which is attached to the negative electrode 6 and is made of a molybdenum plate or a tungsten plate, and 9 and 10 are positive electrode side and negative electrode side electrode blocks respectively connected to the package, which are generally pressure-contacted in a direction indicated by an arrow. Has been done. Further, 11 is a surface coating material made of an organic material such as polyimide varnish or silicone rubber, J 1 , J 2
Are junctions for controlling the main breakdown voltage.
通常の圧接構造方式の半導体装置では、これらの接合
J1,J2の終端が側面に結ぶメサ構造が用いられている。
圧接構造方式の半導体装置でメサ構造が用いられる理由
としては、陽電極５を形成するための合金化時に、プレ
ーナ構造の場合にはプレーナ接合を被覆する絶縁膜が汚
染されて素子の耐圧特性が劣化することがあるか、メサ
構造では合金後に接合の表面処理が可能なとがあげられ
る。In a normal pressure-welded structure semiconductor device, these junctions are
A mesa structure in which the ends of J 1 and J 2 are connected to the side surface is used.
The reason why the mesa structure is used in the pressure contact type semiconductor device is that, when alloying to form the positive electrode 5, in the case of the planar structure, the insulating film covering the planar junction is contaminated and the withstand voltage characteristic of the element is reduced. It may be deteriorated, or the mesa structure may allow the surface treatment of the joint after alloying.
上記のような従来の圧接構造方式の半導体装置において
は、プレーナ構造の半導体チップの場合、陽電極の合金
化の際にプレーナ接合を被覆する絶縁膜の汚染により耐
圧特性が劣化し、またメサ構造の半導体チップの場合、
ポリイミドワニス，シリコンゴム等の有機物質が表面被
覆材11として用いられるため、素子の品質が安定し難
く、さらにはモリブデン板やタングステン板の電極接続
板が取付けられた状態で表面処理を実施するため、工程
が複雑になるとともに、作業性が非常に悪くなるという
問題点があつた。In the conventional pressure contact type semiconductor device as described above, in the case of a semiconductor chip having a planar structure, breakdown voltage characteristics are deteriorated due to contamination of an insulating film covering the planar junction when alloying the positive electrode, and the mesa structure is also used. For semiconductor chips of
Since an organic material such as polyimide varnish or silicon rubber is used as the surface coating material 11, it is difficult to stabilize the quality of the element, and further, the surface treatment is performed with the electrode connection plate such as the molybdenum plate or the tungsten plate attached. However, there is a problem that the process becomes complicated and the workability becomes very poor.
この発明は、かかる問題点を解決するためになされたも
ので、素子の品質を安定させることができ、かつ製造工
程が簡単で作業性のよい圧接構造方式の半導体装置を得
ることを目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor device of a pressure contact structure type which can stabilize the quality of elements, has a simple manufacturing process, and has good workability. .
この発明に係る半導体装置は、プレーナ構造の半導体チ
ップの陽電極と陽電極側の電極ブロック間に陽電極と別
体に分離された陽電極補強板を介在させ、陰電極側の電
極ブロックと陽電極側の電極ブロックとで押圧し、陽電
極補強板を半導体チップに圧接させたものである。In the semiconductor device according to the present invention, a positive electrode reinforcing plate, which is separate from the positive electrode, is interposed between the positive electrode and the positive electrode side electrode block of the semiconductor chip having the planar structure, and the positive electrode side electrode block and the positive electrode side electrode block are separated from each other. The positive electrode reinforcing plate is pressed against the semiconductor chip by pressing with the electrode block on the electrode side.
この発明においては、高温熱処理による半導体チップの
陽電極の合金化が不要となり、パッシベーション処理に
よるウエハ表面の酸化膜が金属で汚染されることがな
く、耐圧特性の劣化を防止できる。In the present invention, it is not necessary to alloy the positive electrode of the semiconductor chip by high temperature heat treatment, the oxide film on the wafer surface is not contaminated by metal due to the passivation process, and deterioration of the withstand voltage characteristic can be prevented.
第１図はこの発明の半導体装置の一実施例を示すゲート
ターンオフサイリスタ（以下GTOという）の断面図で、2
1はｎ形ベース層、22はｐ形ベース層、23はｎ形エミッ
タ層、24はｐ形エミッタ層、25はガードリング領域、2
6,27,28はそれぞれA1等の金属からなる陽電極，ゲート
電極，陰電極であり、これらでプレーナ構造の半導体チ
ップ20が構成されている。29,30はそれぞれ陽電極側お
よび陰電極側の電極ブロック、31は前記陰電極28上に載
置したモリブデンまたはタングステン等からなる電極接
続板、32は前記陽電極26と陽電極側の電極ブロック29間
に介在させたモリブデンまたはタングステン等からなる
陽電極補強板である。FIG. 1 is a sectional view of a gate turn-off thyristor (hereinafter referred to as GTO) showing an embodiment of the semiconductor device of the present invention.
1 is an n-type base layer, 22 is a p-type base layer, 23 is an n-type emitter layer, 24 is a p-type emitter layer, 25 is a guard ring region, 2
Reference numerals 6, 27 and 28 denote a positive electrode, a gate electrode and a negative electrode made of a metal such as A1, respectively, which form the semiconductor chip 20 having a planar structure. 29 and 30 are electrode blocks on the positive electrode side and the negative electrode side, 31 is an electrode connection plate made of molybdenum, tungsten or the like placed on the negative electrode 28, 32 is an electrode block on the positive electrode 26 and the positive electrode side It is a positive electrode reinforcing plate made of molybdenum or tungsten interposed between 29.
このGTOでは、陽電極26と陽電極側の電極ブロック29間
に陽電極補強板32を介在させることにより、圧接時の機
械的ストレスを緩衝することができ、従来のように陽電
極の合金化を行う必要がなくなる。特に、半導体チップ
20をプレーナ構造とすることができることにより、ウエ
ハ状態でのパッシベーションを行うことが可能となり、
従来のメサ構造の半導体装置のように陽電極の合金化後
に有機物質を用いて接合部の表面処理を行う必要がなく
なる。このため、素子の品質の安定化が図れるうえ作業
が容易となり、１枚のウエハから多数のエレメントを切
り出すマルチチップ構造の場合には特に作業が容易とな
る。In this GTO, by interposing the positive electrode reinforcing plate 32 between the positive electrode 26 and the electrode block 29 on the positive electrode side, it is possible to buffer the mechanical stress at the time of pressure contact, and the positive electrode is alloyed as in the past. You don't have to. Especially semiconductor chips
Since 20 can have a planar structure, it becomes possible to perform passivation in a wafer state,
There is no need to perform the surface treatment of the joint portion using the organic substance after alloying the positive electrode as in the conventional semiconductor device having a mesa structure. Therefore, the quality of the device can be stabilized and the work is easy, and the work is particularly easy in the case of a multi-chip structure in which a large number of elements are cut out from one wafer.
なお、このGTOは、ガードリング領域25を設けて接合の
屈曲部Ａにおける電界集中を緩和し、プレーナ構造でメ
サ構造に近い耐圧を得ている。In this GTO, the guard ring region 25 is provided to reduce the electric field concentration at the bent portion A of the junction, and the planar structure has a breakdown voltage close to that of the mesa structure.
またｐ形エミッタ層24とｎ形ベース層21とを陽電極26に
よつて短絡したアノード−エミッタ短絡構造とすること
により、ｎ形ベース層21内の蓄積キャリアを消滅しやす
くし、動作の高速化を図っている。Further, the p-type emitter layer 24 and the n-type base layer 21 are short-circuited by the positive electrode 26 so as to have an anode-emitter short-circuit structure, so that the accumulated carriers in the n-type base layer 21 can be easily erased, and the operation speed can be increased. It is trying to make it.
第２図は順方向耐圧の向上以外に逆方向耐圧の向上を図
ったこの発明の半導体装置の実施例を示す断面図で、こ
の実施例ではガードリング領域25をアノード側のｐ形エ
ミッタ層24の両側に隣接するｎ形ベース層21内に設けた
構造としている。FIG. 2 is a cross-sectional view showing an embodiment of the semiconductor device of the present invention, which is intended to improve the reverse breakdown voltage in addition to the forward breakdown voltage. In this embodiment, the guard ring region 25 is formed on the anode side of the p-type emitter layer 24. The structure is provided in the n-type base layer 21 adjacent to both sides of the.
また第３図も順方向耐圧の向上以外に逆方向耐圧の向上
を図ったこの発明の半導体装置のさらに他の実施例を示
す断面図で、この実施例では上記第２図に示した実施例
のようにアノード側にガードリング領域25を設けるかわ
りに、ｐ形エミッタ層24の両側をカソード側の表面へ伸
ばした構造としている。FIG. 3 is a sectional view showing still another embodiment of the semiconductor device of the present invention, which is intended to improve the reverse breakdown voltage in addition to the forward breakdown voltage. In this embodiment, the embodiment shown in FIG. Instead of providing the guard ring region 25 on the anode side as described above, both sides of the p-type emitter layer 24 are extended to the surface on the cathode side.
なお、上記各実施例でGTOを用いて説明したが、この発
明はこれに限定されるものでなく、通常のサイリスタ，
トランジスタあるいはダイオード等に応用してもよい。Although the above embodiments have been described using the GTO, the present invention is not limited to this, and a normal thyristor,
It may be applied to a transistor or a diode.
この発明は以上説明したとおり、プレーナ構造の半導体
チップの陽電極と陰電極の電極ブロック間に、陽電極と
別体に分離された陽電極補強板を介在させ、陰電極側の
電極ブロックと陽電極側の電極ブロックとで押圧し、陽
電極補強板を半導体チップに圧接させたので、高温熱処
理による陽電極の合金化が不要となり、パッシベーショ
ン処理によるウエハ表面の酸化膜が汚染されることがな
く耐圧特性の劣化を防止でき、またメサ構造の半導体チ
ップのように有機物質を用いて接合部の表面処理を行う
必要がないので、素子の安定化が図れるうえ、製造工程
が簡単で作業性がよくなるという効果がある。As described above, the present invention interposes the positive electrode reinforcing plate, which is separated from the positive electrode, between the positive and negative electrode blocks of the semiconductor chip having the planar structure, and the negative electrode side electrode block and the positive electrode reinforcing plate are separated from each other. Since the positive electrode reinforcing plate is pressed against the semiconductor chip by pressing with the electrode block on the electrode side, alloying of the positive electrode by high temperature heat treatment is unnecessary, and the oxide film on the wafer surface is not contaminated by passivation processing. It is possible to prevent the breakdown voltage characteristics from deteriorating, and because it is not necessary to perform the surface treatment of the joint part using an organic substance like a semiconductor chip with a mesa structure, it is possible to stabilize the element, and the manufacturing process is simple and workability is improved. It has the effect of improving.
第１図はこの発明の半導体装置の一実施例であるGTOの
断面図、第２図はこの発明の半導体装置の他の実施例を
示す断面図、第３図はこの発明の半導体装置のさらに他
の実施例を示す断面図、第４図は圧接構造方式の従来の
サイリスタの断面図である。 図において、20はプレーナ構造の半導体チップ、26は陽
電極、28は陰電極、29は陽電極側の電極ブロック、30は
陰電極側の電極ブロック、32は陽電極補強板である。 なお、各図中の同一符号は同一または相当部分を示す。FIG. 1 is a sectional view of a GTO which is an embodiment of the semiconductor device of the present invention, FIG. 2 is a sectional view showing another embodiment of the semiconductor device of the present invention, and FIG. FIG. 4 is a cross-sectional view showing another embodiment, and FIG. 4 is a cross-sectional view of a conventional pressure contact structure type thyristor. In the figure, 20 is a semiconductor chip having a planar structure, 26 is a positive electrode, 28 is a negative electrode, 29 is an electrode block on the positive electrode side, 30 is an electrode block on the negative electrode side, and 32 is a positive electrode reinforcing plate. The same reference numerals in each drawing indicate the same or corresponding parts.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭56−153767（ＪＰ，Ａ) 特開 昭57−78178（ＪＰ，Ａ) 特開 昭59−218774（ＪＰ，Ａ) 特開 昭58−101433（ＪＰ，Ａ) 特開 昭56−124238（ＪＰ，Ａ) 特開 昭57−181131（ＪＰ，Ａ) 特開 昭58−176954（ＪＰ，Ａ) 特開 昭55−121654（ＪＰ，Ａ) ─────────────────────────────────────────────────── --Continued from the front page (56) Reference JP-A-56-153767 (JP, A) JP-A-57-78178 (JP, A) JP-A-59-218774 (JP, A) JP-A-58- 101433 (JP, A) JP 56-124238 (JP, A) JP 57-181131 (JP, A) JP 58-176954 (JP, A) JP 55-121654 (JP, A)
Claims (1)
面上に陽電極及び陰電極が配設された、プレーナ構造の
半導体チップと、 上記陽電極と分離された別体であって、上記陽電極と接
触して配設された陽電極補強板と、 この陽電極補強板を介して上記陽電極と対向し、また陰
電極と対向してそれぞれの側に配設されるとともにそれ
ぞれの側から押圧し上記陽電極補強板を上記半導体チッ
プに圧接する電極ブロックと、 を備えた半導体装置。1. A semiconductor chip having a planar structure, having first and second main surfaces, on each of which a positive electrode and a negative electrode are disposed, and a separate body separated from the positive electrode. And a positive electrode reinforcing plate disposed in contact with the positive electrode, and facing the positive electrode via the positive electrode reinforcing plate, and facing the negative electrode on each side. And a positive electrode reinforcing plate that is pressed from each side and presses the positive electrode reinforcing plate against the semiconductor chip.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20940785A JPH079919B2 (en) | 1985-09-20 | 1985-09-20 | Semiconductor device |
| EP86902027A EP0238665A1 (en) | 1985-09-20 | 1986-03-27 | Semiconductor device |
| PCT/JP1986/000145 WO1987001866A1 (en) | 1985-09-20 | 1986-03-27 | Semiconductor device |
| IT2165586A IT1213490B (en) | 1985-09-20 | 1986-09-09 | SEMICONDUCTOR DEVICE WITH A STRUCTURE OF CONTACTS OPENING FOR USE IN HIGH POWER APPLICATIONS. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20940785A JPH079919B2 (en) | 1985-09-20 | 1985-09-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6269522A JPS6269522A (en) | 1987-03-30 |
| JPH079919B2 true JPH079919B2 (en) | 1995-02-01 |
Family
ID=16572372
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20940785A Expired - Lifetime JPH079919B2 (en) | 1985-09-20 | 1985-09-20 | Semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0238665A1 (en) |
| JP (1) | JPH079919B2 (en) |
| IT (1) | IT1213490B (en) |
| WO (1) | WO1987001866A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5040051A (en) * | 1988-12-05 | 1991-08-13 | Sundstrand Corporation | Hydrostatic clamp and method for compression type power semiconductors |
| DE58905844D1 (en) * | 1989-02-02 | 1993-11-11 | Asea Brown Boveri | Pressure-contacted semiconductor device. |
| US5210601A (en) * | 1989-10-31 | 1993-05-11 | Kabushiki Kaisha Toshiba | Compression contacted semiconductor device and method for making of the same |
| JPH0744264B2 (en) * | 1989-10-31 | 1995-05-15 | 株式会社東芝 | Pressure contact type semiconductor device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4099201A (en) * | 1977-04-11 | 1978-07-04 | General Electric Company | Semiconductor rectifier assembly having an insulating material therein that evolves gases when exposed to an arc |
| JPS56153767A (en) * | 1980-04-28 | 1981-11-27 | Mitsubishi Electric Corp | Manufacture of planar type thyristor |
| JPS5778178A (en) * | 1980-11-04 | 1982-05-15 | Toshiba Corp | Input protective circuit |
| FR2517471B1 (en) * | 1981-12-02 | 1985-08-02 | Silicium Semiconducteur Ssc | PRESS BOX MOUNTING OF POWER COMPONENTS WITH BRANCHED ELECTRODES STRUCTURE |
| JPS59218774A (en) * | 1983-05-26 | 1984-12-10 | Nec Corp | Thyristor |
-
1985
- 1985-09-20 JP JP20940785A patent/JPH079919B2/en not_active Expired - Lifetime
-
1986
- 1986-03-27 WO PCT/JP1986/000145 patent/WO1987001866A1/en not_active Ceased
- 1986-03-27 EP EP86902027A patent/EP0238665A1/en not_active Withdrawn
- 1986-09-09 IT IT2165586A patent/IT1213490B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| WO1987001866A1 (en) | 1987-03-26 |
| EP0238665A1 (en) | 1987-09-30 |
| IT8621655A0 (en) | 1986-09-09 |
| JPS6269522A (en) | 1987-03-30 |
| IT1213490B (en) | 1989-12-20 |
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