JPH079937B2 - Wiring structure of semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a wiring method in a semiconductor device, and more particularly to a shape of a multilayer wiring.

[Conventional technology]

Conventionally, wiring on a substrate of a semiconductor device is generally used in a plurality of layers, and the wiring of each layer is often orthogonal to the wiring direction of the layers above and below the wiring. Fig. 3 (a)
Is a cross-sectional view of a conventional two-layer wiring, and FIG. 6B is a plan view in which the interlayer insulating film is omitted. In these figures, 3
The first layer wirings 11 of the book are formed in parallel with each other at a certain interval,
The second layer wiring 4 is laid on the upper portion in a direction orthogonal to the second layer wiring 4. An insulating film 3 is formed between these layers.

[Problems to be solved by the invention]

In the conventional wiring in the semiconductor device described above, there is a space between the wirings in the lower layer (aspect ratio with the film thickness of the wiring is around 1).
In the case (1), there is a drawback that the upper layer wiring is constricted due to the step difference of the lower layer wiring, and a breakage or a reduction in the withstand current amount due to a reduction in the cross-sectional area is likely to occur. Further, in order to eliminate the constriction of the upper layer wiring, widening the distance between the lower layer wirings has drawbacks such as a reduction in the number of wirings in the same region and a reduction in the wiring width. On the contrary, if the distance between the lower layer wirings is narrowed uniformly, there is a drawback that a short circuit between the lower layer wirings and an increase in side capacitance of the wirings are caused.

[Means for solving problems]

In the present invention with respect to the above-mentioned problems, by narrowing the interval between the lower layer wirings laid parallel to and adjacent to each other in the vicinity of the intersection with the wiring laid orthogonally on the upper layer,
The constriction of the upper wiring is reduced to prevent the upper wiring from breaking.

〔Example〕

 Next, the present invention will be described with reference to examples.

FIG. 1 (a) is a sectional view of an embodiment of the present invention, and FIG. 1 (b).
FIG. 3 is a plan view showing an interlayer insulating film omitted. In these figures, three first layer wirings 1 are formed in parallel with each other, and a second layer wiring 4 is laid on the upper part of the first layer wirings 1 with an interlayer insulating film 3 interposed therebetween. Then the first of the three
In the layer wiring 1, the line width is laterally bulged in the vicinity of the orthogonal portion to the second layer wiring 4, and as a result, the interval between adjacent lines is partially narrowed. In this way, the interval between a number of parallel lower layer wirings orthogonal to the upper layer wirings is locally narrowed in the vicinity of the intersecting portions orthogonal to each other. To be prevented. On the other hand, the narrower the line spacing, the greater the risk of short-circuiting. However, in the present invention, the line spacing is only locally narrowed, so the yield reduction due to short-circuiting is small.

2 (a) and 2 (b) are a sectional view and a plan view of the second embodiment of the present invention. In FIGS. 2A and 2B, four parallel first-layer wirings 2 have two wirings located on both sides with a constant width in the vicinity of an intersection orthogonal to the wiring 4 in the upper layer. Although the two wires in the middle extend straight, even if the width is constant, the wires on both sides are bent toward each other to make a business trip, and the intervals are narrowed, while the two wires are separated from each other. The intervals are wide. In this example, the upper layer wiring is prevented from being broken by narrowing the upper layer wiring at one side and narrowing it at the other side, where the narrowed space is the tightest. Further, since the wiring width is constant, there is an advantage that the inter-substrate capacitance and the interlayer capacitance are the same as those of the conventional wiring.

〔The invention's effect〕

As described above, the present invention has the effect of suppressing disconnection and reduction of the cross-sectional area of the upper layer wiring by narrowing the interval of the lower layer wiring at the intersection with the upper layer wiring, and improving the yield and reliability of the semiconductor device. .

[Brief description of drawings]

1 (a) and 1 (b) are a cross-sectional view and a plan view with an interlayer insulating film omitted, respectively, of a first embodiment of the present invention. 2 (a) and 2 (b) are a sectional view and a plan view, respectively, of a second embodiment of the present invention. 3 (a) and 3 (b) are a cross-sectional view showing a wiring structure of a conventional semiconductor device and a plan view in which an interlayer insulating film is omitted. 1,2,11 …… First layer (lower layer) wiring, 3 …… Interlayer insulating film, 4
...... Second layer (upper layer) wiring.

Claims (1)

[Claims] 1. A plurality of lower layer wirings provided adjacent to each other in parallel, and an upper layer wiring which is insulated from any of the lower layer wirings by an insulating film covering the lower layer wirings and intersects with the lower layer wirings. A wiring structure of a semiconductor device, wherein an interval between lower layer wirings is narrower at an intersection with the upper layer wiring than in other portions.