JPH0799455B2 - Plane display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device, and more particularly to a protection circuit for a flat panel display device suitable for controlling a scan of a display by an external signal.

[Background of the Invention]

As a display panel protection circuit, for example, Japanese Patent Publication Sho 58
As disclosed in Japanese Patent Laid-Open No. 36794/1992, there is known one that detects the output of a panel driving transistor and lowers the driving power supply voltage to protect the panel when an abnormality occurs.

This method is a reliable method because it directly detects the panel drive output, but many detection circuits must be attached to the output, and a large-power transistor is required to reduce the power supply voltage. There is a problem that it will increase.

Before entering the detailed description of the present invention, the drive circuit of the flat display and the timing of the display scan will be described.

In order to display a flat display, it is common to input display data, a display data transfer clock, a scan signal and a scan reset signal from the outside,
If for some reason these signals are not input correctly and the same part of the display panel continues to light up, the same part of the display panel is detected by detecting this and performing blanking or scanning according to each timing. Protect the display panel by keeping it on for a long time.

Among flat display devices that display in a time-division manner, those that control scanning by an external signal are already known, and an example thereof is shown in a block diagram in FIG.

Electrode 1 is an electrode for controlling scanning, and a voltage is applied to each electrode in the order of 1a, 1b, ...

The electrode 2 is an electrode that specifies the portion to be displayed, and changes in synchronization with the scanning of the electrode 1 by applying a voltage to the portion of the electrode 1 that is selected and displayed.

The flat display panel 3 is a flat display device in which a display is displayed in a portion where a voltage is applied to the electrodes 1 and 2 at the same time.

The shift register 4 is for taking in the data to be applied to the electrode 2 from the outside, and taking in the data (DATA) serially inputted from the outside in synchronization with the clock signal (CLK),
Convert to parallel and output.

The latch flip-flop 5 outputs the parallel output of the shift register 4 to the latch and driver 6 in synchronization with the scan signal HS.

The driver 6 converts the output of the latch flip-flop 5 into a drive voltage for the flat display panel and supplies it to the electrode 2.

The shift register 7 takes in the scan position reset signal VS in synchronization with the scan signal HS. Hold this VS pulse while one HS pulse is input, cut off the VS pulse until the next HS pulse enters, and add the VS pulse again after HS has entered the number of electrodes 1 or more. As a result, the output of the shift register 7 is sequentially output from S1a to S1 as shown in FIG.

The driver 8 converts the sequentially output data of the shift register 7 into a drive voltage for the display panel and applies it to the electrodes 1 to perform time-division scanning. At this time, the intersecting portion of the electrodes 1 and 2 to which the driving voltage is applied appears as a display on the flat display panel 3, and the output of the electrode 2 is changed in synchronization with the scanning of the electrode 1 to change the flat display 3 Arbitrary characters and figures can be displayed on the screen.

However, in the circuit of FIG. 6, although the inputs of the drivers 6 and 8 are switched instantaneously, the voltage applied to the electrodes 1 and 2 is slightly shifted due to the characteristics of the drivers 6 and 8 and the flat display panel 3, so that it is unnecessary. The display may appear on the wrong part.

If the VS and HS timings are not correctly input for some reason, the timing at which voltage is applied to electrode 1 becomes abnormal, and voltage may continue to be applied to the same electrode or voltage may be applied to multiple electrodes simultaneously. If the ratio of the display time to the non-display time becomes high, there is a possibility that the damage due to heat generation, the seizure, etc. may occur.

An example thereof is shown in the timing charts of FIGS.
This figure is a timing chart when it is assumed that VS is taken into the shift register 7 at the rise of HS and a voltage is applied to the electrode 1 to display when S1a to S1 are at the H level.

FIG. 8 shows an example of when the HS is stopped. Since the operation of the shift register 7 is stopped while the HS is stopped, the voltage remains applied to one electrode of the electrodes 1.

FIG. 9 shows an example when the VS pulse width becomes long. Since the data for the VS pulse width is stored in the shift register 7, the time for applying the voltage to each electrode of the electrode 1 becomes long, and at the same time, a plurality of electrodes are formed. A voltage is applied to the electrode of and the display is incorrect. Also VS is H
When stopped at the level, the voltage continues to be applied to all the electrodes of the electrode 1.

Fig. 10 shows an example when the VS cycle becomes shorter than the specified cycle. Since VS enters before the data entered in the shift register 7 is shifted by the number of electrodes of electrode 1, the voltage is applied to multiple electrodes. Is added, the ratio of display time to non-display time increases.

[Object of the Invention]

SUMMARY OF THE INVENTION It is an object of the present invention to prevent, in a flat display device that performs a time-division scan display, an adverse effect on a display panel due to a scan stop with a simple circuit.

[Outline of Invention]

The present invention features a flat panel display device that, when a scan signal for selecting a row or a column of the flat panel display device is stopped, stops the output of a driver that selects at least a row or a column in response thereto.

Example of Invention

An embodiment of the present invention will be described below with reference to FIGS.

The drive circuit of the flat panel display device shown in FIG.
A protection circuit according to the present invention is added to the circuit shown in the figure.

The timers 9, 10, 11 and 12 are one-shot multivibrators that operate at the rising edge or falling edge of the input signal and output the signal for a fixed time. The following description with reference to FIGS. 2-5 assumes that all these timers operate on the rising edge of the input signal.

The timer 9 outputs a pulse having a constant width when the outputs of the drivers 6 and 8 change, and stops the output of the driver all at once, thereby preventing the display of unnecessary portions. An example of the operation at this time is shown in FIG. In addition, timer 9
The setting time is set to a sufficient value depending on the characteristics of the driver and the display panel, and the drivers 6 and 8 that can stop the output by an external signal are used.

The timer 10 is set to be slightly longer than the cycle time THs of the HS signal shown in Fig. 2 so that it is always retriggered when the HS is input correctly, and outputs when the HS stops for a certain time or longer. , Stop the drivers 6 and 8.

FIG. 3 shows an operation example when the HS is temporarily stopped. When the HS stops, the output of the timer 10 becomes H level after a certain period of time, and all the outputs of the drivers 6 and 8 stop, so that the same part does not continue to be displayed as shown in FIG.

By setting the timer 11 to be equal to or shorter than THs in FIG. 2, even if the pulse width of the VS signal cycle time TVs becomes long or stopped, the operation as shown in FIG. 4 is performed. As shown in FIG. 9, the shift register 7 does not contain a plurality of data, and only one data at a time. However, in this case, if VS enters before the data of the shift register 7 is shifted by the number of electrodes 1, a plurality of data will enter the shift register 7 as shown in FIG. 10, so the timer 12 is input to the timer 11 and VS. It is provided between.

The timer 12 is set to be slightly shorter than the TVs shown in FIG. 2, and normally operates as shown in FIG. 2, and the timer 11 is operated by the rise of the output. When the VS cycle becomes shorter than TVs, the VS pulse is applied to the timer 12 before the output falls as shown in FIG. Therefore, no pulse is input to the timer 11, a signal to be input to the shift register 7 is not created, and a plurality of data is not input to the shift register 7.

It should be noted that even if DATA and CLK which are inputs to the shift register 4 become abnormal, the data input to the shift register 4 becomes indefinite and the display only becomes indefinite, so that it does not adversely affect the display panel.

As described above, the present embodiment has an effect of preventing the display panel from being adversely affected even if each signal becomes abnormal.

〔The invention's effect〕

According to the present invention, even if the scan signal is stopped, the driver output of the display device can be stopped by the timer, so that it is possible to prevent the adverse effect on the display panel due to the stop of the scan.

[Brief description of drawings]

FIG. 1 is a block diagram of a drive circuit for a flat panel display to which a protection circuit according to an embodiment of the present invention is added, and FIG.
Timing chart for normal operation in the circuit shown in the figure, No. 3
FIG. 4, FIG. 4 and FIG. 5 are timing charts when an input signal becomes abnormal in the circuit shown in FIG. 1, FIG. 6 is a block diagram showing an example of a drive circuit of a flat display, and FIG. Timing charts during normal operation of the circuit shown in the figure, and FIGS. 8, 9, and 10 are timing charts when the input signal becomes abnormal in the circuit shown in FIG. 3 ... Flat display panel, 4, 7 ... Shift register, 5 ... Latch flip-flop, 6, 8 ... Driver, 9, 10, 11, 12 ... Timer.

Continuation of front page (56) References JP-A-52-128178 (JP, A) JP-A-57-148794 (JP, A)

Claims (2)

[Claims] 1. A first drive signal for outputting a first drive signal corresponding to display data to a row or a column of a plurality of electrodes intersecting in a matrix direction.
And the output of the second driving means for inputting the scan pulse signal of the predetermined cycle and the scan reset signal of the predetermined cycle and outputting the second drive signal for sequentially selecting the column or row electrodes. In the flat display device that performs display, the second driving unit receives the scan pulse signal and generates a first pulse signal having a pulse width smaller than the predetermined period of the scan pulse signal. A second pulse generating means for generating the second pulse when the scan pulse signal is input and the scan pulse signal is not input for a period longer than the predetermined period.
And a means for stopping the output of at least one of the first and second driving means in response to the outputs of the first and second pulse generating means. apparatus. 2. A first driving signal which outputs a first driving signal corresponding to display data to a row or a column of a plurality of electrodes intersecting in a matrix direction.
And the output of the second driving means for inputting the scan pulse signal of the predetermined cycle and the scan reset signal of the predetermined cycle and outputting the second drive signal for sequentially selecting the column or row electrodes. In the flat panel display device that performs display, the second driving unit generates a third pulse having a pulse width of the predetermined period or less of the scan pulse signal in response to the scan reset signal. A plane including pulse generating means and means for stopping the third pulse generating means when the scan reset signal is input and the cycle becomes smaller than the predetermined cycle of the scan reset signal. Display device.