JPH0799465B2 - Display device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a display device including a plurality of display elements arranged in a matrix.

Background Art For example, one display element such as a light emitting diode (hereinafter referred to as LED) is set as one dot, and this is arranged in a matrix of n rows × m columns dot, and the display element of the selected dot is made to emit light to display characters. A display unit (hereinafter, referred to as a display panel) adapted to display a graphic is used. Such a display panel has, for example, 8 × 8 = 64 dots or 16 × 16 light emitting elements on one panel.
= 256 dots, and one such display panel is used as one unit, and the multiple units are connected vertically or horizontally to be used as a promotional medium for electronic news or various display boards. There is.

FIG. 5 is a perspective view showing the appearance of a display panel according to the prior art. The display surface 22 of the display panel 21 is provided with a plurality of display elements 23 realized by, for example, 8 × 8 = 64 LEDs arranged in a matrix of 8 rows by 8 columns. There is.

FIG. 6 is an electric circuit diagram of the display panel 21 of the prior art shown in FIG. 5, and FIG. 7 is a time chart showing its operation. The operation of the prior art will be described with reference to FIGS. 6 and 7 together. In FIG. 7A, 64 dots of data (00) to (77) relating to turning on or off of the 64 dots LED 23 are serially input to the serial data input terminal DI of the shift register 24 through the line l21. .

FIG. 7B shows the shift register 24 via the line l24.
2 shows the waveform of the first clock signal CLK1 applied to the clock input terminal CK1 of FIG. The above data is serially input to the shift register 24 and converted in parallel from the first clock. At the eighth clock timing time t1, eight bits of data (00) to (07) of the above data are derived from the shift register 24 to the line l23.

FIG. 7C shows the clock input terminal CK2 of the latch 25 via the line l24 for every 8 pulses of the first clock signal.
Shows the waveform of the second clock signal CLK2 applied to the shift register 24. At each timing, the latch 25 holds the output data of the shift register 24 derived on the above line l23, and the shift register 24 continues from time t1 to time t2. In between, the next 8-bit data (10) to (17) are input.

Meanwhile, held by latch 25 (00)-(07)
The data output of L is the logical output of latch 25 from line l25.
Each of the anode lines A0 to A7 of the LED 23 is individually supplied through a buffer 26 that amplifies the ED23 to a drivable current output, and further through series resistors R0 to R7 (indicated by reference numeral R when collectively referred to). .

At the same time, in response to the second clock signal CLK2, as shown in FIG. 7 (D), the first cathode line K of the LED 23
0 becomes the “L” level, the corresponding LED 23 lights up, and the first line is displayed. Then, at time t2, the next 8-bit data (10) to (17) are output, and the second cathode line K2 becomes the "L" level as shown in FIG. The line is displayed. The next 8 at time t3
Bit data (20) to (27) are output, and the third cathode line K2 is "L" as shown in FIG. 7 (F).
The third line is displayed as the level.

After that, by repeating the same operation eight times, LED2
The display of 3 dots of 64 dots is performed, and further, by repeating the above operation sequentially and continuously, the LED 23 is dynamically driven and turned on or off to perform a desired display. When one row of cathode lines is at "L" level, the other cathode lines are all kept at "H" level, which enables the dynamic drive.

Although the operation of the display panel 21 for one unit has been described in the above description of the prior art, normally, a plurality of display panels 21 are used and the display panels 21a, 21b, 21c, ... Are used as shown in FIG. , A serial input terminal DI and a serial output terminal DO of the shift registers 24a, 24b, 24c, ... Are sequentially connected, and the first and second clock signal terminals CK1 and CK2 and L (not shown) are connected.
The cathode terminals K0 to K7 of ED23 are connected in parallel. However, the second
The cycle of the clock signal CLK2 is eight times as long as that of the first clock signal CLK1 in the case of FIG. 6, but the cycle is further extended according to the number of added units to operate.

However, in the display according to the above-described prior art, the lighting data of the LED 23 is either lighting or extinguishing, and the brightness thereof is also uniquely determined, resulting in a gradationless display image. If the character to be displayed is a character, it will be satisfied, but
When it is desired to display an image with many dots such as a picture and with gradation, it becomes impossible to display. Although various methods have been proposed in the past for expressing gradations, all of them have a complicated circuit structure and are expensive and uneconomical.

For example, there is a prior art in which a plurality of LEDs are used in one dot, and the LEDs are selectively turned on to obtain gradation.
A special panel in which the pixels are arranged in a matrix is required, which is expensive, and fine gradation cannot be obtained.

It is an object of the present invention to provide a display device which solves the above-mentioned problems and can deal with so-called monotone images that do not require gradation and multi-gradation images, and that can easily realize this. It is to be.

Embodiment FIG. 1 is a circuit diagram for explaining the operation of an embodiment of the present invention. The light emitting diode LD, which is a display element, is a one-dot light emitting element, and is supplied with power from the DC power source E via series circuits of switches Sa, Sb, Sc and resistors Ra, Rb, Rc.
When the switches Sa, Sb, Sc are all OFF, the power does not flow,
The light emitting diode LD does not light up. Switch Sa, Sb, Sc ON
If each state is represented by "1" and each OFF state is represented by "0", it is "000" when all switches Sa, Sb, Sc are in OFF state, and "111" when all switches are in ON state. In the meantime 2 ³
= 8 combinations are obtained, so the values of resistors Ra, Rb, Rc are 4:
If 2: 1 is selected, the current flowing through the light emitting diode LD becomes a ratio of 0: 1: 2: 3: 4: 5: 6: 7: as shown in Table 1, and the switches Sa, Sb, Sc Is turned off at “000”, then “000”,
"111" becomes brighter in the order of "001", "010", "011", ...
It becomes the maximum brightness.

In this way, by combining three switches, it is possible to obtain eight gradations from the light-out to the maximum brightness.

In the circuit shown in the first figure, the values of the resistances Ra, Rb, Rc are selected so that the current changes linearly, but other resistance ratios may be used. If a resistor and a switch are added to the portion B indicated by a two-dot chain line on the right side of FIG. 1, the above current ratio will be further increased, and accordingly, the gradation obtained will also be increased. The present invention is based on the operation of the circuit shown in FIG.

FIG. 2 is an electric circuit diagram of an embodiment of the present invention. In this embodiment, 64 LEDs 3 arranged in 8 rows and 8 columns are arranged on the display surface 2 of the display panel 1 which is a display unit, and 8 gradations are provided including a case where all the LEDs 3 are turned off. It is a circuit output for displaying. Shift register 4a as first conversion means
.About.4c, latches 5a to 5c, buffers 6a to 6c, and series resistances Ra to Rc as the second conversion means are the same across the circuit blocks B0, B1, and B2, and the shift register 4a and latches are the same.
The circuit block B0 as a conversion circuit is constituted by 5a, the buffer 6a and the series resistance Ra. Other circuit block B1, B
The same applies to 2.

Each circuit block (generally referred to by reference numeral B) B0, B
The ends of the series resistors Ra, Rb, and Rc of 1, B2 are commonly connected to form the anode lines A0, A1, A2, ..., A7 of the LED3,
Regarding the series resistances Ra, Rb, and Rc, the ratio of the resistance values is Ra; R
b; Rc = 4: 2: 1. It should be noted that in this embodiment, LED3
Display data which is the serial display information of each dot of D0, D1, D2
3 bits (generally indicated by reference numeral D) and individually added to the data input terminals DIa, DIb, DIc of the shift registers 4a, 4b, 4c via the lines 11a, 11b, 11c, respectively. Is. The above display data D0, D1, D2 are all "00
When it is "0", LED3 is turned off and "001", "010", "01"
It becomes brighter in the order of "1", "100", ..., and becomes the maximum brightness at "111". As explained in FIG. 1 and Table 1, this is because the current flowing through LED3 is 0: 1: 2: 3:
Because the ratio is 4: 5: 6: 7 :, the resistance ratio was set to Ra: Rb: Rc = 4: 2: 1 so that the current value changes linearly, but other resistance ratios May be

In this embodiment, further attention should be paid to the right side of FIG.
As shown by the dotted line, a circuit block Bn can be further added. By adding one circuit block B, the display data D is increased by 1 bit, and the number of gradations is 1 for each addition.
The number is 6,32,64, ... In addition, the additional circuit block B may have the same structure as the existing circuit block B, and the number of circuit blocks to be used may be changed according to the gradation, so that a rational circuit structure without waste can be obtained. Similarly, the number of circuit blocks may be reduced when the number of gradations may be small or the gradation is unnecessary.

In the above-described embodiment, the LED 3 has a structure of 8 rows and 8 columns and 64 dots. However, the number of dots is not limited to this, and a matrix structure with another matrix number may be used.
Further, in the present embodiment, although the LED3 is monochrome one color, one dot of the LED3 is a multicolor dot matrix composed of a plurality of LEDs of different colors (for example, red and green, red and yellow, red and yellow and green). It is also possible to realize multi-color, multi-gradation color image display in which each color has a gradation.

Further, although the LED3 is used as the display element in the present embodiment, the light emitting element is not limited to the LED in the present invention, and naturally the display element whose brightness can be changed by the current can also be implemented. Is.

FIG. 3 is an electric circuit diagram of another embodiment of the present invention.
The figure is a perspective view showing its appearance. It should be noted that the circuit block B consisting of the shift register 4, the latch 5, the buffer 6 and the series resistor R for driving the display element is formed on the single printed wiring board, and the connecting connectors CN1, CN2, CN3 are further formed.
(It is indicated by a reference numeral CN when collectively referred to). Multiple connectors CN may be provided for different purposes.
The connection terminals may be integrated in one place to form one connector.

In this embodiment, the display data D is 8 bits D0 to D7,
Also, in the circuit block B, jumper terminals J1 and J2 that allow arbitrary bits to be selected are arranged on the board, and the selection of the display data D input to the circuit block B is performed by the jumper terminals J1 and J2. It can be easily realized by connecting.

Therefore, when a display device is constructed by a plurality of circuit blocks B, the circuit blocks B to be used can all have the same configuration, which improves productivity and uniforms quality. Since all the interconnections of B are made through the connector CN, a compact laminated structure is obtained as shown in FIG. 4 and a display device with a gradation suitable for the purpose can be easily realized.

As described above, according to the present invention, a plurality of types of display information related to the display mode of each display element are serially input for each type, and the serial input information is used for a plurality of bits according to the array mode of the display elements. A plurality of first converting means for converting and outputting the parallel information to the parallel information and a second converting means for converting the parallel output information from the plurality of first converting means into the driving information of each display element. A first element, a second element, a first element and a second element
A plurality of conversion circuits formed by integrally forming the conversion means are connected to each other through the connection terminals.

This makes it possible to easily realize various display modes from non-gradation to multi-gradation corresponding to display contents and purposes. The number of gradations may be set only by increasing or decreasing the number of conversion circuits, and since the same conversion circuit has a laminated structure, a display device having a compact shape can be realized and miniaturization is easy.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining the operation of one embodiment of the present invention, FIG. 2 is an electric circuit diagram of one embodiment of the present invention, and FIG. 3 is an electric circuit diagram of another embodiment of the present invention. FIG. 4 is a perspective view showing its appearance, FIG. 5 is a perspective view showing the appearance of the prior art, FIG. 6 is its electric circuit diagram, FIG. 7 is a time chart, and FIG.
The figure is a circuit diagram showing a specific example of the prior art. 1,21 …… Display unit, 2,22 …… Display surface, 3,23 …… Display element,
4,24 …… Shift register, 5,25 …… Latch, B …… Circuit block, CN …… Connector, J1, J2 …… Jumper connection terminal, R …… Series resistance

Claims (1)

[Claims] 1. A display device having a display section in which a plurality of display elements are arranged, wherein a plurality of types of display information relating to a display mode of each display element are serially input for each type, A plurality of first conversion means for converting input information into parallel information of a plurality of bits according to the arrangement of the display elements and outputting the parallel information, and parallel output information from the plurality of first conversion means respectively converted to drive information of each display element. A plurality of conversion circuits configured to integrally form the first and second conversion means, the display elements being driven by superposing the output from the second conversion means. A display device, which is connected through a connection terminal.