JPH0799495B2 - Floating point arithmetic unit - Google Patents

Description

The present invention relates to a floating point arithmetic unit of a data processing system, and more particularly to not only a floating point number having a fixed boundary between an exponent part and a mantissa part but also an exponent part and a mantissa. The present invention relates to a floating-point arithmetic unit suitable for floating-point arithmetic whose boundaries are not fixed.

[Conventional technology]

In scientific computing, there is a long-felt need for a numerical representation format that can uniformly represent a microscopic world such as elementary particles to a macroscopic world such as the universe. , IPSJ Transactions,
There is a numerical expression format described in Vol.24, No.2, pp.149-156 (1983). This is to express the floating point without fixing the boundary between the exponent part and the mantissa part. In this case,
This numerical representation format is called URR (Universal Real Number Repre
The floating point number is abbreviated as URR number.

In URR, the length of the exponent is determined by the leading "0" sequence or "1" sequence of the exponent. As a result, a value close to 1 can have a short exponent part and a long mantissa part. Therefore, it should be expressed more accurately than the conventional numerical expression format in which the boundary between the exponent part and the mantissa part is fixed (hereinafter called the conventional format). In addition, extremely large numerical values and extremely small numerical values that cannot be expressed in the conventional format can be expressed because the exponent part can be taken long.

As a conventional example, Japanese Examined Patent Publication No. 61-6409 discloses a means for detecting the length of the "0" or "1" sequence in the first half of the exponent part, and the exponent part and the mantissa part are separated or combined by the detection output. By providing a means to perform mutual conversion between the conventional floating point number and the URR type floating point number (URR number),
Although it has been shown that the conventional arithmetic device is used to calculate the URR number, no consideration is given to speeding up the calculation.

[Problems to be solved by the invention]

In the above-mentioned conventional technology, a floating-point number whose boundary between exponent and mantissa is not fixed such as URR number and a floating-point number whose boundary between exponent and mantissa is fixed (floating point in conventional format) are When handled by the same floating-point arithmetic unit, when the operands are set in the input register of the arithmetic unit that handles fixed-point numbers and conventional-type floating-point numbers in common, and when the difference in the numerical representation format is processed after setting, An additional data load is required on the circuit for separating the exponent part and the mantissa part, which causes a problem that the delay due to the wiring length to the arithmetic unit and the number of loads increases.

SUMMARY OF THE INVENTION It is an object of the present invention to be able to execute a URR number operation in a floating point arithmetic unit without degrading the performance of conventional floating point number operations.

[Means for solving problems]

The purpose of the above is to focus on the fact that the configuration of the data transfer path between the floating point register and the input register of the arithmetic unit of the memory is simple as compared with the peripheral of the arithmetic unit, and there is a time margin. In addition to providing a means to separate the exponent part and the mantissa part of the URR number by adding the first detour to the URR
A second exponentiation unit dedicated to the number is provided, and further, the calculation result of the URR number exponent part and the calculation result of the URR number mantissa part are combined.
This is achieved by providing a detour.

[Work]

Conventional floating-point operations are performed without the detour path. For the URR number, the operand read from the floating point register or memory is used for the exponent part after the boundary between the exponent part and the mantissa part is detected in the detour path (first detour circuit), and the bit shift count is determined. After being separated into the desired format by the bit shifter and the mantissa bit shifter and set in the exponent input register dedicated to the URR number and the mantissa input register shared with the conventional format, the exponent is UR
When the processing dedicated to the R number is executed, the mantissa part is calculated almost the same as the conventional format. After the operation result is set in the exponent operation result register dedicated to the URR number and the mantissa operation result register shared with the conventional format, the detour path (second detour)
After shifting by the exponent bit shifter and the mantissa bit shifter so as to satisfy the URR expression format, the combined final result is transferred to the floating point register or memory.

〔Example〕

 An embodiment of the present invention will be described in detail below with reference to the drawings.

2 to 5 show the 64-bit length used in this embodiment.
The URR number and conventional floating point bit structure and contents are shown. For positive numbers in Fig. 2 and for negative numbers in Fig. 3, the URR numbers are classified by the bit format and corresponding binary numbers, and the URR numbers are separated or converted by a combination circuit. The exponent part format and the mantissa format in the calculator are shown below. FIG. 4 shows a non-numeric format that requires special treatment. Arithmetic operations between non-numbers and ordinary numbers or between non-numbers and non-numbers shall follow the above-mentioned journal of the Information Processing Science Society. FIG. 5 shows a conventional floating-point number format.

Regarding the conventional floating point format, I don't think that it is necessary to add any special explanation to Fig. 5, but since URR numbers have been proposed as a new numerical representation format and it is only a few days later, some explanations regarding Figs. 2 to 4 are made. Add. Since the URR number does not depend on the data length as a numerical expression format, a variable length format that allows a required bit length is also possible, but in this embodiment, it is a fixed length of 64 bits.

2 and 3 show the bit numbers in order from the smallest item number to the largest numerical value. In particular, the bit formats not represented in FIGS. 2 and 3 are shown in FIG.
Shown as a number in the figure. The non-number is a concept introduced to eliminate overflow and underflow in arithmetic, and expresses a state of infinity or infinity rather than a number. As an example of using non-numerical values, as shown in Fig. 2, the finite maximum number of 64-bit length is And Multiplication between However, since it cannot be expressed in 64 bits, the positive infinity bit format of Fig. 4 is adopted as a result at this time. Further, since FIG. 3 shows a negative number,
If the absolute value is taken for the number of item No. 1 which is the largest in Fig. 3,
It becomes the smallest in FIG. this Multiplication between Since it cannot be expressed in 64 bits, the positive infinitesimal bit format in Fig. 4 is adopted as a result.

M used in FIGS. 2 and 3 is a natural number and is related to the length of the exponent part. Since it is assumed that the mantissa part of URR numbers is normalized, 1 for positive numbers and -2 for negative numbers are not included in the bit format of URR numbers. . The exponent part of the URR number expresses a double exponent width with a base of 2. Not only does the mantissa part not be specified depending on the bit format exist, but it also corresponds to a width lower than the double exponent width of the higher order. There are some parts that are cut off or do not exist. The individual bit formats will be described in more detail below.

First, description will be made from FIG. The first bit is a sign bit S, which is 0 for all bit formats of item number 1 to item number 9 and indicates a positive number. Sign bit S
Following is the exponent part E, and the maximum width of the double exponent is m−1, where M + 1 is the number of consecutive 1s from the second bit of item number 1 to item number 4. 1 in succession
The m-1 bit string following the break 0 of the bit string of
It represents a double exponent width of m-2 or less. In item number 1, this portion does not exist, and in item number 2, this portion is cut off in the middle without all m-1 being aligned. Following the exponent part E is the mantissa part F, and in the item numbers 1 to 3, there is no mantissa part explicitly specified as a bit format. The values of the exponent part of item number 5 and item number 6 are 1,2 ^-1 , respectively, and the 4th to 64th 61-bit strings are the mantissa part with the 3rd bit as the last bit of the exponent part. If the number of 0s consecutive from the second bit of item number 7 to item number 9 is m + 1, the maximum width of the double exponent is m, but at this time, the exponent of 2 has a negative value. M following a 1 at a break in a sequence of consecutive 0 bits
The −1 bit string represents a double exponent width of m−2 or less, and is positive as an exponent of 2. In the item number 9, all of the m−1 bits are cut off in the middle. Also, item number 8
No. 9 has no mantissa specified as a bit format.

Finally, FIG. 3 will be explained as an explanation of the 64-bit length URR number itself. The first bit is the sign bit S, which is 1 for all bit formats from item number 1 to item number 9,
Indicates a negative number. Following the sign bit S is an exponent part E, and if the number of 1's consecutive from the second bit of item number 1 to item number 4 is m + 1, the maximum width of the double exponent is m, and The index takes a negative value. The m-1 bit strings following the breaks in the continuous 1 bit string have a double exponent width of m-2 or less, are represented by 1's complement, and are positive as an exponent of 2. In item number 1, this part does not exist, and in item number 2, this part is cut off in the middle without all m-1 pieces, but when converting to a binary number, each bit is 0 for bits that do not fit in 64 bits. Each bit becomes 1 by taking 1's complement,
Be subject to conversion. Further, in the item numbers 1 to 3, there is no mantissa part which is specified as a bit format. No. 5,
The value of the exponent part of item number 6 is 2 ^-1 , 1, respectively, and the 3rd bit is the last bit of the exponent part and the 4th to 64th
The 61-bit string becomes the mantissa part. If the number of consecutive 0s from the second bit of item number 7 to item number 9 is m + 1, the maximum width of the double exponent is m-1. 0 in succession
M-1 bit string following the 1 of the break of the bit string of
It has a double exponent width of -2 or less and is represented by a one's complement. In item number 9, this part is cut off in the middle without all m-1 pieces being prepared, but when converting to a binary number, the part that does not fit in 64 bits is regarded as each bit 0 and the complement of 1 is taken. As a result, each bit becomes 1 and becomes a conversion target. As mantissa which is not specified as bit form negative URR number has -2-point bit sequence of item No. 4, to Koban 7 mantissa two ^one's place as a binary number higher than point as a sign bit as 10. The following additions yield a binary number in two's complement notation.

Regarding the bit length of the exponent part, depending on how continuous the value of the second bit is, when it is cut at the third, the length of the exponent part is the value of the second and third bits and the value of the second bit. It is the same as, and the length of the exponent is 2m + 1 when m + 1 consecutive bits including the second bit are easily understood from the above description with reference to FIGS. 2 and 3. .

An embodiment of the floating point arithmetic unit of the present invention is shown in FIG. In FIG. 1, 1 is a control circuit for controlling the entire floating point arithmetic unit, 2 is a floating point register,
There are 16 64-bit length registers. The control circuit 1 detects whether the arithmetic instruction targets a conventional floating point number or a URR number, and controls the selection in the data transfer path and the update of various registers. Note that the exponent part and the mantissa part of the URR number can be separated or combined by using an adder and a multiplier / divider having the same configuration or sharing them. Therefore, in order to simplify the description, FIG. Now, let's take only the adder and omit the multiplier and divider.

First, the adding operation for the conventional floating point will be described. The first to eighth 8 bits of the first operand (OP1) and the second operand (OP2) of 64-bit length read from the floating point register 2 or the memory are the exponent OP1 register 6 and the exponent OP2 register 7, respectively. When set to, the first and second operands 9 through 9
The 64th 56 bits are set in the mantissa part OP1 register 8 and the mantissa part OP2 register 9, respectively, in a 63-bit length format with two leading zeros and five trailing zeros added. The difference between the exponents is calculated by the subtractor 11 using the second to eighth bits of the exponent register 6, 7 as an operand, and the mantissa having a large exponent is added by the T / C circuit (true-complement logic circuit) 12. In this case, if the two operands have the same sign, the complement is taken if they have different signs, and the mantissa with a small exponent is right-shifted by the exponent difference by the preshifter 13 to obtain the mantissa adder 14 respectively. Send to. The sum of the mantissas is complemented as necessary and made into an absolute value.

The mantissa of the final result is, except when the whole mantissa is zero,
When it is ensured that the uppermost 4 bits are not zero, the shift number is obtained by the zero check circuit 15 and left shifted by the post shifter 18.
By 17, the mantissa is left-shifted and subtracted from the larger exponent. Further, when the mantissa addition result overflows, this is also detected by the zero check circuit 15, and when the post-shifter 18 shifts it to the right by 4 bits, the exponent updating calculator 17 is set to 1 for the larger exponent. Add. Finally exponent calculator result register including sign 20
8 bits and the mantissa part operation result register 21 are stored in the floating point register 2 or the memory as the final operation result.

It should be noted that the floating-point number of the conventional format in this embodiment is a hexadecimal number as shown in FIG. 5, so that a unit to shift or zero is detected. The unit to do is to perform 4 bits as one set.

Next, the adding operation of the URR number will be described. The 64-bit first operant and the second operand read from the floating-point register 2 or the memory have their exponent part and mantissa separated by the URR exponent part / mantissa separation circuit 3, and the exponent part with a 62-bit length is When the exponent part OP1 register 4 for URR number and the exponent part OP2 register 5 for URR number are set, the mantissa part of 63-bit length is set in the mantissa part OP1 register 8 and the mantissa part OP2 register 9.

FIG. 6 shows the details of the URR number exponent part mantissa separation circuit 3.
The exponent part mantissa boundary detection circuit 31 determines the mantissa part according to the value of the value of the next 1st code bit, the value of the 2nd bit (the beginning of the exponent part) and the value of the 2nd bit. For 01, 10, 00, 00 (if it is a non-numeric value) is selected as the number of bit shifts and the most significant 2 bits, for the exponent part, the bit shift number, the sign as the exponent part, and Determines whether one's complement is taken for the width below the maximum width of the double exponent. Next, the exponent bit shifter 32 and the mantissa bit shifter 33
Thus, the URR numbers shown in FIGS. 2 and 3 are shifted so that the exponent part and the mantissa part after separation are associated with each other. The exponent-mantissa-boundary detection circuit 31 detects the information for separating the exponent part and the mantissa part, and also detects six types of non-numerical values shown in FIG. 4 and transmits them to the control circuit 1. The control circuit 1 controls a non-numerical operation so as to obtain an operation result according to the above-mentioned journal.

Regarding the separation of the exponent part and the mantissa part of the URR number, an example of a concrete numerical value is shown below with respect to the number 1986 as follows.

Returning to FIG. 1, the contents of the URR number exponent OP1 register 4 and the URR number exponent OP2 register 5 are input and the URR number subtracter 10 is input.
The difference between the exponents is calculated by using the mantissas of the mantissa part OP1 register 8 and the mantissa part OP2 register 9, the mantissa having a large exponent passes through the T / C circuit 12 without taking a complement, and the mantissa having a small exponent is The preshifter 13 shifts it to the right by the difference of the exponents, and sends it to the mantissa adder 14, respectively. The difference from the conventional floating point is that the mantissa part of the separation of the URR number is in the complement notation, and it is not necessary to take the complement in the T / C circuit 12. The preshifter 13 is not in units of 4 bits but in units of 1 bit. The high-order bit that operates and has a vacancy due to the shift is to perform algebraic shift for embedding a code. In the case of subtraction, after the mantissa having a large exponent is complemented by the T / C circuit 12, the complement is taken by the T / C circuit 12 if the mantissa part of the first operand is mantissa. The adder 14 recomplements the mantissa sum. The output of the mantissa adder 14 is controlled by the zero check circuit 15 so that the shift result by the post shifter 18 satisfies the form of the mantissa part after separation in FIG. 2 or FIG. 3 (referred to as normalization of mantissa part of URR number). When the shift number is calculated and the result obtained by correcting the large exponent in the URR number exponent part update arithmetic unit 16 by the shift number is set in the URR number exponent part operation result register 19, The mantissa part of the normalized URR is set in the mantissa part operation result register 21. After that, the URR number exponent part mantissa combining circuit 22
Is converted so as to satisfy the numerical expression format of URR and stored in the floating point register 2 or the memory.

FIG. 7 shows details of the URR number exponent part and mantissa part coupling circuit 22.
In FIG. 7, after the bit shift number is calculated by the exponent part bit length determination circuit 221, the exponent part bit shifter 222,
The bits are shifted by the mantissa bit shifter 223, and further combined by the exponent mantissa merge circuit 224. Although FIG. 7 shows a configuration in which 222 to 224 are divided,
A circuit configuration in which these three circuits are integrated without being divided is also possible.

〔The invention's effect〕

According to the present invention, it is possible to directly execute a calculation of a URR number, which is a new numerical expression format, by a floating-point calculation device without deteriorating the performance of the conventional calculation of floating-point numbers.

[Brief description of drawings]

FIG. 1 is a block diagram of a floating point arithmetic unit according to an embodiment of the present invention, and FIGS. 2 and 3 are classifications of URR numbers in bit format and corresponding binary numbers, and URR numbers are separated and converted by a combining circuit. Or a figure showing the exponent part format and mantissa part format inside the arithmetic unit to be inversely converted, FIG. 4 is a figure showing the non-numeric value in the URR number, and FIG. 5 is the numerical format of the conventional floating point number 6 and 6 are detailed diagrams of the URR number exponent part mantissa part separation circuit of FIG. 1, and FIG. 7 is a detailed diagram of the URR number exponent part mantissa part combination circuit of FIG. 3 ... URR number exponent part mantissa separation circuit, 4 ... URR number exponent part OP1 register, 5 ... URR number exponent part OP2 register, 10 ... URR number subtractor, 16 ... URR number exponent Update calculator, 19 ... Exponent part operation result register for URR number, 22 ... URR number exponent part mantissa coupling circuit.

Claims (1)

[Claims] 1. A first exponent and a second exponent in which an exponent part and a mantissa part of each operand of a floating-point number having a fixed boundary between an exponent part and a mantissa part to be operated from a floating-point register group or memory are set. Part input register, first and second mantissa part input registers, exponent operation part for performing exponential part operation of the first and second exponent part input registers, and mantissa part operation of the first and second mantissa part input registers An exponent part to be operated in a floating-point arithmetic device including a mantissa operation part for performing the operation, an exponent part operation result register for setting the exponent part operation result, and a mantissa part operation result register for setting the mantissa part operation result. First and second URR number exponent part input registers in which exponent parts of respective operands of floating-point numbers (hereinafter abbreviated as URR numbers) in which the boundary between and the mantissa part are not fixed are set; Registers or memory and the first and second exponent part input register, provided in the data transfer path parallel between said first and second mantissa input register, from the floating point register group or memory,
Exponent part (hereinafter referred to as URR number exponent part) and mantissa part (hereinafter referred to as URR number mantissa part) of each operand of the URR number to be operated
And the URR number exponent part of each separated operand is transmitted to the first and second URR number exponent part input registers, and the URR mantissa part of each operand is transmitted to the first and second mantissa input registers. A first detour, an URR number exponent operation unit for performing an URR number exponent operation of the first and second URR number exponent input registers, a URR number exponent operation result, and the first and second mantissa input registers A floating point decimal point arithmetic unit comprising: a second detour that connects the URR number mantissa part calculation result in the mantissa calculation unit when the URR number mantissa part is set.