JPH0799518B2 - Data processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device using a microcomputer.

2. Description of the Related Art In recent years, efforts have been made to improve the functions and performances of various electronic devices, and high functions are also required for data processing devices using microcomputers that are involved in drive control of these electronic devices.

For example, in a data processing device involved in drive control of an electronic device such as a video tape recorder, processing is performed including data for driving a numeric display for channel display, time display and the like. FIG. 4 is a diagram showing the configuration of the numerical display device, which has four display digits 2, 3, 4, and 5, and each display digit 2 to 5 is composed of _seven segments S _{1 to} S ₇ . Has been done. Each segment S _{1 to} S ₇ is composed of a fluorescent display tube, a liquid crystal, etc., and the numbers “0” to “9” are displayed by selectively applying a drive voltage to these segments S _{1 to} S _7. To do.

FIG. 2 shows a conventional data processing device formed by using a one-chip microcomputer for directly driving such a display.

In FIG. 2, 6 is a one-chip microcomputer, 7 is a central processing unit (hereinafter referred to as CPU), and 8 is a CPU.
ROM storing the execution instructions of 7, 9 is a general-purpose RAM for reading and writing the data necessary for the CPU 7 to execute various instructions according to the commands from ROM 8, and 10 stores the segment data for driving the display 1. The display-only RAM 11 is a display control unit that drives the display 1, which is a driven body, according to the segment data from the display-only RAM 10.

FIG. 3 shows the display-only RAM 10 and display controller 11 of FIG.
FIG. 5 shows a more specific configuration of the periphery, where 12 is a display clock generator that generates a display clock that is a driving original signal, and 13 is a display clock that counts the display clock and is shown in FIGS. ,
Digit clock corresponding to each display digit 2, 3, 4, 5 as shown in d, that is, a digit counter that generates a drive signal, 14 is a display-only RA
A latch for temporarily holding the segment data from M10, that is, drive data, 15 is a digit driver, 16 is a segment driver, 17 is a data bus, and 18 is an address bus.
These buses 17 and 18 are connected to the CPU 7.

In the above structure, the writing of the display segment data is performed as follows. First, display RAM1 from CPU7
For 0, the addresses A _{0 to} A ₃ corresponding to the display digits are specified, and then the segment data of each display digit (for example, “011010 at address A ₀
0 ") is transferred and each of these segment data is written to the corresponding address of the display-only RAM 10.

On the other hand, reading of the display segment data is performed as follows. The clock from the display clock generator 12 is counted by the digit counter 13, and the digit counter 13 generates a digit clock as shown in FIGS. This digit clock is added as an address signal to the display-only RAM 10 to access the display-only RAM 10. As a result, the segment data stored in each address A _{0 to} A ₃ of the display-only RAM 10 is sequentially read out and held in the latch 14.

The segment data held in the latch 14 is applied to the segment driver 16 and is applied to the display 1 in synchronization with the digit clock applied from the digit counter 13 to the digit driver 15. That is, the voltage from the segment driver 16 is selectively applied to each segment of the display digit driven by the output of the digit driver 15, and a predetermined number is displayed on each display digit.

Problems to be Solved by the Invention Along with the higher functionality and higher performance of many electronic devices such as a video tape recorder, a microcomputer for controlling them is also required to have a higher function. The higher the function of the microcomputer, the larger the size of the ROM for storing the program, the size of the RAM for storing the data, and the size of the microcomputer itself.

Under such circumstances, in the case where the dedicated RAM 10 needs to be provided separately from the general-purpose RAM like the conventional data processing device, the increase in the chip size cannot be avoided, which is extremely inconvenient. Moreover, as is apparent from the above description of the embodiment, since the display-only RAM 10 is accessed by both the CPU 7 and the display controller 11, it is necessary to configure it as a so-called dual port RAM having two lines of address lines. Therefore, the chip area is increased more than the addition of the usual single port RAM. Further, since the display-only RAM 10 has a dual port configuration, this function cannot be simply applied to the general-purpose RAM 9 having a single port configuration.

The present invention provides a display driving device that solves the above conventional problems.

Means for Solving Problems The present invention stores drive data of a driven body at a predetermined address of a general-purpose RAM of a microcomputer, and generates a DMA (Direct Memory Access) request signal when the driven body is driven. The general-purpose RAM is disconnected from the control of the CPU, and the segment data stored in the general-purpose RAM is read by accessing the general-purpose RAM by using the drive signal from the signal generation circuit as an address signal, and this segment data is driven by the driven body. It is transferred to the control unit.

Operation In this way, the DMA request signal is used as a kind of interrupt request signal, and if the general-purpose RAM is removed from the control of the CPU when the driven object is driven, the drive signal output from the signal generation circuit
The general-purpose RAM can be accessed as an address signal instead of the address signal from the CPU. Therefore, it becomes possible to store the drive data of the driven body in a part of the single-port general-purpose RAM, and to access the drive data at the time of driving to read the drive data. As a result, dedicated RAM becomes unnecessary,
The chip size of the microcomputer can be reduced.

Embodiment An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a general view of a display driving device according to an embodiment of the present invention.
It is a figure which shows the RAM and the periphery of a display control part.

In FIG. 1, the same parts as those in the conventional example shown in FIGS. 2 and 3 are designated by the same reference numerals and the description thereof will be omitted. A DMA request signal generator 19 in the microcomputer 6 and a micro instruction memory circuit (hereinafter referred to as μROM) 2 which decodes the request signal and gives a read instruction to the general-purpose RAM 9.
One is provided. The segment data for display is written in predetermined addresses A _{0 to} A ₃ in the general-purpose RAM 9 instead of the conventional display-only RAM.

In the above configuration, writing the segment data is done by CP
CPU from U to address specified via address bus 18
Is performed by writing the segment data transferred from the data bus 17 to the data bus 17. The remaining addresses of the general-purpose RAM 9 store various data used during execution of normal instructions other than driving the display.

When driving the display unit, the DMA request signal is generated from the DMA request signal generation unit 19 in the display unit control unit as a kind of interrupt request signal by the CPU.
Input to μROM20 in 7. The function of the DMA request signal as a kind of interrupt signal will be described with reference to FIG. FIG. 6 shows the instructions that the μROM 20 sequentially decodes. Normally, the instruction 1, the instruction 2, and the instruction 3 are decoded in order based on the program stored in advance in the μROM 20, and the CPU 7 executes the instruction contents. However, as shown in FIG.
A DMA request signal is generated from the A request signal generator 19, and the μROM 20
When input to, the μROM 20 decodes this signal. μROM20
, The .mu.ROM 20 executes the instruction 2 which is the instruction immediately before the DMA request signal is generated, and then generates a signal for starting the DMA transfer. That is, when the DMA request signal is generated, the μROM 20 interrupts the decoding and execution of the instruction to be executed by the CPU 7, and starts the process for DMA transfer. After the DMA transfer is completed, the instruction (instruction 3) is decoded and executed again. The DMA request signal generator 1
9 is C based on the timing when display 1 needs to be driven.
The DMA request signal is generated at a constant cycle independently of the operation of PU7. In this way, the μROM20 that is normally used to decode the instructions of the CPU7 is used to decode the DMA request signal and
A Transfer.

Next, the operation of DMA transfer will be described with reference to FIG. D
When the MA request signal generator 19 generates a DMA request signal, it is input to the μROM 20 via the signal line A. As a result of decoding the signal input by the μROM 20, when it is judged as a DMA request signal, a signal of a read command is sent to the general-purpose RAM 9 via the signal line B, and at the same time, the general-purpose RAM 9 is disconnected from the control of the CPU 7. At the same time, the μROM 20 sends a display clock control signal (driving original signal) to the display clock generator 12 via the signal line C. The display clock generator 12 generates a clock when receiving a signal. The digit counter 13 receives this clock through the signal line D and counts it. The digit clock obtained as a result of counting by the digit counter 13 is output to the address bus 18 via the signal line E as an address signal. That is, the display clock generator 12 and the digit counter 13 function as a signal generation circuit that generates an address signal. Address signal is address bus 18
From the general-purpose RAM9 through the signal line F from
The specified addresses A _{0 to} A ₃ are designated. Since the read command is sent to the general-purpose RAM 9 via the signal line B as described above, the addresses A _{0 to} A ₃ designated by the read command are sent.
The segment data stored in is sequentially read out via the signal line G and the data bus 17. The read segment data is sequentially held in the latch 14 in synchronization with the read command from the μROM 20. The segment data held in the latch 14 is applied to the segment driver 16 and is applied to the display 1 in synchronization with the digit clock applied from the digit counter 13 to the digit driver 15. Ie digit driver
The voltage from the segment driver 16 is selectively applied to each segment of the display digit driven by the output of 15, and a predetermined number is displayed on each display digit. As described above, the digit driver 15 and the segment driver 16 in FIG. 1 function as a driven body control unit for driving the display 1 which is a driven body.

FIG. 7 is a timing chart showing the operation of the data processing device of FIG. 1 described above. As shown in the figure, when the DMA request signal (a) is generated, the display clock control signal (b) and the read command signal (e) are simultaneously generated from the μROM 20 in response to this signal. When the display clock generator 12 receives the display clock control signal (b) and generates the clock, the digit counter 13 which receives the clock generates the address signal (c). When the address signal (c) and the read command signal (e) are input to the general-purpose RAM 9, the data signal (d) is sequentially read. In this way, the drive data stored in the general-purpose RAM 9 can be read and displayed. Although one example is shown above, the data processing apparatus of the present invention can be widely applied not only to data processing for a display but also to processing of drive data of other driven bodies.

Note that when such a DMA method is used, normal instruction execution is temporarily suspended, but in practice
It only interrupts for about 2 μS and the execution speed only decreases by about 1%. Therefore, there is almost no problem in programming.

According to the present invention, the driving data of the driven body is stored at a predetermined address of the general-purpose RAM of the microcomputer, and a DMA request signal is generated when the driven body is driven, and the general-purpose RAM is stored in the CPU.
The drive data in the general-purpose RAM is read by accessing the above-mentioned general-purpose RAM by using the digit clock from the digit counter as an address signal, and the data is transferred to the driven body control unit to drive the driven body. Since it is designed to be driven, in addition to general-purpose RAM, dedicated RAM
Need not be provided, so that the chip size of the microcomputer can be reduced. Moreover, general-purpose RA
Since various driven bodies can be driven simply by enlarging or reducing the area for M drive data, the versatility of the data processing apparatus is enhanced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of a data processing device of the present invention, FIG. 2 is a block diagram of a conventional data processing device, and FIG.
FIG. 4 is a block diagram showing the main part of FIG. 2, FIG. 4 is a front view of a display which is a driving target of the present invention and a conventional example, and FIG.
FIG. 6 is a conceptual diagram showing the instructions decoded by the .mu.ROM 20 in the embodiment of the present invention, and FIG. 7 is a timing chart showing the operation in the embodiment. 1 ... Display unit, 2-5 ... Display digit, 6 ... Microcomputer, 7 ... Central processing unit (CPU), 8 ... RO
M, 9 ... General-purpose RAM, 12 ... Display clock generator, 13 ...
… Digit counter, 14 …… Latch, 15 …… Digit driver, 16…
… Segment driver, 17 …… Data bus, 18 …… Address bus, 19 …… DMA request signal generator, 20 …… Micro instruction memory circuit (μROM).

Claims (1)

[Claims] 1. A central processing unit, a ROM for storing and decoding execution instructions of the central processing unit, a driven body control unit for driving a driven body, and control of the central processing unit. When data is read and written by the general-purpose RAM and the drive original signal from the ROM is input, the general-purpose RAM in which the drive data of the driven body is stored at a predetermined plurality of addresses, and among the predetermined plurality of addresses are input. A signal generation circuit for generating an address signal for designating one of them and a DMA request signal generation unit for generating a DMA request signal to the ROM are provided, and when the DMA request signal is generated, the ROM makes the DMA
Control of the central processing unit by decoding the request signal, outputting a data read command to the general-purpose RAM, and specifying the address by outputting the driving original signal to the signal generating circuit. A data processing device, characterized in that the drive data stored in the general-purpose RAM is read out and transferred to the driven body control unit in a state of being separated from the bottom.