JPH0799622B2 - Semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory device in which a volatile semiconductor memory device and a non-volatile semiconductor memory device are combined.

(Prior Art) Generally, a storage device (hereinafter referred to as “memory”) that retains stored contents even when the power is turned off is called a non-volatile memory. Called volatile memory. These memories can be composed of semiconductors, and among the electrically rewritable ones, there are nonvolatile memories such as EEPROMs.
There is also RAM, which is a volatile memory.

(Problems to be solved by the invention) The EEPROM can retain stored data for a long time even when the power is turned off, but there is a limit to the number of times data can be rewritten, and each rewriting operation takes a few _msec . It is not suitable for applications where data is constantly rewritten.

On the other hand, RAM requires 100n to rewrite data.
_It is as short as _sec, and there is no limit to the number of rewrites, but stored data is lost when the power is turned off.

(Means for Solving the Problems) In the present invention, in order to solve the above-mentioned problems, a volatile semiconductor memory and a non-volatile semiconductor memory are combined, and the non-volatile semiconductor memory is stored depending on the necessity of holding the stored contents. The operation means can be switched and a transfer means for transferring the stored data of the volatile semiconductor memory to the nonvolatile semiconductor memory is provided.

When it is not necessary to long term storage (action) data, operates as a volatile semiconductor memory, it can rewrite data at about 100n _sec. On the other hand, when it is necessary to store data for a long period of time, the mode is switched to operate as a non-volatile semiconductor memory, and a voltage is applied to transfer the data stored in the volatile semiconductor memory to the non-volatile semiconductor memory. By doing so, data can be transferred for a period of several _msec regardless of the amount of data, and the data can be stored for a long time.

(Embodiment) FIG. 1 shows a circuit diagram of an embodiment in which an EEPROM is used as a nonvolatile semiconductor memory and a DRAM is used as an example of a volatile semiconductor memory. Since both EEPROM and DRAM are manufactured by MOS technology, they are easy to manufacture, and DRAM has an advantage that the number of elements required for one memory cell is the smallest.

In FIG. 1, three MOS transistors MT ₁ , MT ₂ , and MT ₃ are formed in series on a semiconductor substrate. In actual memory, many combinations are arranged,
For convenience, the portion that operates as one unit has been taken out. MOS
A capacitive element C is connected to an intermediate point 4 between the transistor MT ₁ and the MOS transistor MT ₂ , and a predetermined voltage is applied from a terminal 5. The terminal 1 of the MOS transistor MT ₁ is usually the n layer of the semiconductor substrate and is connected to the column line of the memory, and the terminal 3 of its gate G ₁ is connected to the row line of the memory. The MOS transistor MT ₂ constitutes an EEPROM by providing a floating gate 6 below the normal control gate G ₂ . The MOS transistor MT ₃ can either operate as an EEPROM or a DRA
A voltage is applied from the terminal 7 to the gate G ₃ of the mode switching transistor, which operates as M, or its control gate G ₂ of the MOS transistor MT ₂ . The terminal 2 of the MOS transistor MT ₃ becomes the n layer of the semiconductor substrate. One of the terminals 1 and 2 is on the drain side and the other is on the source side. In the capacitor C, the source or drain region of the semiconductor substrate can be used as one electrode, and the polysilicon provided through the oxide film can be used as the other electrode.

Such a device operates as follows.

(1) Initialization Before starting the operation, a positive voltage is applied to the terminal 7 to accumulate electric charge in the floating gate 6 of the MOS transistor MT ₂ (the electric charge at this time is designated as Q _F ).

(2) During DRAM operation When operating as a normal DRAM, use pins 5 and 7
Is grounded and the MOS transistor MT ₃ is turned off. The equivalent circuit in this state is as shown in FIG. 2 and constitutes a DRAM including one capacitive element and one MOS transistor. The voltage V is applied to the terminal ₁ of the drain of the MOS transistor MT _1.
When this transistor is turned on with _CC applied, the charge accumulated in the capacitive element C (capacitance is CC)
Q _C becomes Q _C = C _C V _CC .

(3) Data transfer from DRAM to EEPROM The equivalent circuit for transferring the data stored in the DRAM described above to the EEPROM is
Shown in the figure.

When the voltage V ₅ is applied to the terminal 5 with the charge Q _C stored in the capacitive element C and the charge Q _F stored in the floating gate 6, C _L (V _F −V ₄ ) + C _H V _F = Q _F … (1) C _C (V ₄ −V ₅ ) + C _L (V ₄ −V _F ) = Q _C … (2) Where, C _C : Capacitance of the capacitor C C _L : Between the floating gate 6 and the substrate Capacitance C _H : Capacitance between floating gate 6 and control gate G ₂ V ₄ : Potential of terminal 4 V ₅ : Voltage of terminal 5 V _F : Potential of floating gate 6 Q _C : Charge accumulated in capacitive element C Q _F Charge accumulated in the floating gate 6 From the equations (1) and (2), the voltage V applied between the floating gate 6 and the diffusion layer constituting one electrode of the capacitor is Represented.

By the way, in the above initial setting, the electric charge of Q _F = −C _H · ΔV _TH (4) is accumulated.

ΔV _TH : Shift value of the threshold value of the MOS transistor MT ₂ due to the charge accumulated in the floating gate 6 by default, and by applying V _CC to the capacitive element C, Q _C = C _C V _CC (5 ) Charge is accumulated.

From equations (3), (4), and (5) The current density J _F injected into the floating gate 6 is determined by the electric field E _OX applied between the floating gate 6 and the diffusion region of the semiconductor substrate, and J _F = AE _OX ² exp (−B / E _OX ) ... (7 ). A and B are constants.

It is represented by. Here, _tox is the thickness of the thin oxide film between the floating gate 6 and the diffusion region.

E _OX of the state in which the charge Q _C = C _C V _CC is accumulated and the state in which the charge C _C V _CC is not accumulated (Q _C = 0) are respectively E
_{If OX1} and E _OX0 , It is represented by.

FIG. 4 shows capacitive elements C and MO of the equivalent circuit shown in FIG.
FIG. 9 is a schematic cross-sectional view of an actual element of a part of the S transistor MT ₂ . When holes are injected into the floating gate 6 by applying the voltage V ₅ to the terminal 5 of the electrode 8 of the capacitor C, and when the charge Q _C = C _C V _CC is accumulated in the capacitor C, ΔE shown in Eq. (9) is better than that in the non-accumulated state
Holes will be injected by a strong electric field only for _OX . Fourth
In the figure, an oxide film is provided on the surface of the semiconductor substrate 9, and the control gate G ₂ , the floating gate 6, the electrode 8 and the like are covered with the oxide film. An n-type diffusion layer 10, for example, is provided on the surface of the semiconductor substrate 9 below the floating gate 6 and below the electrode 8. The n-type semiconductor layer 10 is the second
It becomes the drain or the source of the MOS transistor MT ₂ .
The control gate G ₂ and the floating gate 6 are made to face the channel region of the _second MOS transistor MT ₂ with the oxide film interposed therebetween. The control gate G ₂ is integrated with the gate G _{3 of} the third MOS transistor MT _{3 and} the _third gate transistor G ₃ is provided with an oxide film.
Will face the channel region of the MOS transistor MT ₃ .

When the thickness of the thin oxide film for the hole injection between the floating gate 6 and the diffusion layer 10 and t _OX, t _OX in Example _{= 80Å C C = 50fF C H} = 15.8fF C L = 9.2fF V _CC = 5V.

At this time, when each numerical value is put into the equation (9) and ΔE _OX is calculated, ΔE _OX = 3.54 (MV / cm), and the electric field applied between the floating gate 6 and the diffusion layer 10 is E _OX1 And E _OX0 , if the current densities flowing through the floating gate 6 are J _F1 and J _F0 , then J _F1 / J _{F0 ≈10} ^7, and the electric charge is accumulated in the capacitive element C (Q _C =
In the C _C V _CC ) state, no charge is accumulated (Q _C = 0)
It can be seen that a large amount of positive charges are accumulated in the floating gate 6 as compared with the state.

In this embodiment, the control gate G ₂ of the MOS transistor MT ₂ is grounded and the voltage V ₅ is applied to one electrode of the capacitive element C.
The same thing can be done by grounding one electrode of the capacitive element C and applying a voltage to the terminal 7.

As described above, the data stored in the capacitive element C can be transferred as the data stored in the floating gate 6 by applying a voltage to the terminal 5 or the terminal 7. Even if a large number of storage elements with the above-mentioned configuration are connected, by applying a voltage to the common terminal 5 or 7, all the large-capacity data accumulated as DRAM is transferred at once to the EEPROM at a high speed. can do. The data in the EEPROM is discriminated by the magnitude of the channel current of the MOS transistor MT ₂ or the change in the gate threshold voltage seen from the control gate G ₂ .

(Effects of the Invention) According to the present invention, a volatile semiconductor memory device and a non-volatile semiconductor memory device can be combined to rewrite or save the memory as necessary. Non-volatile RA combining DRAM and EEPROM
M is suitable for high integration.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is an equivalent circuit when operating as a DRAM, FIG. 3 is an equivalent circuit when transferring data from DRAM to EEPROM, and FIG. 2 is a schematic sectional view of an essential part of an IC that has been subjected to FIG. MT ₁ , MT ₂ , MT ₃ ... MOS transistors G ₁ , G ₃ ... Gate G ₂ ... Control gate C ... Capacitance element, 6 ... Floating gate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G11C 17/00 307C

Claims (2)

[Claims] 1. A volatile semiconductor memory device, comprising: a first MOS transistor having a gate and one of voltage applying means at one of a drain and a source; and a gate voltage applying means constituting a nonvolatile semiconductor memory device. And a third MOS transistor having a floating gate and acting as an EEPROM, and a second MOS transistor having a voltage applying means at the other terminal of the drain or the source for mode switching.
Transistor is connected in series, the voltage applying means of the control gate of the second MOS transistor and the gate of the third MOS transistor are commonly connected, and the other end of the capacitive element having the voltage applying means at one end is First
A semiconductor memory device characterized by being connected between a MOS transistor and a second MOS transistor. 2. At least a capacitive element and second and third MOs
The S-transistor is formed on the same semiconductor substrate, and the upper electrode of the capacitive element forms the drain or source region of the second MOS transistor on the surface of the semiconductor substrate forming the lower electrode of the capacitive element via the insulating film. The floating gate of the second MOS transistor faces the channel region of the second MOS transistor through the insulating film, and the control gate of the second MOS transistor faces the insulating film. Is placed above the floating gate of the second MOS transistor via
2. The semiconductor memory device according to claim 1, wherein the control gate of the MOS transistor and the gate of the third MOS transistor are integrally formed.