JPH079974B2 - Manufacturing method of complementary semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a complementary semiconductor device which is densely formed on a Si substrate.

(Prior Art) Complementary semiconductor elements having features such as low power consumption and a wide operating margin will become more important in the future in terms of higher density and higher performance of semiconductor devices. The complementary semiconductor element is a semiconductor device obtained by forming an n-channel MOS transistor in a p-type region and a p-channel MOS transistor in an n-type region on a single crystal Si substrate, and combining the both transistors. As a factor that limits the densification of CMOS devices, the first is to form a well near the surface of the substrate, which is a region of low conductivity and of a conductivity type different from that of the substrate. This is because the element isolation region needs to have a margin because it extends not only in the direction but also in the lateral direction. Secondly, the p-channel MOS transistor and the n-channel MOS transistor are designed to be separated from each other more than necessary in order to prevent the latch-up caused by the operation of the parasitic thyristor. Various device isolation methods have been proposed to overcome these restrictions. For example, Yamaguchi et al.
In the paper published on pages 184 to 193 of Volume 2, as shown in FIG.
This is a separation method in which a groove having a depth of 6 μm is formed by m, the surface of the groove is oxidized, then filled with polycrystalline silicon, and flattened by etching back. Then, phosphorus is ion-implanted into the region to be n-type and diffused to an appropriate depth to form an n-well.
Form 23. The CMOS device is formed after forming the field oxide film. This method has a small element isolation width because there is no lateral diffusion of wells, and because it uses an epi-wafer, it has CM with latch-up resistance.
OS devices can be obtained, and high-density elements are expected.

(Problems to be Solved by the Invention) In order to form an element isolation region used in the complementary semiconductor device shown in FIG. 2, it is necessary to form a groove in a silicon substrate and bury it flat with an insulating film or the like. To do. In order to further reduce the element isolation width here, special lithography technology with high resolution and advanced film deposition technology for filling and flattening fine grooves are required, so long as the current process technology is used.
It was difficult to realize a separation width of 0.5 μm or less.
An object of the present invention is to provide a method for manufacturing a high-density complementary semiconductor device which is capable of easily forming fine and flat separations without being limited by the resolution of the lithography technique.

(Means for Solving the Problems) In the present invention, a groove whose side surface is perpendicular to the substrate surface is formed on a single crystal silicon substrate, and an insulating film is formed only on a side surface portion of the groove. Selectively, and by epitaxially growing silicon so as to be substantially flush with the surface of the single crystal silicon substrate, an insulated gate field effect transistor is formed on the single crystal silicon substrate, which is different from that on the epitaxial growth layer. In a manufacturing method for forming a conductive insulated gate field effect transistor, a step of forming a deep p-type layer by an ion implantation method in a region shallower than a depth of a device isolation region of a device region where an n-channel field effect transistor is formed, And the step of forming the n-type layer having a high impurity concentration on the bottom surface of the groove after the groove is formed and then performing the epitaxial process. The problem of the technique was solved. That is, the gist of the present invention is to realize a fine separation width between the n-channel transistor and the p-channel transistor by controlling the film thickness of the insulating film formed on the side surface of the vertical silicon groove.

(Operation) According to the present invention, since the n-channel MIS transistor and the p-channel MIS transistor forming the CMOS are separately formed in the substrate itself and in the epitaxial layer embedded after the groove is formed in the substrate, Each transistor can be separated by an insulating film deposited on the side surface of the groove. Therefore, the size of the element isolation region can be arbitrarily selected according to the film thickness of the insulating film without depending on a special high resolution lithography technique, and the depth is determined by the etching depth of the silicon trench. Therefore, the deep and narrow isolation region required for CMOS isolation can be easily realized. Further, the concentration of the well can be freely distributed in the depth direction by ion implantation, doping during epitaxial growth, etc., and the well expansion can be almost ignored.

(Example) Hereinafter, the Example of this invention is described in detail using drawing. 1 (a) to 1 (f) are schematic views showing a sectional structure in a main step of a complementary semiconductor device manufactured according to an embodiment of the present invention. P type 1 Ω · cm (up to 10 ¹⁶ cm ^-3 ) plane orientation (100) Si substrate 1 surface is thermally oxidized to a thickness of 5000
An SiO ₂ film of Å is formed, and an SiO ₂ film mask 2 for forming a silicon groove is formed. At this time, <100> is set in the pattern direction. Next, a silicon groove 3 having a depth of 5 μm is formed by reactive ion etching so that the etching side surface becomes perpendicular to the substrate surface.
Are formed (FIG. 1 (a)).

Next, after thermal oxidation oxidizes the Si surface of the groove for about 2500 Å, the SiO ₂ film at the bottom of the groove is etched again by reactive ion etching to leave an insulating film on the side surface of the groove. Then, without using a mask, 1 × 10 ¹⁴ cm ⁻² of phosphorus is implanted at an acceleration energy of 120 keV by an ion implantation method, and annealing is performed for activation to obtain the structure of FIG. 1 (b). Next, when Si is selectively epitaxially grown only on the exposed Si surface without being deposited on the insulating film and the thickness of the epitaxial layer 6 is the same as the depth of the silicon groove, the silicon surface becomes almost flat. The structure of FIG. Next, after etching the SiO ₂ film 2 used as an etching mask, a field oxide film 7 is formed by a selective oxidation method, and at the same time, an n well 8 is obtained. Then, a gate oxide film is formed to obtain FIG. 1 (d). Next, channel ion implantation is performed to control the threshold voltage of the MOS transistor using the resist as a mask, and an n-channel MOS transistor is formed to form a channel stopper for preventing inversion on the sidewall of the insulating film. Boron is implanted into the region with an acceleration energy of 400 keV and a dose of 1 × 10 ¹⁴ cm ^-2 . This forms a layer with a concentration of ~ 10 ¹⁹ cm ^-3 .
Next, deposit 4500Å of polycrystalline silicon by low pressure CVD method,
The gate electrode 11 is formed by using the lithography technique and the reactive ion etching technique. Next, arsenic was added to the n-channel MOS transistor region at an acceleration energy of 150 keV at 5 × 10 ¹⁵
cm ⁻² ion-implanted, n channel source / drain 12 and p channel MOS transistor region are accelerated with boron 3
2 × 10 ¹⁵ cm ^-2 ions are implanted at 0 keV to form a p-channel source / drain 13 (FIG. 1 (e)). Next, S by the CVD method
When the iO ₂ film 14 is deposited, the contact holes are opened, and aluminum wiring is performed, a complementary semiconductor device having a sectional structure as shown in FIG. 1 (f) is obtained.

Although the substrate used in this embodiment is p-type and has a plane orientation (100), the present invention is not limited to this. For example, an n-type substrate is used to form a p-well, and a p-channel MOS transistor is formed on the substrate with an epitaxial layer. An n-channel MOS transistor may be used above. Also, Si for digging Si groove
The reason why the O ₂ mask pattern is set to the <100> direction is that facet planes do not appear in the epitaxial growth layer and stacking faults are few, but the present invention is not limited to this. But it doesn't matter. Also, the silicon groove is 5 μm,
The depth is not limited to this, and the etching shape may be a vertical shape. Further, SiO ₂ film an insulating film formed on the Si groove surface by was a SiO ₂ film having a thickness of 2500Å by thermal oxidation, for example, a CVD method not limited to this, Si ₃ N ₄
It may be a film, and the thickness is not limited as long as it is electrically insulated. Further, although the boron ion implantation for the channel stopper is performed at the same time as the channel implantation step, for example, p-type impurities may be ion implanted at the beginning of the manufacturing process, and the same effect can be obtained. A phosphorus ion-implanted layer 5 is formed at the bottom of the groove, and the channel stopper region 10 is formed.
The reason for forming shallow is to prevent the junction breakdown voltage from decreasing due to contact between the two.

(Effects of the Invention) According to the present invention, the thickness of an insulating film used for element isolation is not defined by a lithographic technique and can be reduced. Further, no mask is required when forming the well, and the high-concentration layer is formed in the deep portion without performing high-temperature annealing or the like (for the substrate concentration of about 10 ¹⁶ cm ^-3
10 ¹⁹ cm at a concentration of ^-3) have, and low surface concentrations well is less lateral diffusion of the can well formation. As a result, a device that is resistant to latch-up is obtained even when the size is reduced.

[Brief description of drawings]

FIG. 1 is a schematic view showing a sectional structure in a main manufacturing process of a complementary semiconductor device in an example of the present invention. Second
The figure is a schematic view showing a cross-sectional structure of a complementary semiconductor device manufactured by a conventional example. In the figure, 1 ... P-type Si substrate, 2 ... SiO ₂ film mask 3 ... Trench, 4 ... Sidewall SiO ₂ film 5 ... Phosphorus ion implantation layer, 6 ... Epitaxial layer 7 ... Field oxide film, 8, 23 ... N-well 9 ... Gate oxide film, 10 ... Channel stopper region 11,26 ... Gate electrode 12,27 ... N-channel source / drain 13,28 ... P-channel source / drain 14 ... CVDSiO ₂ film, 15, 30 ... Aluminum wiring 21 ... High-concentration p-type substrate Region, 22 ... Low-concentration p-type epi layer 24 ... Silicon oxide film, 25 ... Trench isolation region 29 ... Interlayer insulating film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 27/08 331 C 8934-4M 27/092 (56) Reference JP-A-58-35966 (JP , A) JP 58-192346 (JP, A) JP 60-21560 (JP, A) JP 60-95962 (JP, A)

Claims (1)

[Claims] 1. A groove in which a side surface is vertical to a substrate surface is formed on a single crystal silicon substrate, an insulating film is formed on the side surface of the groove, and the single crystal silicon is selectively formed in the groove. Silicon is epitaxially grown so as to be substantially flush with the substrate surface, an insulated gate field effect transistor is formed on the single crystal silicon substrate, and an insulated gate field effect transistor of a different conductivity type is formed on the epitaxial layer. In the method of manufacturing a complementary semiconductor device,
At the beginning of the manufacturing process or after epitaxial growth,
A step of forming a p-type layer having a high impurity concentration in a region which is shallower than the central portion between the bottom of the insulating film which becomes the element region for forming the n-channel field effect transistor and the substrate surface and does not overlap with the source / drain by the ion implantation And a step of forming an n-type layer having a high impurity concentration on the bottom surface of the groove after digging the groove and then performing the epitaxial growth.