JPH079982B2 - Charge transfer device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device capable of obtaining excellent high speed operation characteristics.

2. Description of the Related Art A conventional charge transfer device has a typical structure as shown in FIG. 2A. In this structure, buried channel regions 7 and 10 are formed below the two layers of polycrystalline silicon gates 1 and 2. Further, the impurity concentration of the buried channel is higher in the region 7 than in the region 10. Therefore, the polycrystalline silicon gate 1 serves as a signal charge storage gate, and the polycrystalline silicon gate 2 serves as a transfer gate. In the figure, 8 is a silicon substrate and 11 is a gate oxide film.

The charge transfer in the case of this conventional structure will be described with reference to the potential model diagrams of FIGS. 2B and 2C. 2B, 2C,
Indicates the state of the potential under the gate.
The position corresponds to FIG. 2A. In FIG. 2B, the pulse φ ₁ applied to the electrode 3 is at a high level (hereinafter “H”), and the pulse φ ₂ applied to the electrode 4 is at a low level (hereinafter, “H”).
In the case of "L", the signal charge 9 is accumulated under the first gate of the polycrystalline silicon gate 1 of the electrode 3.
In FIG. 2C, the pulse becomes the next timing,
The pulse φ _{1 of the} electrode 3 becomes “L”, the pulse φ _{2 of the} electrode 4 becomes “H”, and it can be seen from the potential state that the signal charge 9 is transferred to the electrode 4 on the right side in the drawing.

As described above, FIG. 2 shows a conventional charge transfer portion having a structure in which a buried layer portion is divided into a storage portion and a barrier portion, which is driven by two-phase antiphase pulses. It (Reference: Charge Transfer Device (Modern Science Co., Ltd.) Yoshiyuki Takeishi, Hiroshi Kayama PP22-27) Problems to be Solved by the Invention In recent years, a plurality of one-dimensional solid-state image pickup devices are arrayed to have the same size as a subject or a document on paper. A contact image sensor has been developed. In this case, the size of one pixel is larger than that of a conventional one-dimensional solid-state imaging device using a lens, and accordingly, the gate length per stage of the charge transfer unit is also large. Therefore, the fringing field effect is reduced and the transfer efficiency is lowered, and the function as the image sensor is deteriorated especially at high speed operation.

Means for Solving the Problems In view of the above problems, the present invention provides an embedded channel unit,
The region has three opposite conductivity types to the substrate and has different concentrations, the regions are arranged in series, and the first gate electrode is formed on the highest concentration region, and the other two regions are formed. A second gate electrode is formed on one of the two regions, and the region having the higher concentration of the other two regions having different concentrations is adjacent to the region having the highest concentration under the first gate electrode. Therefore, the first gate electrode and the second gate electrode are commonly connected and connected to the clock pulse applying electrode.

Action According to the present invention, a contact image sensor with high transfer efficiency can be realized.

EXAMPLE FIG. 1A shows a sectional view of a charge transfer portion according to the present invention, and FIGS. 1B and 1C show potential profiles of charge transfer. In FIG. 1A, the structure has a two-layer polycrystalline silicon gate and a buried channel portion as in the structure of the conventional example, but the second gate length is the first times and the buried channel portion has a concentration different from each other. It is different from the conventional structure in that it is divided into three different regions. In FIG. 1A, 1 is a polycrystal silicon gate of the first gate, 2 is a polycrystal silicon gate of the second gate, 5, 6, and 7 are buried channel regions, and the impurity concentration is 7, 6, 5 It is getting bigger in order. Each of the buried channel regions 5 and 6 is formed under the polycrystalline silicon gate 2 which is the second gate, and the region 7 is formed under the polycrystalline silicon gate 1 of the first gate as in the conventional case.
The buried channel regions 5, 6, and 7 have the same size, and therefore the second gate length is twice the first gate length. Reference numeral 8 is a silicon substrate, and 11 is a gate oxide film. The region where the electrodes 3 and 4 are combined corresponds to one stage of charge transfer.

The charge transfer in the charge transfer portion having the structure according to the present invention is shown in FIG.
This will be explained using B and C. It is driven by two-phase clock pulses φ ₁ and φ ₂ as in the conventional example. In FIG. 1B, the pulse φ ₁ applied to the electrode 3 is “H” and the pulse φ ₂ applied to the electrode 4 is “L”. , The signal profile 9 is stored in the buried channel regions 6 and 7 below the electrode 3. The potential profile at the next timing is shown in FIG. 1C, and the pulse φ ₁ is applied to the electrode 3.
Is “L”, and the pulse φ ₂ is applied to the electrode 4 at “H”.
In FIG. 1C, the signal charge 9 is accumulated in the buried channel regions 6 and 7 below the electrode 4, and the charge is transferred to the right side in the drawing. Compared with the potential profile of the conventional example, the potential is also subdivided by the amount of subdivision of the gate region, and the transfer is performed smoothly. Generally, the transfer rate is said to be inversely proportional to the square of the gate length. By subdividing the gate region by the structure of the present invention, high transfer efficiency can be obtained, which is advantageous at high speed operation.

As shown in FIG. 1A, the embodiment of the present invention divides the buried channel portion into three regions having different concentrations, and is composed of a charge transfer portion having a two-layer polycrystalline silicon gate structure. As a manufacturing method, a buried channel region is formed immediately before the formation of the polycrystalline silicon gate 2 of the second gate.
By implanting ions 5 and 6 with the same species and the same dose twice, and by patterning the photoresist film, the buried channel region 5 that is not implanted once and the buried channel region 6 that is implanted twice are formed. And the difference in concentration is provided. Further, the size of each region is also determined by patterning the photoresist film. The other manufacturing method can be carried out by a method which is completely the same as the conventional structure.

EFFECTS OF THE INVENTION The present invention provides a contact type one-dimensional solid-state imaging device in which the size of one gate length is large, and by subdividing the gate region, high transfer efficiency is obtained, and the effect is particularly great at high speed operation. Become.

[Brief description of drawings]

FIG. 1 is a structural sectional view and a potential model diagram of a charge transfer device according to an embodiment of the present invention, and FIG. 2 is a structure and a potential model diagram of a conventional charge transfer device. 1 ... Polycrystalline silicon gate, 2 ... Polycrystalline silicon gate, 3,4 ... Electrodes to which clock pulse is applied, 5,6,
7, 10 ... buried channel region, 8 ... silicon substrate, 9 ... signal charge, 11 ... gate oxide film.

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, which comprises three regions having conductivity types opposite to those of the substrate and having different concentrations, said regions being arranged in series, and the uppermost region having the highest concentration. Has a first gate electrode formed thereon, a second gate electrode is formed on the other two regions, and the region having the higher concentration of the other two regions having different concentrations is A charge transfer device having a structure in which a first gate electrode and a second gate electrode are commonly connected to a clock pulse applying electrode, being close to a region having the highest concentration under the first gate electrode.