JPH0810703B2 - Method for manufacturing field effect transistor - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a method for manufacturing a metal-semiconductor junction field effect transistor (MESFET).

[Background of the Invention]

FETs using compound semiconductors such as GaAs and InP show excellent characteristics in high frequency and high speed, and amplifiers in the microwave band and above,
Alternatively, it is used as a high-speed digital element that integrates them. For FETs, the structure of MESFET, which uses metal with a junction junction for the gate electrode, is mainly used. The FET with this structure has a short gate length, a small gate junction capacitance, a small parasitic resistance between the gate and the source, and a small resistance of the gate metal.

The self-aligned structure of the n ⁺ ion-implanted layer with a highly heat-resistant gate electrode is often used as a method for producing a high-performance FET with high yield. This gate metal is mainly
W-based alloys such as WSix are used. This is because even if the heat treatment for activating the ion-implanted layer at a temperature of about 800 ° C. is performed, the shrink bond does not deteriorate. A drawback of W-based gate metals is that they have higher resistance than Al or Au-based gate metals. For this reason, the FETs with the above structure have hardly been used for analog circuits. Attempts have been made to reduce the resistance of metal with heat-resistant gates, and one example is as follows.

The improved conventional FET has a heat-resistant T-type self-aligned gate structure for improved performance, as described in Spring 1985, Proceedings of the 32nd Lecture on Related Products, pp644, 31P-X-4 (SHO 60.3). It's getting rid of. However, in this structure, 2
Since the layer heat-resistant gate metal structure is used, it is difficult to control the size of the submicron gate with high precision, and it is difficult to form the ohmic electrode on the entire surface of the gate pattern by self-alignment.

[Object of the Invention]

An object of the present invention is to provide a manufacturing method suitable for a high performance MESFET.

[Outline of Invention]

The FET using the high heat resistance gate electrode is essentially excellent in the following points. (1) Control of threshold voltage (V _T ) is better than that of the recess method, (2) Series resistance (Rs) between gate and source can be reduced by forming an n ⁺ layer by high-concentration ion implantation, (3) ) A submicron gate length (L _g ) can be formed by dry etching, which has better control than the conventional lift-off method. On the other hand, since the resistance of the gate metal is large,
The present invention was made to solve this drawback.

FIG. 1 shows a basic configuration diagram of a cross section of an FET according to the present invention.
The semi-insulating GaAs substrate crystal 1 has an n-type active layer 2 partially,
In contact with this, the WSix Schottky gate metal 3 is formed. Self-aligned technology allows both sides of the gate metal
The n ⁺ layer 5 is ion-implanted. A sidewall material 4 made of an insulating material is processed around the gate metal 3, and an insulating material 9 is further attached. Then, a source, a gate, and a drain are drilled and lift-off is performed to form an AuGe alloy and Au-based ohmic material. The manufacturing method is characterized in that a source electrode 7, a gate electrode 6, and a drain electrode 8 are formed by applying metal.

FIG. 2 shows dimensional relationships when the gate metal 3 and the gate electrode 6 have a misalignment Δ according to the present invention. The gate electrode length L _m is determined by the following relational expression, where the gate metal length L _g and the side wall width L _S.

L _m ≤L _g + 2L _S −Δ (1) Generally, the misalignment Δ due to photolithography is 0.3 μm or less by the current high technology, so for example, L _g = 0.5 μm, L _S = 0.5 μm, L _m ≦ 1.2 μm, and the gate electrode L _m can be processed. Side walls 4 by utilizing the height of the gate metal 3, may be formed by a strong dry Etsu quenching anisotropy, can be formed by coating insulating film of silica film and the like, none of the width L _S of the side wall of the gate metal high There is a degree of freedom that can be changed proportionally. The gate electrode 6 may be formed in a process different from that of the source / drain electrodes 7 and 8,
In either case, the low resistance metal determines the gate resistance.

Example of Invention

An embodiment of the present invention will be described below with reference to FIG. 50 keV of Si ions at the required 100 points on the semi-insulating GaAs substrate crystal 1
And anneal to form the n-type active layer 2. Tungsten silicide (WSix) metal 3 is deposited on the GaAs surface to a thickness of about 500 nm and processed into a gate metal 3 pattern by dry etching. To make a high-performance FET, this gate length should be 1 μm or less. Next, with photoresist pattern 51, G outside the FET area
The aAs surface is masked and annealed implanted Si ions at a high concentration in 150keV to form an n ⁺ -type low-resistance layer 5. This is self-aligned with the gate metal 3 (a). Then, the photoresist is removed and a CVD SiN film 40 is deposited to a thickness of about 600 nm (b). This SiN film 40 is dry-etched using CF ₄ -based etching gas to form the side wall 4 of the gate metal 3. This sidewall remains due to anisotropic dry etching, and the width is ~ 0.6 μm on each side. Continuing, C
A VD / SiO ₂ film 90 is deposited to a thickness of 600 nm (c). The photoresist pattern 52 is used to form holes in the source, gate, and drain regions, and then the SiO ₂ film is removed by dry etching.
70, 60 and 80 contact holes are processed (d).
After this, AuGe alloy, Ni, Au are continuously evaporated to about 500 nm.
The thickness of the metal is left, and this metal is left only in the portions which are opened by the lift-off of the photoresist pattern 52. As a result, the source electrode 7, the gate electrode 6 and the drain electrode 8 are formed (e). Since the gate electrode 6 is overlaid on the gate metal 3 of WSi, it is about 1/20 to 1 compared with the gate resistance of WSi only.
/ 30 could be lowered.

FIG. 4 is a top view of a completed view of the FET described in FIG. The outer circumference of the side wall 4 and the outer circumference of the gate electrode 6 are shown with respect to the outer circumference of the gate metal 3. Due to the effect of the side wall 4 of the insulating material, the gate electrode 6 does not directly contact the GaAs surface.

 Another embodiment of the present invention will be described below.

After processing the gate metal of WSi in Fig. 3, a silica film (called SOG) is spin-coated to form a side wall on the side surface of the gate metal. This can be formed by utilizing the property that the liquid remains thick on the side surface of the convex portion when the liquid solidifies. Subsequent steps are the same as in the above-mentioned example. It should be additionally noted that such a side wall can be similarly formed of a material such as polyimide resin or polyladder silicon resin.

 Another embodiment of the present invention will be described below.

Instead of the photoresist pattern 52 of FIG. 3 (d),
Only the gate electrode part 60 was processed and formed in a separate process. This is for the purpose of freely selecting the structure of the gate electrode 6 having a lower resistance than the source / drain electrodes 7 and 8. Al of about 700 nm was used as the gate electrode.

〔The invention's effect〕

According to the present invention, when the gate metal 3 having a short gate length and having a steep cross-section is surrounded by the side wall 4, the mechanical strength is increased and the steep step is significantly reduced.
The yield is improved when the wiring process is performed. Further, when the gate electrode is overlapped on the gate metal 3 by lift-off, as shown in FIG. 1, the surface unevenness disappears, which is also preferable for the wiring process.

As described above, in the manufacturing method of the present invention, since the Schottky junction is made of WSi metal having good heat resistance, the source-gate series resistance of the FET is reduced. Since it does not use a process of removing the active layer such as recess, it has features such as uniform FET performance, easy reproducibility of the gate length down to submicron, and the high gate resistance with WSix alone. The gate metal resistance value can be reduced by lifting off the gate sidewall and low resistance material.
There is a feature that can also be improved by noise noise gear (NF). In addition, the process is less complicated than other methods.

[Brief description of drawings]

FIG. 1 is a sectional view of the FET structure of the present invention, FIG. 2 is a sectional view of the FET structure with misalignment according to the present invention, FIG. 3 is a sectional view of an element showing a manufacturing procedure according to the present invention, and FIG. It is a top view of FET. 1 ... Semi-insulating GaAs substrate crystal, 2 ... N-type active layer, 3 ...
... gate metal, 4 ... side wall of gate, 5 ... n ⁺ low resistance layer, 6 ... gate electrode, 7 ... source electrode, 8 ... drain electrode, 9 ... insulating film.

Claims (1)

[Claims] 1. A method of manufacturing a field effect transistor using a high heat resistant gate metal for contacting a semiconductor, the method comprising: forming a source and a drain by ion implantation using the gate metal as a mask; and after forming the source and the drain. A step of forming sidewalls made of an insulating material on both sides of the gate metal in the source / drain direction; a step of coating the gate metal and the sidewalls with an insulating film; and a source / drain direction of the gate metal of the insulating film. Exposing the entire area and the upper surface portion of the side wall continuous with it by etching using a photoresist pattern as a mask;
A method of manufacturing a field effect transistor, comprising the step of forming a gate electrode made of a material having a resistivity lower than that of the material of the gate metal so as to be in contact with the gate metal by lift-off using the photoresist pattern.