JPH0810704B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0810704B2 JPH0810704B2 JP61140038A JP14003886A JPH0810704B2 JP H0810704 B2 JPH0810704 B2 JP H0810704B2 JP 61140038 A JP61140038 A JP 61140038A JP 14003886 A JP14003886 A JP 14003886A JP H0810704 B2 JPH0810704 B2 JP H0810704B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- drain
- forming
- sio
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/80—FETs having rectifying junction gate electrodes
- H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/161—Source or drain regions of field-effect devices of FETs having Schottky gates
Landscapes
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、詳しくは通信、伝送シス
テム等に用いる電力増幅器を構成するキーデバイスに好
適な、マイクロ波高出力用の電界効果型半導体装置に関
する。Description: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a field effect semiconductor for high microwave output, which is suitable for a key device that constitutes a power amplifier used in a communication system, a transmission system or the like. Regarding the device.
従来の高出力用電界効果トランジスタは「電子通信学
会技術研究報告（信学技報）第78巻（1979）第226号pp5
5〜59」に記載のように、ドレイン耐圧を大きくするた
め、第２図に示すようにリセス構造をとるようになつて
いた。特にGaAs等の化合物半導体を用いた高出力電界効
界トランジスタではこのリセス構造素子が主流となつて
いた。しかし、上記リセス構造は、エッチング技術によ
って形成されるため、能動層２の露出部分がエッチされ
て、第２図に示したように表面に段差が形成されて、製
造工程上の各種制約が起りやすいという欠点を持つてい
た。The conventional high-power field effect transistor is described in "Technical Report of IEICE Technical Report (Technical Review) Vol. 78 (1979) No. 226 pp5.
5 to 59 ", in order to increase the drain breakdown voltage, a recess structure has been adopted as shown in FIG. In particular, this recess structure element has been the mainstream in high-power field-effect transistors using compound semiconductors such as GaAs. However, since the recess structure is formed by the etching technique, the exposed portion of the active layer 2 is etched and a step is formed on the surface as shown in FIG. 2, which causes various restrictions in the manufacturing process. It had the drawback of being easy.
上記従来技術ではドレイン耐圧を高くするという点
で、効果を持つが、段差構造となる。しかし、このよう
な段差構造になると、絶縁膜や金属膜等の形成が制限さ
れたり、配線や電極等のパターンを形成する際に、断線
やパターン寸法精度の低下を配慮せねばならず、工程が
複雑になって歩留劣化，信頼度低下の原因となるという
欠点を有していた。The above-mentioned conventional technique is effective in increasing the drain breakdown voltage, but has a step structure. However, with such a step structure, formation of an insulating film, a metal film, or the like is limited, and when forming a pattern of wiring, an electrode, or the like, consideration must be given to disconnection and deterioration of pattern dimensional accuracy. However, it has a drawback that it becomes complicated and causes yield deterioration and reliability deterioration.
本発明の目的は段差を有さないプレナー構造でドレイ
ン耐圧の向上を図ることにある。すなわち、ソース・ゲ
ート・ドレイン各電極が平面上に配置されていても、ド
レイン耐圧が大きく出来る素子構造及び製造を提供する
ことを目的としている。An object of the present invention is to improve drain breakdown voltage with a planar structure having no step. That is, it is an object of the present invention to provide a device structure and a manufacturing method that can increase the drain breakdown voltage even if the source, gate and drain electrodes are arranged on a plane.
上記目的を達成するために、本発明は下記の点を構成
要素とする。In order to achieve the above object, the present invention has the following points as constituent elements.
（１） ドレイン電圧の電界を緩和するために高抵抗層
をゲート・ドレイン間に設ける。(1) A high resistance layer is provided between the gate and the drain to reduce the electric field of the drain voltage.
（２） 高抵抗層は少なくとも能動層のキヤリア濃度よ
り小さいものを用いる。(2) For the high resistance layer, at least a carrier concentration lower than the carrier concentration of the active layer is used.
（３） 高抵抗層は表面若しくは表面近傍に設ける。(3) The high resistance layer is provided on or near the surface.
したがつて、ゲート・ドレイン間に高抵抗層を設ける
場合、ドレイン電流が減少しないようにドレイン電流経
路を十分確保できるようにする。すなわち、高抵抗層は
印加したドレイン電圧によつて発生する電界を緩和させ
るのに必要な厚さ、キヤリヤ濃度にする。高抵抗層の厚
さは濃度に関係するが、100Å以上あれば効果が大とな
る。Therefore, when the high resistance layer is provided between the gate and the drain, the drain current path should be sufficiently secured so that the drain current does not decrease. That is, the high resistance layer has a thickness and a carrier concentration required to alleviate the electric field generated by the applied drain voltage. The thickness of the high resistance layer is related to the concentration, but the effect is great if it is 100 Å or more.
接合型電界効果トランジスタに於けるドレイン電圧の
破壊は下記の点で起る事が多い。The breakdown of the drain voltage in the junction field effect transistor often occurs at the following points.
ａ） ドレイン電圧の増大で電界がゲート・ドレイン間
の表面に集中して、破壊する。a) The electric field concentrates on the surface between the gate and the drain due to the increase of the drain voltage, and breaks.
ｂ） ドレイン電圧とゲート電圧の増大でドレイン側の
能動層中のバルク内で破壊する。この場合の破壊電圧は
バルク内のキヤリア濃度で決まる。プレナー型電界効果
トランジスタ動作の場合では上記ａ）でほとんどドレイ
ン電圧の破壊が決まつている。b) Breakdown in the bulk in the active layer on the drain side due to increase in drain voltage and gate voltage. The breakdown voltage in this case is determined by the carrier concentration in the bulk. In the case of the operation of the planar type field effect transistor, the breakdown of the drain voltage is almost decided in the above a).
一方、電界を緩和する方法は従来技術で示されるよう
な、形状で行う他に、誘電率、キヤリア濃度でも可能と
なる。キヤリア濃度が低い程、誘電率の大きい程、ドレ
イン耐圧を大きくすることができる。On the other hand, the method of relaxing the electric field can be performed by using the shape as shown in the prior art, as well as the dielectric constant and the carrier concentration. The lower the carrier concentration and the higher the dielectric constant, the higher the drain breakdown voltage can be.
本発明は、電界集中が起る領域の半導体層のキャリア能
度を下げることによって、ドレイン耐圧を向上させるも
のである。The present invention improves the drain breakdown voltage by lowering the carrier efficiency of the semiconductor layer in the region where electric field concentration occurs.
以下、本発明の実施例を図を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第３図に示すように基板結晶として半絶縁性GaAs基板
１を用い、有機金属を用いた結晶成長法で基板結晶１上
にｎ型GaAs層２を成長させた。有機金属を用いる方法と
はGaとしてトリメチルガリウム（金属）、Asにはアルシ
ン（ガス）を用い、ドーパントとしてSi不純物源となる
モノシラン（ガス）、キヤリアガスとして水素を用い
た。次に、第４図のように電極パターン形成用絶縁膜Si
O26をモノシランガスを用いた熱分解法で形成した後、
ホトリソグラフ工程を経てソース３、ドレイン領域４に
穴を開け、厚さ3500ÅのAu−Ge−Ni系金属膜を形成した
後、周知のリフトオフ法によって上記孔内のみに残し
て、他の部分からは除去し、さらに、アロイングし、オ
ーミツクコンタクトを形成した。その後、ゲート電極５
を同様な手法で形成した。ゲート金属としてAu/Pt/Tiの
三層構造を用い、厚さは3500Åとした。その後、第１図
のようにゲートとドレイン間に高抵抗層７を、形成する
ために第５図で示すようにホトリソグラフ工程でゲート
電極５とドレイン電極４の間以外の部分上にホトレジス
ト膜８を残した。その後、Arイオンをホトレジスト膜８
をマスクとして、120KeVで打込み、ゲート・ドレイン間
に高抵抗層７を形成した。Arイオンの代りにHe,N2など
も使用できる。As shown in FIG. 3, a semi-insulating GaAs substrate 1 was used as a substrate crystal, and an n-type GaAs layer 2 was grown on the substrate crystal 1 by a crystal growth method using an organic metal. With respect to the method of using an organic metal, trimethylgallium (metal) was used as Ga, arsine (gas) was used as As, monosilane (gas) that was a Si impurity source was used as a dopant, and hydrogen was used as a carrier gas. Next, as shown in FIG. 4, the insulating film Si for forming the electrode pattern is formed.
After forming O 2 6 by a thermal decomposition method using monosilane gas,
After making a hole in the source 3 and the drain region 4 through a photolithography process to form an Au-Ge-Ni-based metal film having a thickness of 3500Å, it is left only in the hole by a well-known lift-off method, and the other parts are removed. Was removed and further alloyed to form an ohmic contact. Then, the gate electrode 5
Was formed in a similar manner. A three-layer structure of Au / Pt / Ti was used as the gate metal, and the thickness was 3500Å. Thereafter, in order to form a high resistance layer 7 between the gate and the drain as shown in FIG. 1, a photoresist film is formed on a portion other than between the gate electrode 5 and the drain electrode 4 by a photolithography process as shown in FIG. 8 left. After that, Ar ions are applied to the photoresist film 8
Using as a mask, a high resistance layer 7 was formed between the gate and drain by implanting at 120 KeV. He, N 2 etc. can be used instead of Ar ions.
以上のように素子を作成した結果、ドレイン耐圧を9V
から18Vまで大きくすることができた。As a result of making the device as described above, the drain withstand voltage is 9V.
It was possible to increase from 18V to 18V.
実施例２ 実施例１と基本的に同じであるが第１図の高抵抗層７
の形成が異なる。すなわち、ソース３、ゲート５、ドレ
イン４電極形成後、SiO2膜６を除去した。ホトリソグラ
フ工程でゲート・ドレイン間以外にホトレジスト膜８を
残し、Arイオンをホトレジスト膜８をマスクとして25Ke
Vの加速電圧で打込んだ。素子全体の保護膜として、プ
ラズマ法によるシリコンナイトライド膜を用いた。本実
施例では高抵抗層を抵加速で可能であることが示され
た。Example 2 Basically the same as Example 1, but with the high resistance layer 7 of FIG.
Formation is different. That is, after forming the source 3, gate 5 and drain 4 electrodes, the SiO 2 film 6 was removed. In the photolithography process, the photoresist film 8 is left except between the gate and drain, and Ar ions are used for 25 Ke with the photoresist film 8 as a mask.
Driven with V acceleration voltage. A silicon nitride film formed by a plasma method was used as a protective film for the entire device. In this example, it was shown that the high resistance layer can be formed by low acceleration.
以上の様に、本発明によればイオン打込み技術を用い
る簡単な方法で高出力素子に必須であるレイン耐圧を大
幅に改善することができる。As described above, according to the present invention, it is possible to greatly improve the rain breakdown voltage, which is essential for high-power devices, by a simple method using the ion implantation technique.
機能的にはゲート・ドレイン間に高抵抗層を設けて、
電界緩和を行わせしめることにある。これに伴ない、ド
レイン耐圧が大幅に向上し、高出力素子としての機能が
大幅にアップする。本実施例によると出力として1.7倍
の改善が見られた。また、実施例で示したように、本発
明は簡単なプロセス技術で素子作成が可能となり、従来
素子作成にイオン注入技術を加えるだけで可能である。Functionally, a high resistance layer is provided between the gate and drain,
The purpose is to relax the electric field. Along with this, the drain breakdown voltage is significantly improved, and the function as a high output element is significantly improved. According to this example, the output was improved by 1.7 times. Further, as shown in the embodiments, the present invention enables the device fabrication by a simple process technique, and can be achieved only by adding the ion implantation technique to the conventional device fabrication.
第１図は本発明の素子構造の断面図、第２図は従来の素
子断面構造、第３図乃至第５図は本発明の素子作成工程
図である。 １……基板結晶、２……能動層、３……ソース電極、４
……ドレイン電極、５……ゲート電極、６……SiO2膜、
７……高抵抗層、８……ホトレジスト膜。FIG. 1 is a cross-sectional view of the element structure of the present invention, FIG. 2 is a conventional element cross-sectional structure, and FIGS. 3 to 5 are process drawings for producing the element of the present invention. 1 ... Substrate crystal, 2 ... Active layer, 3 ... Source electrode, 4
...... Drain electrode, 5 ... Gate electrode, 6 ... SiO 2 film,
7: high resistance layer, 8: photoresist film.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/808 29/812 Ｈ０１Ｌ 21/265 Ｊ (72)発明者 山根 正雄 東京都国分寺市東恋ヶ窪１丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 水田 博 東京都国分寺市東恋ヶ窪１丁目280番地 株式会社日立製作所中央研究所内 (56)参考文献 特開 昭59−171169（ＪＰ，Ａ) 特開 昭53−76675（ＪＰ，Ａ) 特開 昭57−177537（ＪＰ，Ａ)─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Internal reference number FI Technical indication location H01L 29/808 29/812 H01L 21/265 J (72) Inventor Masao Yamane 1 Higashikoigakubo, Kokubunji, Tokyo 280-chome, Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Hiroshi Mizuta 1-280, Higashi Koigakubo, Kokubunji, Tokyo Metropolitan Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-59-171169 (JP, A) Kai 53-76675 (JP, A) JP-A-57-177537 (JP, A)
Claims (1)
た結晶成長法によってGaAs層を形成する工程と、モノシ
ランを用いた熱分解法によってSiO2層を上記GaAs層上に
形成する工程と、上記SiO2層のソース電極およびドレイ
ン電極を形成すべき領域にそれぞれ穴を形成する工程
と、リフトオフ法を用いて当該穴内にAu−Ge−Ni膜を選
択的に形成して、上記SiO2層の厚さと等しい厚さを有す
るソース電極およびドレイン電極を形成する工程と、上
記SiO2層のゲート電極を形成すべき領域に穴を形成する
工程と、リフトオフ法を用いて当該穴内にAu−Ge−Ni膜
を選択的に形成して、上記SiO2層の厚さと等しい厚さを
有するゲート電極を形成する工程と、上記ドレイン電極
と上記ゲート電極の間の上記GaAs層の表面領域に、Arイ
オン、HeイオンおよびN2からなる群から選択されたイオ
ンを、上記SiO2層を介してイオン打込みして、高抵抗層
を形成する工程を含むことを特徴とする半導体装置の製
造方法。1. A step of forming a GaAs layer on a semi-insulating GaAs substrate by a crystal growth method using an organic metal, and a pyrolysis method using monosilane to form an SiO 2 layer on the GaAs layer. A step, a step of forming a hole in each of the regions of the SiO 2 layer where the source electrode and the drain electrode are to be formed, and an Au-Ge-Ni film is selectively formed in the hole using a lift-off method, forming a source electrode and a drain electrode having a thickness equal to the thickness of the SiO 2 layer, forming a hole in the region for forming the gate electrode of the SiO 2 layer, in the hole by using a lift-off method au-Ge-Ni layer selectively formed and a step of forming a gate electrode having a thickness equal to the thickness of the SiO 2 layer, the surface region of the GaAs layer between the drain electrode and the gate electrode a, Ar ions, the group consisting of He ions and N 2 La selected ions, and ion implantation through the SiO 2 layer, a method of manufacturing a semiconductor device characterized by comprising the step of forming a high-resistance layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61140038A JPH0810704B2 (en) | 1986-06-18 | 1986-06-18 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61140038A JPH0810704B2 (en) | 1986-06-18 | 1986-06-18 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62298182A JPS62298182A (en) | 1987-12-25 |
| JPH0810704B2 true JPH0810704B2 (en) | 1996-01-31 |
Family
ID=15259517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61140038A Expired - Lifetime JPH0810704B2 (en) | 1986-06-18 | 1986-06-18 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0810704B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6461067A (en) * | 1987-09-01 | 1989-03-08 | Nec Corp | Field-effect transistor and manufacture thereof |
| DE4233766C2 (en) * | 1992-10-07 | 1994-12-22 | Fraunhofer Ges Forschung | Process for the production of field effect transistors |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5376675A (en) * | 1976-12-17 | 1978-07-07 | Nec Corp | High breakdown voltage field effect power transistor |
| JPS57177537A (en) * | 1981-04-24 | 1982-11-01 | Matsushita Electric Ind Co Ltd | Isolation of semiconductor element |
| JPS59171169A (en) * | 1983-03-17 | 1984-09-27 | Nec Corp | Field effect transistor and its manufacturing method |
-
1986
- 1986-06-18 JP JP61140038A patent/JPH0810704B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62298182A (en) | 1987-12-25 |
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