JPH0810731B2 - Chip carrier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip carrier used for mounting an IC on a wiring board used for an electronic device or the like.

[0002]

2. Description of the Related Art A conventional chip carrier of this type is constructed as shown in FIG. 2, and this chip carrier is, for example, IEICE TRANSAITIONS. (VOL.E 74, No. 8 AUGUST 1991).
See page 2331. This conventional technique uses TAB (Ta
pe Automated Bonding) The IC 50 is connected face down on the wiring board 51, and the cap 52 with good thermal conductivity is attached.
Is hermetically sealed. Seam welding 53 for hermetic sealing
Is used, the variation in the height direction and the inclination of the IC are
Silicon rubber 54 is absorbed as a buffer between 0 and the wiring board 51 for absorption.

Further, another conventional chip carrier is shown in FIG. 3, and this chip carrier is disclosed in JP-A-62-62.
It is described in Japanese Patent No. 545. In this other conventional chip carrier, the IC chip 67 is face-down TAB mounted similarly to the conventional technique of FIG. 2, and the cap 69 is bonded to the substrate by Au / Sn 60 and is sealed at the same time. . In other chip carriers, variations in IC mounting height are adjusted by moving the cap 69 having the cutout portion on the side surface of the substrate 61.

Further, another conventional chip carrier is shown in FIG. 4, which is also the 41st ECTC paper collection 1991.
It is published in P.704 for the year. The IC 70 is connected to a pad on a thin film provided on the wiring board 71 via a bump, and an AIN cap 75 is soldered to hermetically seal it. In this conventional example, it is considered that the cap variation and the IC mounting height variation are caused by selecting the cap after mounting the IC.

[0005]

Conventionally, in this main chip carrier, the adhesive thickness between the cap and the IC is reduced by using the conventional silicon rubber shown in FIG. 2 or by selecting the cap after mounting the IC. Although it was possible to keep it constant, with flip-chip mounting in which signals are taken out from the entire surface of the IC through bumps with the increase in the number of signals of the IC in recent years, the lower surface of the IC is made of an elastic material such as silicon rubber. It becomes impossible to protect the connection part from

Further, as in the conventional example shown in FIG. 4, the method of selecting the caps after mounting the ICs to adjust the heights requires preparing various kinds of caps having different heights, which leads to deterioration in cost and yield. There is a problem. In addition, there is a problem that solder of the bonding material scatters and flows into the chip carrier due to the flow at the time of sealing and bonding, so that the connecting portion between the IC and the substrate is easily short-circuited.

Further, when the cap provided with the notch is moved on the side surface of the substrate to adjust the variation of the IC mounting height as in the conventional example shown in FIG. 3, there is an advantage that the cost is low, but the sealing is still performed. Au / S of the joining material when joining
n scatters and flows into the chip carrier to cause I
There is a risk of short-circuiting the connection between C and the board.

FIG. 5 is an explanatory view of dimensions from the substrate to the inner wall of the cap. The variation in the height H from the substrate 81 to the inner wall of the cap 83 is about ± 0.03 mm in normal mechanical processing accuracy, and the face-down mounting from the substrate 81 is I.
The variation in the height h to the upper surface of the C chip 88 is ± 0.05 mm when the variation in the thickness of the LSI wafer and the variation in the height of the bump portion are combined. Therefore, the thickness of the adhesive material 82 for bonding the IC chip 88 and the cap 83 is the minimum. If the thickness is 0.03 mm, it will vary from 0.03 to 0.21 mm. Adhesive material 8
When 2 is thick, there is a problem that the thermal resistance from the IC chip 88, which is the heat source, to the upper surface of the cap 83, which is the heat radiation surface, increases, and the cooling effect deteriorates. Further, when an adhesive is used as the adhesive material, it becomes difficult to remove voids in the adhesive when the adhesive becomes thick, and there is a problem in that reliability quality is poor, such as an increase in thermal resistance and the occurrence of cracks due to thermal stress. is there.

[0009]

A chip carrier of the present invention comprises a substrate having a pad, an IC chip mounted face down on the substrate, and a cap adhered to the back surface of the IC chip. And a chip carrier for sealing the IC chip with the cap, which has a sealing height adjustment frame having a structure that fits with the cap, and the substrate is provided when the sealing height adjustment frame and the cap are joined. There is a step in which the upper surface of the substrate is higher than the lower end position of the cap.

Another chip carrier of the present invention is claim 1.
In the described chip carrier, there is a step in which the bonding position of the cap and the sealing height adjusting frame is included from the upper surface of the substrate.

[0011]

The present invention will be described below with reference to the drawings.

FIG. 1A is a sectional view showing a chip carrier according to an embodiment of the present invention. In FIG. 1A, the IC
The chip 8 is a high temperature solder bump 4 (for example, 5Sm / 95Pb,
10Sn / 90Pb, 80Au / 20Sn, etc.) is mounted face down on the pad 3 on the substrate 1 by the flip chip connection method.

The substrate 1 has a step at the end thereof so that the joining position of the sealing height adjusting frame 7 and the cap 10 is lower than the upper surface of the substrate 1, and the sealing height adjusting frame 7 is The step portion is joined with the sealing material 5.

The back surface of the IC chip 8 is adhered to a cap 10 by an adhesive material 9, and the cap 10 is sealed and joined by a sealing height adjusting frame 7 and a sealing material 6.

Since the sealing height adjusting frame 7 has a structure in which the surface is in contact with the height direction of the cap 10, the substrate 1 to IC
Even if the height to the upper surface of the chip 8 or the height from the substrate 1 to the inner wall of the cap 10 varies, the sealing and bonding can be reliably performed. As a method of supplying the adhesive material 9, I
It becomes possible to print on the back surface of the C chip 8 using a template, etc., and it becomes possible to thinly supply a certain amount of adhesive material with good thermal conductivity (for example, Epotek XD9028 made by Epotek Co., Sn / Pb solder). . Since the cap 10 cools the IC chip 8 via the adhesive material 9, a material having good thermal conductivity and a coefficient of thermal expansion as close to that of silicon as possible (eg Cu / W, A1N, glass ceramics, mullite, etc.) is used. .

Since the sealing height adjusting frame 7 is joined to the step portion of the substrate 1 and the joining position with the cap 10 is lower than the upper surface of the substrate 1, the sealing material 6 scatters during the sealing. Even if it flows, it is prevented from being inserted into the connecting portion between the IC chip 8 and the substrate 1. As a result, the sealing material 6 can be made of a fluid material such as Au / Sn or Sn / Pb solder.

Although flip-chip connection is performed in this manner in FIG. 1A, the method of connecting the IC chip 8 is shown in FIG.
As shown in (B), the IC chip 8 and the pad 3 on the substrate 1 are connected to the high-temperature solder (for example, the pad 3 on the substrate 1) via the micro lead pins 24 (hereinafter referred to as micro pins).
10Sn / 90Pb, 80Au / 20Sn, etc.) and micropin 4
Even if the IC chip 8 side and the pad 21 on the IC chip 8 are joined by a micropin connection method using a higher-temperature solder (for example, Cd / Ag, Zn / A1 etc.), the IC chip 8 is faced on the substrate 1. If it is installed down, the same effect can be obtained.

However, in the micro pin connection method as shown in FIG. 1B, the mysulo-pins 24 alleviate the thermal stress due to the difference in thermal expansion between the IC chip 8 and the substrate 1, so that the substrate 1 is made of alumina ceramic, for example. It is possible to use a material having a coefficient of thermal expansion different from that of silicon. However, in the flip chip mounting method using solder bumps of the embodiment shown in FIG. 1A, a material having a coefficient of thermal expansion depending on the size of the IC chip 8 is used. Selection is required.

FIG. 1C shows an embodiment in which micro pins 32 are used instead of the bumps 2 of the embodiment shown in FIG. 1A, and FIG. 1D shows the embodiment shown in FIG. 1B. An example in which the micro pins 32 are used instead of the bumps 2 will be shown.

Next, an example of an assembling method will be described with reference to FIG. First, the sealing height adjusting frame 5 is bonded to the substrate 1 using the sealing material 5. Next, the IC chip 8 is flip-chip mounted on the substrate 1. Next, after a certain amount of the adhesive material 9 is supplied to a predetermined position of the cap 10 using a template or the like, IC
The back surface of the chip 8 is aligned with the cap 10 and mounted, and heated. Finally, the joint surface between the cap 10 and the sealing height adjusting frame 7 is heated from the side surface, and at the same time, the sealing material 6 is supplied to carry out sealing joining.

When assembling the chip carrier of the present invention by the procedure, the sealing material 5, bumps 4, adhesive material 9, sealing material 6
It is necessary to stratify the junction temperatures of. To give an example,
94Au / 6Si (370 ℃) as the sealing material 5 and 5Sn / as the bump 4
95Pb (320-324 ℃), 80Au / 20Sn (280 as adhesive material 9
63 ° C.) and 63Sn / 37Pb (183 ° C.) can be used as the sealing material 6.

[0022]

As described above, since the chip carrier of the present invention has the sealing height adjusting frame between the cap for sealing the IC and the substrate, the adhesive material used for bonding the IC and the cap together. Can be made thin and uniform, and as a result, it has the effect of lowering the thermal resistance from the IC to the top surface of the cap, improving cooling efficiency, and facilitating removal of the binder in the adhesive. It also has the effect of improving sex quality.

Further, since the encapsulating material is prevented from entering the chip carrier, it has the effects of improving reliability quality and improving product yield.

[Brief description of drawings]

FIG. 1 is a view showing a cross section of each embodiment of the present invention.

FIG. 2 is a sectional view showing a conventional chip carrier.

FIG. 3 is a cross-sectional view showing another conventional chip carrier.

FIG. 4 is a sectional view showing still another conventional chip carrier.

FIG. 5 is an explanatory diagram showing a cross-sectional structure of a conventional chip carrier.

[Explanation of symbols]

 1 Substrate 3,21 Pad 4 Solder Bump 5,6 Sealing Material 7 Sealing Height Adjustment Frame 8 IC Chip 9 Adhesive Material 10 Cap 24, 32 Micro Pin

Claims (2)

[Claims] 1. A substrate having a pad, an IC chip mounted by face down of the substrate, and a cap adhered to the back surface of the IC chip, and the substrate and the cap seal the IC chip. The chip carrier has a sealing height adjustment frame having a structure that fits with the cap, and the substrate has a step where the substrate upper surface is higher than the lower end position of the cap when the sealing height adjustment frame and the cap are joined. A chip carrier having. 2. The chip carrier according to claim 1, wherein the joint position of the cap and the sealing height adjusting frame has a step which is pulled from the upper surface of the substrate.