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JPH0810792B2 - Method for manufacturing multilayer wiring board - Google Patents
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JPH0810792B2 - Method for manufacturing multilayer wiring board - Google Patents

Method for manufacturing multilayer wiring board

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Publication number
JPH0810792B2
JPH0810792B2 JP3105533A JP10553391A JPH0810792B2 JP H0810792 B2 JPH0810792 B2 JP H0810792B2 JP 3105533 A JP3105533 A JP 3105533A JP 10553391 A JP10553391 A JP 10553391A JP H0810792 B2 JPH0810792 B2 JP H0810792B2
Authority
JP
Japan
Prior art keywords
wiring board
wiring
thick film
thin film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3105533A
Other languages
Japanese (ja)
Other versions
JPH04226097A (en
Inventor
旻 村田
一之 藤本
常彰 亀井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3105533A priority Critical patent/JPH0810792B2/en
Publication of JPH04226097A publication Critical patent/JPH04226097A/en
Publication of JPH0810792B2 publication Critical patent/JPH0810792B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 【0001】 【産業上の利用分野】本発明は、厚膜配線基板部と薄膜
配線基板部とからなる混成構成の多層配線基板の製造方
法に関する。 【0002】 【従来の技術】電子計算機等に用いる大容量の混成集積
回路用多層配線基板として、一般に配線を厚膜印刷焼結
方式で形成し、基板および層間絶縁物としてアルミナセ
ラミックを用いた基板が用いられている。ところが近
年、電子計算機において高機能,高速化の要請が強く、
この結果大配線容量の混成集積回路用基板が要求される
ようになった。厚膜アルミナセラミック基板では、配線
密度が印刷工程の精度で限定され(最小可能配線ピッチ
150μm)るため、配線層5〜10層、絶縁層5〜1
0層の多層で基板寸法100mm の基板が出現してい
る。層数の増大は各層間の接続点数を大幅に増すため、
基板製造歩留の大幅低下をもたらすという欠点がある。
また基板の大型化は、信号伝送路の増大をきたすため高
速化が図れない。 【0003】そこで、配線形成を半導体工業のプロセス
である薄膜ホトプロセスを用いることが試みられてい
る。薄膜プロセスを用いて多層化した基板では、電子計
算機用混成集積回路基板として必要なコネクタの着脱に
耐える数百本の端子をとりだすことは一般に困難であ
る。この端子に関しては基板裏面全域に焼結タングステ
ンにNiメッキしたピン接続部を配列し、この接続部に
銀ろうあるいははんだろうでリードピンを接続している
従来の厚膜多層配線基板が適している。ところで高密
度,高速化を要する回路領域は論理信号回路である。電
源回路グランド層は、従来の厚膜多層配線の配線密度で
十分余裕がある。したがって、論理信号層を薄膜基板部
として形成し、電源グランド層やリードピン端子部を厚
膜基板部として形成した薄膜−厚膜混成方式で高密度,
高速基板を達成できる。 【0004】薄膜−厚膜混成方式の多層配線基板の製造
は、第1図に示す工程でできる。焼結タングステンから
なる電源・グランド層2・リードピン端子部3を含む厚
膜基板部10を通常の厚膜多層基板の製法であるグリー
ンシート法で形成する。薄膜基板部の配線と接続する厚
膜基板部の配線端子4をアルミナ絶縁層5のスルーホー
ルに穴うめして形成しておく。この厚膜基板部10の上
面に薄膜基板部の配線となる整合層6を通常の薄膜プロ
セスである抵抗加熱蒸着あるいはスパッタにてAlある
いはCr/Cu/Crで形成し、ネガ型レジストを用い
るホトリソエッチングで整合層6をパターン化する。こ
のとき、配線端子4と整合層6を必ず重ねあわせる。厚
膜基板部10は製造時の焼結収縮にばらつきがあり、配
線端子4の位置ばらつきは基板中心からみてその位置の
中心からの距離の0.6〜1.0%となる。このため、
両基板部の接続を基板全域で図るためには、位置ばらつ
きの幅を配線端子4あるいは整合層6の接続部に与えな
ければならない。このため、整合層6は高密度配線化が
図れるホトリソエッチング工程を用いながら、厚膜配線
基板部の配線密度と同じにしなければならない。この上
に通常の薄膜プロセスで形成するSiO2やポリイミド
膜を絶縁層7とし、そのスルーホール8をホトリソエッ
チングで形成する。こののち、絶縁層7の上面に薄膜基
板部の配線61を整合層6と同様に形成し、更に絶縁層
71、スルーホール81を絶縁層7、スルーホール8と
同様に形成する。これらの工程を繰返して薄膜基板部1
1を形成し、高密度、高速用の多層配線基板となる。 【0005】この多層配線基板では、高密度化になんら
寄与しない厚膜−薄膜接続の適合のための層が整合層6
および絶縁層7と2層要しており、このため、工程が冗
長され、歩留まり低下の原因となっている。 【0006】また、第1図の配線端子4には、整合層6
で覆われない個所が必ず発生する。これは整合層6のパ
ターン化時の金属エッチング用のエッチング液が配線端
子4に触れるため、配線端子4を酸化(腐食)させ、信頼
性を落す原因となる。また、厚膜基板部10の表面粗さ
は通常3〜4μmあるため、整合層6のホトリソエッチ
ングが困難であり、配線抵抗の安定性が悪いことがわか
っている。 【0007】本発明の目的は、以上の製造上の欠点を除
き、厚膜配線基板部と薄膜配線基板部とからなる混成構
成の多層配線基板の製造方法を提供することにある。 【0008】 【課題を解決するための手段】上記目的は、厚膜配線基
板部のスルーホールを焼結収縮による位置ずれ量を見込
んだ大きさとし、該スルーホールに配線端子を形成し、
該厚膜配線基板部の上部面に整合層を介することなく絶
縁層を直に形成し、該絶縁層の一部にホトリソエッチン
グ法によりスルーホールを形成し、該スルーホールを介
して前記配線端子と薄膜配線基板部との接続を行なうこ
とを特徴とする厚膜配線基板部と薄膜配線基板部とから
なる混成構成の多層配線基板の製造方法により達成され
る。 【0009】 【作用】本発明は、従来技術の整合層が担っていた厚膜
配線基板部の焼結収縮による位置ずれによっても該厚膜
配線基板部と薄膜配線基板部とを適合できるという機能
を厚膜配線基板部のスルーホールに形成した配線端子に
担わせることにした。即ち、厚膜配線基板部のスルーホ
ールの大きさを、該厚膜配線基板部の焼結収縮による位
置ずれ量を見込んだ大きさとしたのである。その結果、
本発明では、従来技術において必要であった適合のため
の整合層が不要となり、整合層の形成時に薄膜プロセ
スとして用いる金属エッチング用のホトリソエッチング
液が厚膜配線基板部の配線端子4に触れて酸化(腐食)を
引き起こし、信頼性を低下させるという問題はなくな
り、また、表面が粗い厚膜配線基板部上に苦労して薄
膜プロセスであるホトリソエッチングを行ない、整合層
を形成する必要がなくなった。 【0010】 【実施例】以下第2図に示す実施例により、本発明を具
体的に説明する。同図(a)は厚膜配線基板部を作る方
法を説明する図、同図(b)は厚膜配線基板部に薄膜配
線基板部を形成する方法を説明する図である。 【0011】 【実施例】第2図に示す10は、タングステンの焼結体
からなる電源配線層やグランド層2を含む、グリーンシ
ート法で製造したアルミナ厚膜多層配線基板部10であ
る。配線端子4はアルミナ絶縁層5のスルーホールにタ
ングステンペーストを穴うめ焼結して形成されている。
配線端子4の径は、接続する薄膜のスルーホール径に寸
法ばらつきを加えた径とする。寸法ばらつきの式は、 (寸法ばらつき)=(グリーンシート法での焼結収縮ばらつき)×(基板の長辺寸法) ×1/2 であり、ここで、(グリーンシート法での焼結収縮ばら
つき)を0.6〜1.0%、(基板の長辺寸法)を50m
mとすると、 (寸法ばらつき)=(0.6〜1.0%)×(50mm)×1/2 =0.15〜0.25mm となる。そして、薄膜のスルーホール径を50μmとす
ると、配線端子4の径は、200〜300μmとなる。
基板部10の裏面には焼結タングステンパッドに銀ろう
で接続されたリードピン9がついている。配線端子4
は、アルミナ絶縁層5の上面と同一平面もしくは10μ
m以下で突出するように形成されている。この基板部1
0にポリイミド樹脂をスピンコーティング方式で塗布
し、熱硬化して絶縁層7を形成する。この絶縁層7にネ
ガ型レジスト(例えば、東京応化製のOMR83)をコー
ティングし、レジストを紫外線露光でパターン化し、湿
式エッチングで配線端子4の上部の絶縁層7にスルーホ
ール8を形成する。ここで用いるエッチング液は絶縁膜
用のものであり、金属用のものとはエッチング液の種類
が異なる。このため、絶縁膜用のエッチング液は金属で
構成される配線端子4には実質的に悪影響を与えない。
また、スルーホール8の形成にネガ型レジストを用いる
のは、厚膜基板部10が硬く、そり、うねりがあるた
め、硬くて壊れやすいポジ型レジストでは露光時にマス
クとの接触でレジストがはく離し、絶縁層7にピンホー
ルが発生するのを避けることにある。そして配線端子4
の上面をアルミナ絶縁層の上面より沈めないのは、ネガ
型レジストを用いるので、露光時にマスクと間隔があく
と紫外光のまわりこみでスルーホール8が形成できなく
なるのを避けるためである。スルーホール8の形成後、
抵抗加熱あるいは、エレクトロンビーム蒸着スパッタな
どでアルミあるいはチタン+銅+チタンからなる配線6
1を形成し、通常のホトリソ工程でパターン化する。こ
の配線61のパターン化は、表面粗さの大きい厚膜多層
配線基板部10(表面粗さ4〜6μm)上ではなく、滑ら
かな絶縁層7の上で行なうため、20〜40μmピッチ
での高密度な配線化ができ、かつ、ピンホールの発生を
抑制できる。また、前述したように、配線61のパター
ン化は絶縁層7の上で行なわれるものであり、従来技術
のように配線端子4上にて整合層6を金属用のエッチン
グ液を用いてパターン化することで配線端子4をもエッ
チングするような心配はない。以降、この上部にポリイ
ミド樹脂層71と配線61を繰返し形成し、薄膜多層配
線基板部11を形成する。なお、リードピン9は、薄膜
配線基板部11を形成したあとに付けてもよい。 【0012】 【発明の効果】以上のように、本発明によれば、従来の
厚膜多層配線基板より2〜3倍の高密度化図れる。ま
た、配線総数、スルーホール接続数が大幅に低減でき、
製品歩留まりが向上する。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a multilayer wiring board having a hybrid structure including a thick film wiring board portion and a thin film wiring board portion. As a multi-layer wiring board for a large-capacity hybrid integrated circuit used in an electronic computer or the like, a wiring is generally formed by a thick film printing sintering method, and a board using alumina ceramics as a board and an interlayer insulator. Is used. However, in recent years, there has been a strong demand for high functionality and high speed in electronic computers,
As a result, a hybrid integrated circuit substrate having a large wiring capacity has been required. In the thick film alumina ceramic substrate, the wiring density is limited by the accuracy of the printing process (minimum possible wiring pitch 150 μm), so that the wiring layers 5 to 10 and the insulating layers 5-1
A substrate having a substrate size of 100 mm 2 has appeared with 0 layers. Since the increase in the number of layers significantly increases the number of connection points between layers,
There is a drawback that the yield of substrate manufacturing is significantly reduced.
In addition, an increase in the size of the board causes an increase in the number of signal transmission paths, and thus the speed cannot be increased. Therefore, it has been attempted to use a thin film photoprocess, which is a process in the semiconductor industry, for forming wiring. It is generally difficult to take out hundreds of terminals which can withstand attachment / detachment of a connector, which is required as a hybrid integrated circuit board for electronic computers, in a board which is multilayered using a thin film process. For this terminal, a conventional thick film multilayer wiring board in which pin connection parts made of sintered tungsten and plated with Ni are arranged all over the back surface of the substrate, and lead pins are connected to the connection parts with silver solder or solder solder is suitable. The circuit area that requires high density and high speed is the logic signal circuit. The power circuit ground layer has a sufficient margin in the wiring density of the conventional thick film multilayer wiring. Therefore, the logic signal layer is formed as a thin film substrate portion, and the power supply ground layer and the lead pin terminal portion are formed as thick film substrate portions.
A high speed substrate can be achieved. The thin-film / thick-film hybrid type multilayer wiring board can be manufactured by the process shown in FIG. The thick film substrate portion 10 including the power source / ground layer 2 and the lead pin terminal portion 3 made of sintered tungsten is formed by a green sheet method which is a usual method for producing a thick film multilayer substrate. The wiring terminals 4 of the thick film substrate portion connected to the wiring of the thin film substrate portion are formed by filling the through holes of the alumina insulating layer 5. A matching layer 6 to be the wiring of the thin film substrate is formed on the upper surface of the thick film substrate 10 by Al or Cr / Cu / Cr by resistance heating vapor deposition or sputtering which is a normal thin film process, and a negative resist is used. The matching layer 6 is patterned by so-etching. At this time, the wiring terminal 4 and the matching layer 6 are always overlapped. The thick film substrate portion 10 has variations in sintering shrinkage during manufacturing, and the positional variation of the wiring terminals 4 is 0.6 to 1.0% of the distance from the center of the position when viewed from the substrate center. For this reason,
In order to connect the two board portions over the entire area of the board, the width of positional variation must be given to the connection portion of the wiring terminal 4 or the matching layer 6. Therefore, the matching layer 6 must have the same wiring density as that of the thick film wiring board portion while using a photolithographic etching process capable of achieving high density wiring. An SiO 2 or polyimide film formed by a normal thin film process is used as an insulating layer 7, and a through hole 8 is formed by photolithography etching. After that, the wiring 61 of the thin film substrate is formed on the upper surface of the insulating layer 7 in the same manner as the matching layer 6, and the insulating layer 71 and the through hole 81 are formed in the same manner as the insulating layer 7 and the through hole 8. By repeating these steps, the thin film substrate 1
1 to form a multi-layer wiring board for high density and high speed. In this multilayer wiring board, the matching layer 6 is a layer for adapting thick film-thin film connection which does not contribute to high density.
In addition, the insulating layer 7 and two layers are required, which makes the process redundant and reduces the yield. A matching layer 6 is formed on the wiring terminal 4 in FIG.
There will always be places that are not covered by. This causes the etching liquid for metal etching at the time of patterning the matching layer 6 to come into contact with the wiring terminals 4, so that the wiring terminals 4 are oxidized (corroded) and the reliability is lowered. Further, since the surface roughness of the thick film substrate portion 10 is usually 3 to 4 μm, it is known that photolithography etching of the matching layer 6 is difficult and the stability of the wiring resistance is poor. An object of the present invention is to provide a method for manufacturing a multilayer wiring board having a hybrid structure composed of a thick film wiring board section and a thin film wiring board section, excluding the above manufacturing defects. [0008] The above-mentioned object is to make the through hole of the thick film wiring board portion a size that allows for the amount of positional displacement due to sintering shrinkage, and form a wiring terminal in the through hole.
An insulating layer is directly formed on the upper surface of the thick film wiring board portion without a matching layer, a through hole is formed in a part of the insulating layer by a photolithography etching method, and the wiring is formed through the through hole. This is accomplished by a method of manufacturing a multilayer wiring board having a hybrid structure including a thick film wiring board section and a thin film wiring board section, characterized in that terminals are connected to the thin film wiring board section. The present invention has a function of adapting the thick film wiring board portion and the thin film wiring board portion even if the thick film wiring board portion is misaligned due to the sintering shrinkage of the thick film wiring board portion, which was carried by the matching layer of the prior art. The wiring terminals formed in the through holes of the thick film wiring board portion are to be carried. That is, the size of the through hole in the thick film wiring board portion is set to a size that allows for the amount of positional deviation due to the sintering shrinkage of the thick film wiring board portion. as a result,
According to the present invention, the matching layer for matching which is required in the prior art is not necessary, and the photolithographic etching solution for metal etching used as a thin film process when forming the matching layer touches the wiring terminals 4 of the thick film wiring board portion. However, the problem of reducing reliability due to oxidation (corrosion) is eliminated, and it is necessary to form a matching layer by performing photolitho etching, which is a thin film process, on the thick film wiring board with a rough surface. lost. The present invention will be described in detail with reference to the embodiment shown in FIG. FIG. 7A is a diagram for explaining a method of forming a thick film wiring board portion, and FIG. 7B is a diagram for explaining a method of forming a thin film wiring substrate portion on a thick film wiring substrate portion. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference numeral 10 shown in FIG. 2 is an alumina thick film multilayer wiring board portion 10 manufactured by a green sheet method, which includes a power supply wiring layer and a ground layer 2 made of a sintered body of tungsten. The wiring terminals 4 are formed by filling a through hole of the alumina insulating layer 5 with tungsten paste and sintering it.
The diameter of the wiring terminal 4 is a diameter obtained by adding dimensional variation to the through hole diameter of the thin film to be connected. The formula for the dimensional variation is (dimensional variation) = (variation in sintering shrinkage in the green sheet method) x (dimension of the long side of the substrate) x 1/2, where (variation in sintering shrinkage in the green sheet method) ) Is 0.6 to 1.0%, (long-side dimension of substrate) is 50 m
When m, (dimensional variation) = (0.6 to 1.0%) × (50 mm) × 1/2 = 0.15 to 0.25 mm. When the through hole diameter of the thin film is 50 μm, the diameter of the wiring terminal 4 is 200 to 300 μm.
The lead pins 9 connected to the sintered tungsten pads with silver solder are attached to the back surface of the substrate portion 10. Wiring terminal 4
Is the same plane as the upper surface of the alumina insulating layer 5 or 10 μ
It is formed so as to project below m. This board part 1
0 is coated with a polyimide resin by a spin coating method and heat-cured to form the insulating layer 7. The insulating layer 7 is coated with a negative resist (for example, OMR83 manufactured by Tokyo Ohka Kabushiki Kaisha), the resist is patterned by exposure to ultraviolet light, and a through hole 8 is formed in the insulating layer 7 above the wiring terminal 4 by wet etching. The etching liquid used here is for the insulating film, and the type of etching liquid is different from that for metal. Therefore, the etching liquid for the insulating film does not substantially affect the wiring terminals 4 made of metal.
The use of a negative resist for forming the through holes 8 is because the thick film substrate portion 10 is hard and has warps and undulations. , In order to avoid generation of pinholes in the insulating layer 7. And wiring terminal 4
The reason why the upper surface of (1) is not submerged from the upper surface of the alumina insulating layer is to prevent the through hole 8 from being unable to be formed due to the wraparound of the ultraviolet light if there is a gap from the mask during exposure because a negative resist is used. After forming the through hole 8,
Wiring 6 made of aluminum or titanium + copper + titanium by resistance heating or electron beam evaporation sputtering
1 and patterned by a conventional photolithographic process. Since the wiring 61 is patterned on the smooth insulating layer 7 rather than on the thick film multilayer wiring board portion 10 (surface roughness 4 to 6 μm) having a large surface roughness, a high pitch of 20 to 40 μm is required. The wiring can be densely formed, and the occurrence of pinholes can be suppressed. Further, as described above, the patterning of the wiring 61 is performed on the insulating layer 7, and the matching layer 6 is patterned on the wiring terminal 4 by using an etching solution for metal as in the prior art. By doing so, there is no concern that the wiring terminal 4 is also etched. After that, the polyimide resin layer 71 and the wiring 61 are repeatedly formed on the upper portion of the thin film multilayer wiring board portion 11. The lead pins 9 may be attached after the thin film wiring board portion 11 is formed. As described above, according to the present invention, the density can be increased by 2 to 3 times that of the conventional thick film multilayer wiring board. In addition, the total number of wires and the number of through-hole connections can be greatly reduced,
Product yield is improved.

【図面の簡単な説明】 【図1】薄膜混成多層基板の従来製造方法を説明する
図。 【図2】本発明の実施例を説明する図。 【符号の説明】 10…厚膜多層配線基板部、11…薄膜多層配線基板
部、4…厚膜基板部の配線端子、5…厚膜基板部の絶縁
層、7,71…薄膜基板部の絶縁層、6…整合層、61
…薄膜基板部の配線、9…リードピン。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating a conventional method for manufacturing a thin film hybrid multilayer substrate. FIG. 2 is a diagram illustrating an example of the present invention. [Explanation of reference numerals] 10 ... Thick film multilayer wiring board section, 11 ... Thin film multilayer wiring board section, 4 ... Wiring terminals of thick film board section, 5 ... Insulating layer of thick film board section, 7, 71 ... of thin film board section Insulating layer, 6 ... Matching layer, 61
... Wiring of thin film substrate, 9 ... Lead pin.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 亀井 常彰 神奈川県横浜市戸塚区吉田町292番地株式 会社 日立製作所生産技術研究所内 (56)参考文献 特開 昭56−42399(JP,A) 特開 昭50−28655(JP,A) 特開 昭53−28266(JP,A)   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kamei Tsuneaki             Stock, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Company Hitachi, Ltd. Production Technology Laboratory              (56) References JP-A-56-42399 (JP, A)               Japanese Patent Laid-Open No. 50-28655 (JP, A)               JP-A-53-28266 (JP, A)

Claims (1)

【特許請求の範囲】 1.厚膜配線基板部のスルーホールを焼結収縮による位
置ずれ量を見込んだ大きさとし、該スルーホールに配線
端子を形成し、該厚膜配線基板部の上部面に整合層を介
することなく絶縁層を直に形成し、該絶縁層の一部にホ
トリソエッチング法によりスルーホールを形成し、該ス
ルーホールを介して前記配線端子と薄膜配線基板部との
接続を行なうことを特徴とする厚膜配線基板部と薄膜配
線基板部とからなる混成構成の多層配線基板の製造方
法。
[Claims] 1. The through holes in the thick film wiring board are
A wiring terminal is formed in the through hole with an amount of misalignment taken into consideration, and an insulating layer is directly formed on the upper surface of the thick film wiring substrate without a matching layer, and a part of the insulating layer is formed. A hybrid structure comprising a thick film wiring board portion and a thin film wiring board portion, characterized in that a through hole is formed by a photolithography etching method, and the wiring terminal and the thin film wiring board portion are connected through the through hole. Manufacturing method of multilayer wiring board.
JP3105533A 1991-05-10 1991-05-10 Method for manufacturing multilayer wiring board Expired - Lifetime JPH0810792B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3105533A JPH0810792B2 (en) 1991-05-10 1991-05-10 Method for manufacturing multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3105533A JPH0810792B2 (en) 1991-05-10 1991-05-10 Method for manufacturing multilayer wiring board

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP17141281A Division JPS5873193A (en) 1981-10-28 1981-10-28 Method of producing multilayer circuit board

Publications (2)

Publication Number Publication Date
JPH04226097A JPH04226097A (en) 1992-08-14
JPH0810792B2 true JPH0810792B2 (en) 1996-01-31

Family

ID=14410230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3105533A Expired - Lifetime JPH0810792B2 (en) 1991-05-10 1991-05-10 Method for manufacturing multilayer wiring board

Country Status (1)

Country Link
JP (1) JPH0810792B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024247904A1 (en) * 2023-05-31 2024-12-05 株式会社村田製作所 Stretchable device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6753595B1 (en) * 2003-01-14 2004-06-22 Silicon Integrated Systems Corp Substrates for semiconductor devices with shielding for NC contacts
JP6375121B2 (en) * 2014-02-27 2018-08-15 新光電気工業株式会社 WIRING BOARD, SEMICONDUCTOR DEVICE, AND WIRING BOARD MANUFACTURING METHOD

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5632800B2 (en) * 1973-07-17 1981-07-30
JPS5328266A (en) * 1976-08-13 1978-03-16 Fujitsu Ltd Method of producing multilayer ceramic substrate
JPS5642399A (en) * 1979-09-13 1981-04-20 Fujitsu Ltd System for producing multilayer wiring board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024247904A1 (en) * 2023-05-31 2024-12-05 株式会社村田製作所 Stretchable device

Also Published As

Publication number Publication date
JPH04226097A (en) 1992-08-14

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