JPH0810854B2 - Data line terminator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a data line termination device of a time division two-wire bidirectional transmission system for transmitting a bidirectional signal in a time division system by a two-wire transmission line. It is about.

[Conventional technology]

Conventionally, this type of time division two-wire bidirectional transmission type data line terminating device simultaneously sends signals sent from a station side to a plurality of subscriber lines in the same phase, and the subscriber side sends the signals to the station side. By sending a signal with a certain guard time, there is no uplink / downlink signal at the same time in the same cable, so near-end crosstalk is avoided, while a clock is generated from the received data and phase-synchronized with the internal clock. I was sending and receiving.

[Problems to be solved by the invention]

Since the conventional data line terminator described above transmits and receives data at the timing synchronized with the internal clock, if multiple data line terminators are accommodated in the same cable, the phase synchronization of the transmission timing is performed. There is a drawback that you cannot do it.

[Means for solving problems]

The data line terminal device of the present invention selects the desired frame period signal by the selector according to the contents of the select signal, then detects the rising edge (or falling edge) of the selected frame period signal and outputs the initialization signal. Generate and
By this initialization signal, the timing clock of the transmission clock generation circuit or the reception clock generation circuit is output to the data transmission / reception circuit.

[Action]

The invention can accommodate any asynchronous frame period signal.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a data circuit terminating device according to the present invention. In the figure, 1 is an output terminal for outputting the following frame period signal, 2 is an input terminal for receiving the frame period signal 2a, and 3a and 3b are "00", "0".
Selector terminals to which selector signals 4 of "1" and "10" are input, 5
Is a data transmission / reception terminal for inputting / outputting transmission data or reception data, and 6 is the content of this selector signal 4 (00,01,10)
The following frame period signal 8a, frame period signal 2a
And one of the frame cycle signals 9a is selected and output, 7 is a rising edge (or a falling edge) of the input frame cycle signal and is differentiated by the original clock 11a of the main oscillating circuit described below. Is generated and outputs an initialization signal (preset or clear), 8 is initialized by the input of this initialization signal and generates and outputs various timing clocks, while generating a frame period signal 8a. The transmission clock generation circuit for outputting to the output terminal 1 and the selector 6, and 9 generates frame timings according to the received data input to the data transmission / reception terminal 5 and generates and outputs various timing clocks, while keeping a certain guard time. A reception clock generation circuit for generating the frame period signal 9a and outputting it to the selector 6, 10 is a transmission clock generation circuit 8 and A data transmission / reception circuit for transmitting and receiving data by inputting various timing clocks output from the reception clock generation circuit 9. Reference numeral 11 denotes a main clock 11a to an initialization circuit 7, a transmission clock generation circuit 8 and a reception clock generation circuit 9. This is the main oscillation circuit that outputs.

Next, the operation of the data line terminating device having the above configuration will be described. First, when the selector signal 4 is set to "00", the selector 6 selects and outputs the frame period signal 8a output from the transmission clock generation circuit 8. Therefore, the initialization circuit 7 differentially detects the rising edge of the frame period signal 8a by the original clock 11a, detects the rising edge, and outputs the initialization signal. Therefore, the transmission clock generation circuit 8 can be free-running at a constant frame period. Next, when the selector signal 4 is set to "01",
The selector 6 is a frame period signal 2a input to the input terminal 2.
To output. Therefore, the initialization circuit 7 performs differential detection on the rising edge of the frame period signal 2a by the original clock 11a, detects the rising edge, and outputs the initialization signal. Therefore, the transmission clock generation circuit 8 can operate in response to the frame period signal 2a. Similarly, when the selector signal 4 is set to "10", the selector 6 selects and outputs the frame period signal 9a output from the reception clock generation circuit 9. Therefore, the initialization circuit 7 uses the rising edge of the frame period signal 9a as the original clock 11a.
The differential detection is performed by, the rising edge is detected and the initialization signal is output. Therefore, the reception clock generation circuit 9 can be free-running at a constant frame period.

FIG. 2 is a diagram in which a plurality of the data line terminating devices shown in FIG. 1 are connected, and the data line terminating device 12a is the main device and the data line terminating devices 12b to 12n are the slave devices. Therefore, the output terminal 1 of the data line termination device 12a
Input terminals 2 of the data line terminators 12b to 12n are connected to. According to the data circuit terminating device having this configuration,
For example, the selector signal 4 input to the selector 6 of the data line terminating device 12a is set to "00", and the data line terminating device 12b ...
Each 12n selector signal 4 is set to "10". For this reason, the selector 6 of the data line terminating device 12a selects the frame period signal 8a output from the transmission clock generation circuit 8, so that the data line terminating device as described in detail in FIG.
12a will be self-propelled at a fixed frame cycle. On the other hand, the frame period signal 8a is the data line termination device 12b.
Input to each selector 6 via the input terminal 2 of 12n.
Therefore, each selector 6 receives the input frame period signal.
Since 8a is selected and output, each transmission clock generation circuit 8 is initialized by the above operation. Therefore, the transmission signals from the data line terminators 12b to 12n, which are slave devices, are out of phase with the main oscillator circuit with respect to the transmission signal from the data line terminator 12a, which is the master device (one clock width of the main clock). Sent out. Normally, this main clock (clock for digital phase synchronization circuit) uses about 10 MHz, and the data transmission speed is used at about 300 KHz, so this phase shift is of course not a problem.

〔The invention's effect〕

As described in detail above, according to the data line terminal device of the present invention, it is possible to deal with any asynchronous frame period signal by selecting the frame period signal and creating the initialization signal. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data line terminating device according to the present invention, and FIG. 2 is a configuration diagram in which a plurality of data line terminating devices shown in FIG. 1 are connected. 1 ... Output terminal, 2 ... Input terminal, 3a and 3b ... Selector terminal, 4 ... Selector signal, 5 ... Data transmission / reception terminal, 6 ... Selector, 7 ... Initialization circuit, 8 ... For transmission Clock generation circuit, 9 ... Reception clock generation circuit, 10
... Data transmission / reception circuit, 11 ... Main oscillation circuit, 12a-12n ...
… Data line terminator.

Claims (1)

[Claims] 1. A data line terminating device of a time division two-wire bidirectional transmission system, which transmits and receives data at a constant period on a two-wire line, and a selector for selecting a frame period signal and a selected frame period signal. An initialization circuit that detects a rising edge (or a falling edge) and generates an initialization signal, a transmission clock generation circuit that generates a transmission timing clock based on this initialization signal, and a reception clock that generates a reception timing clock from received data. A data circuit terminating device comprising: a timing circuit for use, a data transmitting / receiving circuit for transmitting / receiving data by inputting various timing clocks, and a main oscillating circuit for generating a main clock.