JPH0810895B2 - Image processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image processing apparatus for obtaining a high-quality reproduced image.

[Prior art]

Conventionally, it has been considered to reproduce a halftone image using a dither method or a density pattern method. However, in either case, a small threshold matrix does not provide sufficient gradation, and a large threshold matrix must be used. As a result, it is not possible to obtain a high-quality output due to a reduction in resolution, a textured structure due to the periodic structure of the matrix, and the like.

In order to eliminate the above-mentioned drawbacks, in the dither method, a method in which a plurality of dither matrixes are used to multivalue the dot information is also considered. However, in such a method, a complicated circuit configuration is required to synchronize each dither matrix, and the system must be large and complicated. Therefore, there is a limit to the multi-valued conversion using a plurality of diamatrics.

〔Purpose〕

The present invention has been made in view of the above points, and an object of the present invention is to provide an image processing apparatus capable of faithfully reproducing grayscale information with high gradation.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram of an image processing apparatus according to the present embodiment. In FIG. 1, reference numeral 1 is a digital data output device for A / D converting image data from a CCD sensor or a video camera (not shown). , The digital data of a predetermined bit having the gradation information is output. This digital data may be temporarily stored in the memory or may be input from an external device by communication or the like. From this digital data output device 1, one line of picture element data (pixel data) is continuously output, and the first pixel data is first latched by the first latch circuit 2 and then the second pixel is output by the second image clock. The latch circuit 3 of FIG.

By the way, in the first addition circuit 4, the first latch circuit 2
The addition process is performed on the image data latched in and the subsequent image data. Further, the second adder circuit 5 is the first adder circuit 4
Then, the data value added in step 3 and the data value latched in the second latch circuit 3 are added. That is, the second adding circuit 5 outputs a value obtained by adding three consecutive pixel data. In this embodiment, two addition circuits, that is, the first addition circuit and the second addition circuit are used, but it is also possible to use one addition circuit.

In the present embodiment, the digital image data output from the digital data output device 1 is a signal having a grayscale level of 65 gradations, but the second addition circuit 5 adds and synthesizes three picture elements. It becomes a signal of 193 gradations. The addition-synthesized signal is γ-corrected by the correction circuit 6 including a correction map ROM. This correction is sequentially performed so as to be different for each line, and the same correction is repeated for every three lines. The corrected image signal is digital-analog conversion circuit (D / A
It is converted into an analog quantity by a conversion circuit 7 and the amplitude is corrected by an amplification circuit 8 and then input to one terminal of a comparison circuit 9. On the other hand, a triangular wave (pulse pattern) synchronized with the three picture elements is output from the pulse pattern generation circuit 10, and this pulse pattern is matched with the dynamic range of the image signal by the amplification circuit 11 and the other terminal of the comparison circuit 9 is output. To enter. The comparator circuit 9 compares the pulse level of the repetitively generated triangular wave with the input image signal to pulse-width-modulate the image information for every three picture elements, and
Output as binarized image data. Then, the pulse width modulated image signal is input to a modulation circuit for modulating the laser beam, for example. The laser beam is turned on / off according to the pulse width, and a halftone image is formed on a recording medium (not shown).

In order to synchronize the above processing, the reference clock from the reference clock generator 12 is synchronized with the horizontal synchronization signal generated from the horizontal synchronization signal generating circuit 15 for each line by the counter 13 by, for example, 1/8. The period is counted down and becomes an image clock (pixel clock) for transferring pixel data. This pixel clock is a ternary counter 14
The pulse pattern is synchronized with the pulse pattern synchronizing clock for generating a pulse pattern. Further, the ternary counter 14 generates three types of pulse pattern synchronization clocks which are shifted by one pixel clock. That is, the pulse pattern synchronization clock for generating the pulse pattern is generated with a shift of one pixel for each line. The counters 13 and 14 perform counting operation in synchronization with the horizontal synchronizing signal 15. Further, each time the horizontal synchronizing signal is input, the ternary count 16 sequentially outputs three types of signals shifted by one line cycle. This signal is used as a selection signal for the three types of pulse pattern synchronization signals generated from the counter 14, is input to the gate circuit 17, and is also used as a selection signal for the correction up for each line in the correction circuit 6.

FIG. 2 is a diagram for explaining signal waveforms of respective parts of the apparatus of FIG. 2A shows the reference clock generated from the reference clock generator 12, and FIG. 2B shows the horizontal synchronizing signal. The horizontal synchronizing signal may be generated internally or may be given from the outside. Further, the horizontal synchronizing signal corresponds to, for example, a well-known beam detect (BD) signal if the apparatus is applied to a laser beam printer. Further, FIG. 2C shows a pixel clock output from the counter 13, which is generated in synchronization with the horizontal synchronizing signal. As described above, this pixel clock is formed by dividing the reference clock into ⅛ cycle. The ternary counter 14 further counts down the image clock shown in FIG.
A pulse pattern synchronization clock for every three picture elements is formed as shown in (f). The pulse pattern synchronization clocks shown in FIGS. 2D to 2F are signals shifted by one pixel clock, and one of them is selected for each line.
It is input to the pulse pattern generation circuit via the AND gate and the OR gate 17d. FIG. 2G shows a case where the digital image signal from the data output device 1 is directly D / A converted. The broken lines in FIGS. 2 (h) to (j) are signals obtained by adding and synthesizing the pixel data of three pixels in the adding circuit 5, correcting the correction data in the correction circuit 6, and further D / A converting in the D / A converter 7. Indicates. The addition-synthesized signals are corrected differently for each line, and even if the same input image signal for three lines is input, for example, three different types of signals are obtained after the correction. The broken lines in FIGS. 2 (h) to (j) are an example of the case where the same signal is input in three consecutive lines, and it can be seen that the form of the image signal after correction is different for each line. .

The solid lines in FIGS. 2 (h) to (j) are pulse patterns (triangular wave) output from the pulse pattern generation circuit 10.
As can be seen from the figure, 1 per line
Triangular waveforms that are shifted by picture element clocks are generated. The comparator circuit 9 compares the corrected signal with the pulse pattern, and outputs pulse width-modulated binarized data as shown in FIGS. 2 (k) to (m). That is, the signal of FIG. 2 (k) is output from the first line, the signal of FIG. 2 (l) is output from the second line, and the signal of FIG. 2 (m) is output from the third line from the comparison circuit 9. It is what is done.

As described above, in this embodiment, digital image data for three pixels are added and combined, and then corrected, and the corrected data is converted into analog image data and compared with a triangular wave having a predetermined period. As a result, almost continuous pulse width modulation becomes possible, and a high gradation image output can be obtained.

Further, in the present embodiment, since the number of gradations is increased by combining a plurality of pieces of pixel information, even if the γ correction is performed, the number of gradations does not decrease and smooth gradation reproduction is possible. It is a thing.

Further, according to this embodiment, since the synchronizing signals for generating the pulse pattern are shifted by one pixel for each line, the growth center position of the pulse width shifts for each line, and it is macroscopically viewed. The output pattern is a diagonal dot-like pattern that looks natural to the eye. Furthermore, the growth centers of the pulse width are equalized in the output screen, which is also preferable in terms of resolution reproduction.

Although the waveform of the pulse pattern used in this embodiment is a triangular wave, a sawtooth wave, a sine wave, a trapezoidal wave or the like may be used. The waveform of the pulse pattern is selected in consideration of the relationship of the linearity with respect to the pulse width of the output device and the method of growing dots. For example, a triangle wave or a sine wave grows in the center of the dot, and a sawtooth wave grows in one side.

Next, the γ correction executed by the correction circuit 6 will be described. The solid line shown in FIG. 3 shows the input image signal-recording density characteristic when pulse width modulation is performed and recording is performed by a laser beam printer. That is, the one having a relatively small input signal has a sharp rise in the density, and the one having a relatively large input signal has a characteristic that it grows only gently, and the characteristic is extremely poor in linearity. still,
The broken line in FIG. 3 shows an ideal input image signal-recording density characteristic. Therefore, in this embodiment, a different correction is performed for each line and the same correction is repeated for every three lines. That is, as shown in FIG. 4, the first line shows the relationship between the input and output of the correction circuit 6 in FIG.
The correction circuit 6 is constructed so that the above relationship is established, and the second and third lines have such relationships as shown in FIGS. 4 (b) and 4 (c), respectively.

FIG. 5 is an example of a pattern output using the configuration of this embodiment. FIG. 5 is a diagram showing an output pattern in the case where all pixels constituting one screen have the same level of input grayscale data by using the configuration of the present embodiment. Since each line undergoes different correction, it is shaded. Pulse width modulation as shown is performed. Further, as described above, the center position of dot growth is shifted by one pixel for each line.

In this embodiment, the pulse pattern is generated once every three picture element clocks, but it may be generated longer or shorter. Also, the addition and synthesis of the picture element data was performed every three picture elements,
The number of picture elements to be added and synthesized may be appropriately determined. This is determined in consideration of the response speed and resolution of the device.

Further, the generation cycle of the pulse pattern and the addition / synthesis cycle of the picture element data may be different from each other.

Further, the pulse pattern is configured to be shifted by one picture element for each line, but it may be shifted for more picture elements or may be performed without shifting at all. The growth pattern will be a vertical line if there is no deviation.

Further, although the same correction is repeated every three lines, the number of repeated lines may be appropriately determined. Alternatively, a plurality of pixels may be one block (one line includes one line), and a different γ correction is performed for each block, and the same correction may be repeated every predetermined number of blocks. Further, different correction may be performed for each pixel. Further, it may be configured so that the form of γ correction can be selected. That is, for example, if it is configured so that it can be moved and adjusted between points A and B in FIG. 4, more versatility occurs.

In addition, γ correction was performed after the addition and synthesis of pixel data.
The γ correction may be performed before the addition and synthesis.

[Effect]

As described above, according to the present invention, the added digital signal is added by the pattern signal having the dynamic range of the digital data added for each of the plurality of pixels and the matching amplitude and the plurality of pixel periods. Since the data is pulse-width modulated, the storability of the image density and the gradation of the reproduced image are improved, and the image reproducibility of the input digital data is improved.

Further, according to the present invention, it is possible to obtain a reproduced image of high quality with a simple structure.

The present invention can be applied to various image processing apparatuses such as facsimiles and laser beam printers.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining the image processing apparatus according to the present embodiment, FIG. 2 is a diagram showing waveforms of respective parts of the circuit shown in FIG. 1, and FIG. 3 is an input image signal without .gamma. Correction. FIG. 4 is a diagram showing a recording density characteristic, FIG. 4 is a diagram showing a relationship of .gamma. Correction for each line in the present embodiment, and FIG. In the figure, 1 is a digital data output device, 2 and 3 are latch circuits, 4 and 5 are addition circuits, 6 is a correction circuit, 7 is a D / A conversion circuit, 8 and 11 are amplification circuits, 9 is a comparison circuit, and 10 is a comparison circuit. Pulse pattern generation circuit, 12 is basic clock generator, 13, 14, 16
Is a counter, 17a to 17c are AND gates, and 17d is an OR gate.

Claims (1)

[Claims] 1. A digital data output means for continuously outputting digital data for each pixel; an addition means for adding digital data output from the digital data output means for each of a plurality of consecutive pixels; and the addition means. Pulse width modulation means for pulse-width modulating the digital data output from the addition means with a pattern signal having an amplitude matched with the dynamic range of the output digital data and having the plurality of pixel periods. An image processing device characterized by the above.