JPH0810899B2 - Digital gradation signal thinning circuit - Google Patents

Description

Detailed Description of the Invention

[Industrial applications]

The present invention relates to a thinning circuit for digital gradation signals for reproducing a picture image.

[Prior art]

There is a halftone dot method as a method of correcting a digital gradation signal when an image is reproduced from the digital gradation signal. FIG. 7 is an example of analog halftoning. In order to express the density of an image, the two-dimensional image data space is subdivided into fixed areas, and the data values within the divided areas are divided into dot sizes. It is to be replaced with the size of Sa. In FIG. 7, 4 dots are represented. FIG. 8 shows an example of digital halftone dot printing, which is implemented by comparing input data with a reference table and outputting the data. That is, if the value of the input data at the position corresponding to the data value at each position in the reference table is large, the output is a black dot, and conversely, if the value is equal or smaller, the output is a white dot. As shown in the example of FIG. 8, when each data value of the reference table is set such that the center position of the table is the smallest and the value is successively larger in a spiral manner, the output data has a constant input data value. If there are halftone dots. Then, the size of the halftone dot changes depending on the value of the input data, and in the case of the input data 1, the output data 1
In case of input data 2, it becomes output data 2. As described above, when the digital gradation signal is converted into halftone dots to reproduce the gradation, unlike the reproduction of the digital binary signal,
It has a characteristic that the output image does not deteriorate much even if the input digital gradation signal is thinned out to some extent. Taking advantage of this characteristic, the configuration of the gradation correction circuit is simplified,
Conventionally, the thinning processing of the input digital gradation signal is performed for the reason of increasing the processing speed. By the way, in this case, the simple thinning-out circuit has a drawback that the output image is affected by the fluctuation due to the non-uniformity of the input image itself, the non-uniformity due to the noise component, and the like, and the image quality is easily deteriorated. Therefore, conventionally, averaging processing is performed after thinning processing of digital gradation signals. FIG. 9 is an example of a conventional circuit of this type, and FIG. 10 is its timing chart. In this example, the thinning-out cycle is one kind. In this example, a digital gradation signal S1 consisting of data SI1, SI2, SI3 ...
(FIG. 10A) is supplied to the thinning circuit 12 to perform thinning processing for thinning one data every three data cycles. The output signal S2 of this thinning-out circuit 12 (B in the same figure)
Latch timing signal S3 synchronized with the decimation period from
It is latched in the latch circuit 14 by (C in the same figure). The output S4 of the latch circuit 14 (D in the figure) is the averaging circuit.
The output signal S2 of the thinning circuit 12 is supplied to the averaging circuit 15 and is subjected to the averaging calculation process of (S2 + S4) / 2, and from this averaging circuit 15, Y1, Y4, Y
An output signal S5 consisting of 7, ... Is obtained. here, Becomes

[Problems to be Solved by the Invention]

However, as described above, when the averaging processing is performed after the digital gradation signal thinning processing, the processing in the averaging circuit 15 is the averaging of the data sampled in the thinning circuit 12, and the thinning circuit 12 Data not sampled at does not participate in the averaging. For this reason, there is a drawback in that, among the non-uniformity of the input image itself, the non-uniformity due to the noise component, and the like, it is not possible to cancel the periodic gradation fluctuations peculiar to the input signal to the maximum extent. Also, when two types of thinning cycles are used in the thinning circuit, the output varies even with a constant gradation change that is not affected by the nonuniformity of the input image itself and the nonuniformity due to noise components. Has a drawback. The present invention aims to eliminate the above drawbacks.

[Means for Solving the Problems]

The digital gradation signal thinning-out circuit according to the present invention corresponds to the embodiment of FIG. 1 described later, and comprises delay means 22 for delaying the input digital gradation signal by a predetermined multiple of the data period, and delay means 22 for delaying the input digital gradation signal. An averaging circuit 24 for averaging the delayed signal and the input digital gradation signal, and a decimating circuit 25 for decimating the output signal of the averaging circuit 24. In the case where two kinds of thinning cycles, that is, a certain cycle and a cycle different from that by one data cycle are mixed, the delay time of the delay means 22 is set to be equal to one of the thinning cycles. .

[Action]

In the present invention, the averaging process of the input digital gradation signal and the signal delayed by the delay unit 22 is performed before the thinning process. In this case, the delay time of the delay means 22 is set equal to one of the first and second thinning periods. Since the first thinning cycle and the second thinning cycle are different by one data cycle, except for the timing for each least common multiple of the delay time in the delay means 22 and the thinning repeating cycle including the first and second cycles. In the averaging circuit 24, the data that is not sampled when the thinning process is performed before this averaging is averaged with the sampled data. Then, the thinning process is performed after the averaging.

【Example】

FIG. 1 is an embodiment of a thinning circuit for digital gradation signals according to the present invention, and FIG. 2 is a timing chart thereof. In this example, the thinning-out cycle is one type of 3, and the delay time in the delay means is one data cycle longer than the thinning-out cycle. In FIG. 1, reference numeral 21 denotes an input terminal, and the digital gradation signal D1 (FIG. 2A) followed by the data IN1, IN2, IN3, ... Through the input terminal 21 is supplied to the delay circuit 22. In this example, the delay circuit 22 has four latch circuits 22a, 22b, 22.
It consists of c and 22d. Then, through the terminal 23, the latch timing signal D2 (B in the figure) synchronized with the signal input timing of the input digital gradation signal D1 is supplied to each latch circuit 22a, 22b, 22.
The digital gradation signal D1 supplied to c, 22d is sequentially shifted to the latch circuits 22A, 22b, 22c, 22d,
The outputs D3 to D6 of a to 22d are as shown in FIGS. Therefore, the output D6 of the latch circuit 22d becomes the digital gradation signal four data before the input digital gradation signal D1. Then, the output D6 of the latch circuit 22d, that is, the output of the delay circuit 22 and the input digital gradation signal D1 are supplied to the averaging circuit 24, and the averaging processing of both outputs is performed. The output D7 of the averaging circuit 24 becomes data X1, X2, X3 ... As shown in FIG. Therefore, when the input digital gradation signal D1 is directly thinned out in one type of thinning-out cycle 3, data that is not sampled is also added to the averaging process. The output D7 of the averaging circuit 24 is supplied to the thinning circuit 25, and data is thinned out from the output D7 in a predetermined thinning pattern. From this, as shown in FIG. 2H, X1, X4, ...
The following output D8 is obtained. 3 and 4 are diagrams for comparison between the circuit system of the present invention and the conventional circuit system. FIG. 3 shows the input digital gradation signal D1, where the broken line is the ideal source analog signal, and the solid line is due to the non-uniformity and noise component of the input image itself when converting from analog signal to digital signal. It is a digital gradation signal added with non-uniformity and the like. In this case, the number of input gradations is 16 gradations (0 to 15). Further, in the figure, ◯ and ● are input signal points, and ● are sampling points of the thinning circuit, and the thinning cycle is one kind. FIG. 4 shows the difference between the output signal after the input digital gradation signal of FIG. 3 is corrected by the thinning circuit of the present invention and the output signal after being corrected by the two types of conventional circuit examples. is there. In FIG. 4,  ---  is an output by the circuit of the present invention. X1,
X4 ... Corresponds to the output D8 of the thinning circuit 25. X -...- X are outputs in the case of the conventional circuit example of the simple thinning circuit. □ ‥‥ □ is the output of a conventional circuit example that averages after thinning. Y1, Y4 ... are the outputs S5 of the averaging circuit 15 in FIG.
It corresponds to. In the case of the circuit of the present invention and the conventional circuit example of averaging after thinning, the timing is delayed by one sampling point in the circuit configuration. Comparing the output signals of the above circuits, it can be seen that the output signal of the circuit of the present invention is remarkably the closest to the ideal source analog signal in the section A shown in FIG. . Next, in the thinning circuit 25, when two types of thinning periods are mixed and the two types of thinning periods are different from one data period, for example, when the thinning period is a repetition of 3, 3, 4, delay In the circuit 22, three or four latch circuits are provided. As a result, the output that is not sampled when the input digital signal is directly thinned can be used for averaging in the averaging circuit 24, and the object of the present invention can be achieved. That is, for example, in the case where the thinning cycle is a repetition of 3, 3, 4, and the number of latch circuits in the delay circuit 22 is 4, 10 cycles of the thinning cycle and the delay circuit 22 For every 40 data cycles, which is the least common multiple of 4 data cycles, which is the delay cycle in, the averaging circuit uses the output sampled when the direct decimation processing is performed. The output that is not sampled when is used for averaging in the averaging circuit 24. In this case, according to the above-mentioned example, the delay time in the delay circuit 22 should correspond to two types of thinning periods, and should be two types of delay time different from each thinning period. It gets complicated. It is also possible to set one kind of delay time different from both thinning periods,
On the contrary, the result may defeat the initial purpose of the present invention. For example, when the thinning cycle is a repetition of 3, 3, 4, and when the delay time of the delay circuit 22 is 5 data cycles, the output sampled when the direct thinning processing is performed every 10 data cycles. Would be used in the averaging circuit. In this respect, in the case of the above-mentioned example, the thinning cycle of two types is 1
Since the delay time of the delay circuit 22 is set to one of the two types of thinning periods in consideration of the difference only in the data period, the configuration can be simplified as compared with the case of setting the two types of delay times. In addition, it is possible to maximize the opportunity to use the output that is not sampled when the direct decimation process is performed for the averaging in the averaging circuit 24. 5 and 6 are also diagrams for comparing the circuit system of the present invention with the conventional circuit system. FIG. 5 shows that the digital gradation input signal has a constant gradation change, and two thinning cycles are mixed. In this example, the number of input gradations is 22 gradations (0 to 21).
○, ● are input signal points, ● are sampling points of the thinning circuit, and the thinning cycle is a repetition of 3 ・ 3 ・ 4. FIG. 6 shows the difference between the output signals of the decimating circuit of the present invention and the conventional decimating and averaging circuit of the input digital gradation signal of FIG. In FIG. 6,  ---  is an output by the circuit of the present invention. □ -...- □ is the output from the circuit that averages after decimation. As is clear from the figure, the output of the circuit of the present invention is a straight line like the input signal, and fluctuations appear in the output of the conventional averaging circuit after decimation. As described above, by adopting the circuit of the present invention, it is possible to obtain a digital gradation signal output with high reproducibility in which the source analog signals are decimated in a more effective manner. Then, the present invention is a signal which is not sampled when the thinning process is performed first and which is not involved in averaging,
Since averaging is performed with the signal to be sampled, it is possible to select the delay amount in the delay circuit so that the optimum output can be obtained during averaging. That is, an optimum output can be obtained by changing the delay amount (corresponding to the number of latch circuits in the above example) adapted to the characteristic condition of the nonuniformity of the input signal, and similarly, the input / output condition ( For example, the optimum output can be obtained by changing the delay amount, that is, the number of latch circuits and the thinning pattern, which is adapted to the linear density difference between the input and output, the inherent periodic gradation variation of the input and output, etc. Is possible.

【The invention's effect】

As described above, according to the present invention, it is possible to average the output sampled and the non-sampled output when the input digital gradation signal is directly thinned out. Therefore, there is an effect that a high-quality output with high reproducibility can be obtained when the halftone processing is performed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a digital gradation signal thinning circuit according to the present invention, FIG. 2 is a timing chart for explaining the same, and FIGS. 3 and 4 are embodiments of the present invention. For comparing the output signal of the conventional circuit and the output signal of the conventional circuit, FIGS. 5 and 6 are for comparing the output signal of another embodiment of the present invention with the output signal of the conventional circuit. FIG. 7 is a diagram for explaining the analog halftone dot processing, FIG. 8 is a diagram for explaining the digital halftone dot processing, and FIG. 9 is a block diagram of a conventional circuit. The figure is a timing chart for the explanation. 22; delay circuit 22a, 22b, 22c, 22d; latch circuit 24; averaging circuit 25; thinning circuit

Claims (1)

[Claims] 1. A delay means for delaying an input digital gradation signal by a predetermined multiple of a data cycle, and an averaging circuit for averaging the signal delayed by the delay means and the input digital gradation signal. A thinning circuit that performs thinning processing on the output signal of the averaging circuit, wherein the thinning circuit has a first cycle in which the thinning cycle is an integral multiple of the data cycle, and the first cycle is 1 data. A second cycle having a different cycle is mixed, and the delay time of the delay means is the first cycle or the second cycle.
The thinning circuit for digital gradation signals is characterized in that it is selected to be equal to one of the periods.